From 927076dd7d662a71bf8decb0ee4792d73b4ac043 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 10 Jul 2020 16:16:12 +0100 Subject: [PATCH] do not set div result if overflow occurs --- src/soc/fu/div/output_stage.py | 51 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 6b5a42ec..b5b286a6 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -113,34 +113,35 @@ class DivOutputStage(PipeModBase): o = self.o.o.data - with m.Switch(op.insn_type): - with m.Case(InternalOp.OP_DIVE): - with m.If(op.is_32bit): - with m.If(op.is_signed): - # matches POWER9's divweo behavior - comb += o.eq(quotient_65[0:32].as_unsigned()) + with m.If(~ov): # result is valid (no overflow) + with m.Switch(op.insn_type): + with m.Case(InternalOp.OP_DIVE): + with m.If(op.is_32bit): + with m.If(op.is_signed): + # matches POWER9's divweo behavior + comb += o.eq(quotient_65[0:32].as_unsigned()) + with m.Else(): + comb += o.eq(quotient_65[0:32].as_unsigned()) with m.Else(): - comb += o.eq(quotient_65[0:32].as_unsigned()) - with m.Else(): - comb += o.eq(quotient_65) - with m.Case(InternalOp.OP_DIV): - with m.If(op.is_32bit): - with m.If(op.is_signed): - # matches POWER9's divwo behavior - comb += o.eq(quotient_65[0:32].as_unsigned()) + comb += o.eq(quotient_65) + with m.Case(InternalOp.OP_DIV): + with m.If(op.is_32bit): + with m.If(op.is_signed): + # matches POWER9's divwo behavior + comb += o.eq(quotient_65[0:32].as_unsigned()) + with m.Else(): + comb += o.eq(quotient_65[0:32].as_unsigned()) with m.Else(): - comb += o.eq(quotient_65[0:32].as_unsigned()) - with m.Else(): - comb += o.eq(quotient_65) - with m.Case(InternalOp.OP_MOD): - with m.If(op.is_32bit): - with m.If(op.is_signed): - # matches POWER9's modsw behavior - comb += o.eq(remainder_64[0:32].as_signed()) + comb += o.eq(quotient_65) + with m.Case(InternalOp.OP_MOD): + with m.If(op.is_32bit): + with m.If(op.is_signed): + # matches POWER9's modsw behavior + comb += o.eq(remainder_64[0:32].as_signed()) + with m.Else(): + comb += o.eq(remainder_64[0:32].as_unsigned()) with m.Else(): - comb += o.eq(remainder_64[0:32].as_unsigned()) - with m.Else(): - comb += o.eq(remainder_64) + comb += o.eq(remainder_64) ###### sticky overflow and context, both pass-through ##### -- 2.30.2