From 927b7c13a2e6af224178aa4de6843318eacf7bca Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 8 Jul 2019 08:57:05 +0200 Subject: [PATCH] soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) --- litex/soc/integration/soc_core.py | 2 -- litex/soc/integration/soc_sdram.py | 2 +- litex/soc/software/bios/boot.c | 4 ++-- litex/soc/software/bios/main.c | 8 ++++---- litex/soc/software/bios/sdram.c | 8 ++++---- litex/soc/software/libbase/system.c | 4 ++-- litex/soc/software/libbase/time.c | 2 +- litex/soc/software/libnet/microudp.c | 2 +- litex/tools/remote/csr_builder.py | 6 +++--- 9 files changed, 18 insertions(+), 20 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index b451ef80..835acef1 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -291,7 +291,6 @@ class SoCCore(Module): bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.add_csr_master(self.wishbone2csr.csr) self.config["CSR_DATA_WIDTH"] = csr_data_width - self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone) # Add UART @@ -312,7 +311,6 @@ class SoCCore(Module): self.submodules.identifier = identifier.Identifier(ident) self.add_csr("identifier_mem", allow_user_defined=True) self.config["CLOCK_FREQUENCY"] = int(clk_freq) - self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) # Add Timer if with_timer: diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 3e95c0c7..27e6f324 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -69,7 +69,7 @@ class SoCSDRAM(SoCCore): main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits + geom_settings.colbits)*phy.settings.databits//8 - self.add_constant("L2_SIZE", self.l2_size) + self.config["L2_SIZE"] = self.l2_size # add a Wishbone interface to the DRAM wb_sdram = wishbone.Interface() diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index 10064940..be7c9278 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -40,7 +40,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u flush_cpu_icache(); #endif flush_cpu_dcache(); -#ifdef L2_SIZE +#ifdef CONFIG_L2_SIZE flush_l2_cache(); #endif boot_helper(r1, r2, r3, addr); @@ -60,7 +60,7 @@ static int check_ack(void) timer0_en_write(0); timer0_reload_write(0); - timer0_load_write(SYSTEM_CLOCK_FREQUENCY/4); + timer0_load_write(CONFIG_CLOCK_FREQUENCY/4); timer0_en_write(1); timer0_update_value_write(1); recognized = 0; diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index 0c2fe189..95b439cb 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -314,7 +314,7 @@ static void do_command(char *c) else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c)); else if(strcmp(token, "ident") == 0) ident(); -#ifdef L2_SIZE +#ifdef CONFIG_L2_SIZE else if(strcmp(token, "flushl2") == 0) flush_l2_cache(); #endif #ifdef CSR_CTRL_BASE @@ -483,11 +483,11 @@ int main(int i, char **c) #else printf("Unknown"); #endif - printf(" @ %dMHz\n", SYSTEM_CLOCK_FREQUENCY/1000000); + printf(" @ %dMHz\n", CONFIG_CLOCK_FREQUENCY/1000000); printf("\e[1mROM\e[0m: %dKB\n", ROM_SIZE/1024); printf("\e[1mSRAM\e[0m: %dKB\n", SRAM_SIZE/1024); -#ifdef L2_SIZE - printf("\e[1mL2\e[0m: %dKB\n", L2_SIZE/1024); +#ifdef CONFIG_L2_SIZE + printf("\e[1mL2\e[0m: %dKB\n", CONFIG_L2_SIZE/1024); #endif #ifdef MAIN_RAM_SIZE printf("\e[1mMAIN-RAM\e[0m: %dKB\n", MAIN_RAM_SIZE/1024); diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index 0edc127c..b6aa5237 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -667,7 +667,7 @@ static int memtest_bus(void) array[i] = ONEZERO; } flush_cpu_dcache(); -#ifdef L2_SIZE +#ifdef CONFIG_L2_SIZE flush_l2_cache(); #endif for(i=0;i