From 92ab5cdd449dcb44781347c986365065af17ba74 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 13:06:12 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 0b01436de..4966f1e65 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -316,10 +316,20 @@ of the problem-space: All of these things come entirely from "Augmentation" of the Scalar operation being prefixed: at no time is the Scalar operation significantly altered. -From there, several more "Modes" can be added, including saturation, -which is needed for Audio and Video applications, "Reverse Gear" +From there, several more "Modes" can be added, including + +* saturation, +which is needed for Audio and Video applications +* "Reverse Gear" which runs the Element Loop in reverse order (needed for Prefix -Sum), and more. +Sum) +* Data-dependent Fail-First, which emerged from asking the simple + question, "If modern Vector ISAs have Load/Store Fail-First, + and the Power ISA has Condition Codes, why not make Conditional + early-exit from Arithmetic operation looping?" +* over 500 Branch-Conditional Modes emerge from application of + Boolean Logic in a Vector context, on top of an already-powerful + Scalar Branch-Conditional instruction. **What is missing from Power Scalar ISA that a Vector ISA needs?** -- 2.30.2