From 92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Tue, 25 Oct 2005 18:52:02 +0000 Subject: [PATCH] * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by making one a macro of the other. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. --- cpu/ChangeLog | 5 + cpu/m32c.cpu | 9 +- opcodes/ChangeLog | 10 ++ opcodes/m32c-asm.c | 3 - opcodes/m32c-desc.c | 26 +-- opcodes/m32c-desc.h | 411 ++++++++++++++++++++++---------------------- opcodes/m32c-dis.c | 3 - opcodes/m32c-ibld.c | 14 -- opcodes/m32c-opc.c | 23 ++- opcodes/m32c-opc.h | 2 +- 10 files changed, 246 insertions(+), 260 deletions(-) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 6ea2b0e4532..48311b21b3f 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2005-10-25 DJ Delorie + + * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by + making one a macro of the other. + 2005-10-21 DJ Delorie * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index 93d2bfe598b..9ac7d78b2a2 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -5997,10 +5997,10 @@ ;------------------------------------------------------------- (define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) - (dni (.sym op 16 -Q-sp) - (.str op ":Q #imm4,sp") + (dni (.sym op 16 -wQ-sp) + (.str op ".w:q #imm4,sp") ((machine 16)) - (.str op "${size}$Q #${Imm-12-s4},sp") + (.str op ".w$Q #${Imm-12-s4},sp") (+ opc1 opc2 opc3 Imm-12-s4) (sem QI Imm-12-s4 sp) ()) @@ -7123,6 +7123,9 @@ (binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) ; add.BW:Q #imm4,sp (m16 #7) (binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) +(dnmi add16-bQ-sp "add16-bQ-sp" () + "add.b:q #${Imm-12-s4},sp" + (emit add16-wQ-sp Imm-12-s4)) ; add.BW:G #imm,sp (m16 #6) (binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) ; add.BW:G src,dst (m16 #4 m32 #6) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2234e02eedb..89ca63d51e7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2005-10-25 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + 2005-10-25 Arnold Metselaar * configure.in: Add target architecture bfd_arch_z80. diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index fdd15141f76..1bfa926efdb 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -879,9 +879,6 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_A1 : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk); break; - case M32C_OPERAND_A1A0 : - errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & junk); - break; case M32C_OPERAND_AN16_PUSH_S : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1); break; diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index 01c521569b0..d75c9083d70 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -1422,10 +1422,6 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<f_4_1, 0); break; diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index bbf9a870352..f5c2dc32946 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -562,8 +562,6 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, break; case M32C_OPERAND_A1 : break; - case M32C_OPERAND_A1A0 : - break; case M32C_OPERAND_AN16_PUSH_S : errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); break; @@ -1711,8 +1709,6 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, break; case M32C_OPERAND_A1 : break; - case M32C_OPERAND_A1A0 : - break; case M32C_OPERAND_AN16_PUSH_S : length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); break; @@ -2822,9 +2818,6 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_A1 : value = 0; break; - case M32C_OPERAND_A1A0 : - value = 0; - break; case M32C_OPERAND_AN16_PUSH_S : value = fields->f_4_1; break; @@ -3406,9 +3399,6 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_A1 : value = 0; break; - case M32C_OPERAND_A1A0 : - value = 0; - break; case M32C_OPERAND_AN16_PUSH_S : value = fields->f_4_1; break; @@ -3995,8 +3985,6 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, break; case M32C_OPERAND_A1 : break; - case M32C_OPERAND_A1A0 : - break; case M32C_OPERAND_AN16_PUSH_S : fields->f_4_1 = value; break; @@ -4556,8 +4544,6 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, break; case M32C_OPERAND_A1 : break; - case M32C_OPERAND_A1A0 : - break; case M32C_OPERAND_AN16_PUSH_S : fields->f_4_1 = value; break; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 2ca538ea237..1ac88591bf2 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -7497,7 +7497,7 @@ static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Un 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } }; -static const CGEN_IFMT ifmt_add16_Q_sp ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = { 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } }; @@ -78714,11 +78714,11 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), 0 } }, & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 } }, -/* add${size}$Q #${Imm-12-s4},sp */ +/* add.w$Q #${Imm-12-s4},sp */ { { 0, 0, 0, 0 }, - { { MNEM, OP (SIZE), OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, - & ifmt_add16_Q_sp, { 0x7db0 } + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, + & ifmt_add16_wQ_sp, { 0x7db0 } }, /* add.b$G #${Imm-16-QI},sp */ { @@ -79682,6 +79682,10 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = #else #define F(f) & m32c_cgen_ifld_table[M32C_/**/f] #endif +static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + #undef F /* Each non-simple macro entry points to an array of expansion possibilities. */ @@ -79703,12 +79707,23 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = static const CGEN_IBASE m32c_cgen_macro_insn_table[] = { +/* add.b:q #${Imm-12-s4},sp */ + { + -1, "add16-bQ-sp", "add.b:q", 16, + { 0|A(ALIAS), { (1<