From 92f04eab106ec10fe9b1d154e7e61dd017a2f145 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 8 Jun 2013 14:45:28 +0200 Subject: [PATCH] Added "cd" and "ls" commands for convenience --- kernel/select.cc | 111 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/kernel/select.cc b/kernel/select.cc index fa1c3db02..1ab15c9a9 100644 --- a/kernel/select.cc +++ b/kernel/select.cc @@ -939,3 +939,114 @@ struct SelectPass : public Pass { } } SelectPass; +struct CdPass : public Pass { + CdPass() : Pass("cd", "a shortcut for 'select -module '") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" cd \n"); + log("\n"); + log("This is just a shortcut for 'select -module '.\n"); + log("\n"); + log("\n"); + log(" cd \n"); + log("\n"); + log("When no module with the specified name is found, but there is a cell\n"); + log("with the specified name in the current module, then this is equivialent\n"); + log("to 'cd '.\n"); + log("\n"); + log(" cd ..\n"); + log("\n"); + log("This is just a shortcut for 'select -clear'.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + if (args.size() != 2) + log_cmd_error("Invalid number of arguments.\n"); + + if (args[1] == "..") { + design->selection_stack.back() = RTLIL::Selection(true); + design->selected_active_module = std::string(); + return; + } + + std::string modname = RTLIL::escape_id(args[1]); + + if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) { + RTLIL::Module *module = NULL; + if (design->modules.count(design->selected_active_module) > 0) + module = design->modules.at(design->selected_active_module); + if (module != NULL && module->cells.count(modname) > 0) + modname = module->cells.at(modname)->type; + } + + if (design->modules.count(modname) > 0) { + design->selected_active_module = modname; + design->selection_stack.back() = RTLIL::Selection(); + select_filter_active_mod(design, design->selection_stack.back()); + design->selection_stack.back().optimize(design); + return; + } + + log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname)); + } +} CdPass; + +struct LsPass : public Pass { + LsPass() : Pass("ls", "list modules or objects in modules") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ls\n"); + log("\n"); + log("When no active module is selected, this prints a list of all module.\n"); + log("\n"); + log("When an active module is selected, this prints a list of objects in the module.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + if (args.size() != 1) + log_cmd_error("Invalid number of arguments.\n"); + + if (design->selected_active_module.empty()) + { + log("\n%d modules:\n", int(design->modules.size())); + for (auto &it : design->modules) + log(" %s\n", RTLIL::id2cstr(it.first)); + } + else + if (design->modules.count(design->selected_active_module) > 0) + { + RTLIL::Module *module = design->modules.at(design->selected_active_module); + + if (module->wires.size()) { + log("\n%d wires:\n", int(module->wires.size())); + for (auto &it : module->wires) + log(" %s\n", RTLIL::id2cstr(it.first)); + } + + if (module->memories.size()) { + log("\n%d memories:\n", int(module->memories.size())); + for (auto &it : module->memories) + log(" %s\n", RTLIL::id2cstr(it.first)); + } + + if (module->cells.size()) { + log("\n%d cells:\n", int(module->cells.size())); + for (auto &it : module->cells) + log(" %s\n", RTLIL::id2cstr(it.first)); + } + + if (module->processes.size()) { + log("\n%d processes:\n", int(module->processes.size())); + for (auto &it : module->processes) + log(" %s\n", RTLIL::id2cstr(it.first)); + } + } + } +} LsPass; + -- 2.30.2