From 92f24b784ddf822e39743288d331199a9691257a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 13 Dec 2011 14:08:39 +0100 Subject: [PATCH] wishbone: decoder: fix slave cyc generation in registered mode --- migen/bus/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py index bca7fce4..b464adea 100644 --- a/migen/bus/wishbone.py +++ b/migen/bus/wishbone.py @@ -113,7 +113,7 @@ class Decoder: # combine cyc with slave selection signals i = 0 for slave in self.slaves: - comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i])) + comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i])) i += 1 # generate master ack (resp. err) by ORing all slave acks (resp. errs) -- 2.30.2