From 930dd76d7472508ae57188bd0ef354ad5a039ff8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Jul 2020 15:25:27 +0100 Subject: [PATCH] move cia and msr to trap input record --- src/soc/fu/compunits/test/test_compunit.py | 9 ++++++--- src/soc/fu/test/common.py | 8 -------- src/soc/fu/trap/main_stage.py | 8 +++++--- src/soc/fu/trap/pipe_data.py | 3 +-- src/soc/fu/trap/test/test_pipe_caller.py | 13 +++++++++---- src/soc/fu/trap/trap_input_record.py | 2 ++ 6 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 19358176..0189f721 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -210,7 +210,8 @@ class TestRunner(FHDLTestCase): if self.funit == Function.LDST: yield from setup_test_memory(l0, sim) - index = sim.pc.CIA.value//4 + pc = sim.pc.CIA.value + index = pc//4 msr = sim.msr.value while True: print("instr index", index) @@ -224,7 +225,8 @@ class TestRunner(FHDLTestCase): # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(self.bigendian) # le / be? - yield pdecode2.msr.eq(msr) + yield pdecode2.msr.eq(msr) # set MSR "state" + yield pdecode2.cia.eq(pc) # set PC "state" yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.do.fn_unit @@ -270,7 +272,8 @@ class TestRunner(FHDLTestCase): # call simulated operation yield from sim.execute_one() yield Settle() - index = sim.pc.CIA.value//4 + pc = sim.pc.CIA.value + index = pc//4 msr = sim.msr.value # get all outputs (one by one, just "because") diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index dac8c170..036084e5 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -144,14 +144,6 @@ class ALUHelpers: print ("extra inputs: so", so) yield alu.p.data_i.xer_so.eq(so) - def set_msr(alu, dec2, inp): - if 'msr' in inp: - yield alu.p.data_i.msr.eq(inp['msr']) - - def set_cia(alu, dec2, inp): - if 'cia' in inp: - yield alu.p.data_i.cia.eq(inp['cia']) - def set_slow_spr1(alu, dec2, inp): if 'spr1' in inp: yield alu.p.data_i.spr1.eq(inp['spr1']) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index dfd75bef..5f711ff4 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -61,7 +61,8 @@ class TrapMainStage(PipeModBase): """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0 """ comb = m.d.comb - msr_i = self.i.msr + op = self.i.ctx.op + msr_i = op.msr nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1 # trap address @@ -85,7 +86,8 @@ class TrapMainStage(PipeModBase): may change in the future, hence the (unused) trap_addr argument """ comb = m.d.comb - msr_i, msr_o = self.i.msr, self.o.msr + op = self.i.ctx.op + msr_i, msr_o = op.msr, self.o.msr comb += msr_o.data.eq(msr_i) # copy msr, first, then modify comb += msr_o.data[MSR.SF].eq(1) comb += msr_o.data[MSR.EE].eq(0) @@ -108,7 +110,7 @@ class TrapMainStage(PipeModBase): op = self.i.ctx.op # convenience variables - a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr + a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, op.cia, op.msr srr0_i, srr1_i = self.i.srr0, self.i.srr1 o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia srr0_o, srr1_o = self.o.srr0, self.o.srr1 diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index d2de8552..de55cf2e 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -7,8 +7,7 @@ class TrapInputData(IntegerData): ('INT', 'rb', '0:63'), # RB/immediate ('FAST', 'fast1', '0:63'), # SRR0 ('FAST', 'fast2', '0:63'), # SRR1 - ('FAST', 'cia', '0:63'), # Program counter (current) - ('FAST', 'msr', '0:63')] # MSR + ] def __init__(self, pspec): super().__init__(pspec, False) # convenience diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index ed1f7089..15be93d1 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -48,8 +48,8 @@ def set_alu_inputs(alu, dec2, sim): yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR1 yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1 - yield from ALUHelpers.set_cia(alu, dec2, inp) - yield from ALUHelpers.set_msr(alu, dec2, inp) + #yield from ALUHelpers.set_cia(alu, dec2, inp) + #yield from ALUHelpers.set_msr(alu, dec2, inp) return inp # This test bench is a bit different than is usual. Initially when I @@ -218,12 +218,14 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) + msr = sim.msr.value pc = sim.pc.CIA.value + print ("starting msr, pc %08x, %08x"% (msr, pc)) index = pc//4 while index < len(instructions): ins, code = instructions[index] - print("pc %08x instr: %08x" % (pc, ins & 0xffffffff)) + print("pc %08x msr %08x instr: %08x" % (pc, msr, ins)) print(code) if 'XER' in sim.spr: so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 @@ -233,18 +235,21 @@ class TestRunner(FHDLTestCase): # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(bigendian) # little / big? + yield pdecode2.msr.eq(msr) # set MSR in pdecode2 + yield pdecode2.cia.eq(pc) # set CIA in pdecode2 yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.do.fn_unit self.assertEqual(fn_unit, Function.TRAP.value) alu_o = yield from set_alu_inputs(alu, pdecode2, sim) - yield pdecode2.msr.eq(alu_o['msr']) # set MSR in pdecode2 yield opname = code.split(' ')[0] yield from sim.call(opname) pc = sim.pc.CIA.value index = pc//4 print("pc after %08x" % (pc)) + msr = sim.msr.value + print("msr after %08x" % (msr)) vld = yield alu.n.valid_o while not vld: diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py index 111368ca..f7613790 100644 --- a/src/soc/fu/trap/trap_input_record.py +++ b/src/soc/fu/trap/trap_input_record.py @@ -13,6 +13,8 @@ class CompTrapOpSubset(CompOpSubsetBase): layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), + ('msr', 64), # TODO: "state" in separate Record + ('cia', 64), # likewise ('is_32bit', 1), ('traptype', 5), # see trap main_stage.py and PowerDecoder2 ('trapaddr', 13), -- 2.30.2