From 932475a29b07e0f5c958b35bc0e30751bebc7ef0 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Thu, 25 Jul 2019 08:43:35 +0200 Subject: [PATCH] cpu/vexriscv: bump submodule --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 747a2e01..854f9bd2 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 747a2e012f43d13c3487acc3c758477aad277559 +Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004 -- 2.30.2