From 9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 3 Jun 2020 14:35:27 +0000 Subject: [PATCH] RTLIL: factor out RTLIL::Module::addMemory. NFC. --- kernel/rtlil.cc | 12 ++++++++++++ kernel/rtlil.h | 2 ++ passes/techmap/flatten.cc | 8 +------- passes/techmap/techmap.cc | 8 +------- 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ca4201b53..dc1add0ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1884,6 +1884,18 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth return cell; } +RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other) +{ + RTLIL::Memory *mem = new RTLIL::Memory; + mem->name = name; + mem->width = other->width; + mem->start_offset = other->start_offset; + mem->size = other->size; + mem->attributes = other->attributes; + memories[mem->name] = mem; + return mem; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8228523d5..8d2e42b42 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1170,6 +1170,8 @@ public: RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 605759bec..dbea12dca 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -79,15 +79,9 @@ struct FlattenWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9c0402e0f..535db9465 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -174,15 +174,9 @@ struct TechmapWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } -- 2.30.2