From 933a46dfa573f3ec5eddf6918d1825795e04043e Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 5 Jul 2020 19:13:26 -0300 Subject: [PATCH] Implement sender. --- src/soc/experiment/alu_hier.py | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index b98a39fb..c4d5305b 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -14,7 +14,7 @@ from nmigen.hdl.rec import Record, Layout from nmigen.cli import main from nmigen.cli import verilog, rtlil from nmigen.compat.sim import run_simulation -from nmigen.back.pysim import Simulator +from nmigen.back.pysim import Simulator, Settle from soc.decoder.power_enums import InternalOp, Function, CryIn @@ -386,7 +386,6 @@ class BranchALU(Elaboratable): return list(self) def run_op(dut, a, b, op, inv_a=0): - from nmigen.back.pysim import Settle yield dut.a.eq(a) yield dut.b.eq(b) yield dut.op.insn_type.eq(op) @@ -475,18 +474,35 @@ def test_alu(): def test_alu_parallel(): m = Module() - m.submodules.alu = alu = ALU(width=16) + m.submodules.alu = dut = ALU(width=16) sim = Simulator(m) sim.add_clock(1e-6) - def process(): - yield + def send(a, b, op, inv_a=0): + yield dut.a.eq(a) + yield dut.b.eq(b) + yield dut.op.insn_type.eq(op) + yield dut.op.invert_a.eq(inv_a) + yield dut.p.valid_i.eq(1) + yield Settle() + while True: + rdy = yield dut.p.ready_o + if rdy: + break + yield + + def producer(): + yield from send(5, 3, InternalOp.OP_ADD) + + def consumer(): + yield dut.n.ready_i.eq(1) - sim.add_sync_process(process) + sim.add_sync_process(producer) + sim.add_sync_process(consumer) sim_writer = sim.write_vcd( "test_alu_parallel.vcd", "test_alu_parallel.gtkw", - traces=alu.ports() + traces=dut.ports() ) with sim_writer: sim.run() -- 2.30.2