From 934ee74bc0d04b866968f3aba0dc16fe7bccb1d9 Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Sun, 6 Aug 2023 01:37:05 +0000 Subject: [PATCH] RISC-V: Fix opcode entries of "vmsge{,u}.vx" Their check_func should be "match_never", not "match_opcode". The reasons this error did not cause any disassembler errors are: 1. The problem will not reproduce if "no-aliases" is specified (because macro instructions are handled as aliases). 2. If not, all affected compressed instructions or their aliases precede before "vmsge{,u}.vx" macro instructions. However, it'll easily break if we reorder opcode entries. This commit fixes this issue before the *accident* occurs. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Make sure that we never match to vmsge{,u}.vx instructions unless specified in the assembler. --- opcodes/riscv-opc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 3efab9a407d..f9e5ded3a6e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1606,10 +1606,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS }, {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS }, -{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_opcode, INSN_MACRO }, -{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_opcode, INSN_MACRO }, -{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_opcode, INSN_MACRO }, -{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_opcode, INSN_MACRO }, +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO }, +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO }, {"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0}, {"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0}, -- 2.30.2