From 93613b3c43964a39ab7cf1caaa205e40f9975e6a Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 May 2019 08:52:01 +0100
Subject: [PATCH] add global pending collator

---
 src/scoreboard/{int_fn_unit.py => fn_unit.py} |  6 +-
 src/scoreboard/global_pending.py              | 93 +++++++++++++++++++
 2 files changed, 96 insertions(+), 3 deletions(-)
 rename src/scoreboard/{int_fn_unit.py => fn_unit.py} (98%)
 create mode 100644 src/scoreboard/global_pending.py

diff --git a/src/scoreboard/int_fn_unit.py b/src/scoreboard/fn_unit.py
similarity index 98%
rename from src/scoreboard/int_fn_unit.py
rename to src/scoreboard/fn_unit.py
index 70393fc9..304ce3f9 100644
--- a/src/scoreboard/int_fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -7,8 +7,8 @@ from nmigen.lib.coding import Decoder
 from shadow_fn import ShadowFn
 
 
-class IntFnUnit(Elaboratable):
-    """ implements 11.4.8 integer function unit, p31
+class FnUnit(Elaboratable):
+    """ implements 11.4.8 function unit, p31
         also implements optional shadowing 11.5.1, p55
 
         shadowing can be used for branches as well as exceptions (interrupts),
@@ -171,7 +171,7 @@ def int_fn_unit_sim(dut):
     yield
 
 def test_int_fn_unit():
-    dut = IntFnUnit(32, 2)
+    dut = FnUnit(32, 2)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_int_fn_unit.il", "w") as f:
         f.write(vl)
diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
new file mode 100644
index 00000000..50e43378
--- /dev/null
+++ b/src/scoreboard/global_pending.py
@@ -0,0 +1,93 @@
+from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+from nmigen import Module, Signal, Cat, Elaboratable
+from nmutil.latch import SRLatch
+from nmigen.lib.coding import Decoder
+
+
+class GlobalPending(Elaboratable):
+    """ implements Global Pending Vector, basically ORs all incoming Function
+        Unit vectors together.  Can be used for creating Read or Write Global
+        Pending.  Can be used for INT or FP Global Pending.
+
+        Inputs:
+        * :wid:       register file width
+        * :fu_vecs:   a python list of function unit "pending" vectors, each
+                      vector being a Signal of width equal to the reg file.
+
+        Notes:
+
+        * the regfile may be Int or FP, this code doesn't care which.
+          obviously do not try to put in a mixture of regfiles into fu_vecs.
+        * this code also doesn't care if it's used for Read Pending or Write
+          pending, it can be used for both: again, obviously, do not try to
+          put in a mixture of read *and* write pending vectors in.
+        * if some Function Units happen not to be uniform (don't operate
+          on a particular register (extremely unusual), they must set a Const
+          zero bit in the vector.
+    """
+    def __init__(self, wid, fu_vecs):
+        self.reg_width = wid
+        # inputs
+        self.fu_vecs = fu_vecs
+        for v in fu_vecs:
+            assert len(v) == wid, "FU Vector must be same width as regfile"
+
+        self.g_pend_o = Signal(wid, reset_less=True)  # global pending vector
+
+    def elaborate(self, platform):
+        m = Module()
+
+        pend_l = []
+        for i in range(self.reg_width): # per-register
+            vec_bit_l = []
+            for v in self.fu_vecs:
+                vec_bit_l.append(v[i])             # fu bit for same register
+            pend_l.append(Cat(*vec_bit_l).bool())  # OR all bits for same reg
+        m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+
+        return m
+
+    def __iter__(self):
+        yield from self.fu_vecs
+        yield self.g_pend_o
+
+    def ports(self):
+        return list(self)
+
+
+def g_vec_sim(dut):
+    yield dut.dest_i.eq(1)
+    yield dut.issue_i.eq(1)
+    yield
+    yield dut.issue_i.eq(0)
+    yield
+    yield dut.src1_i.eq(1)
+    yield dut.issue_i.eq(1)
+    yield
+    yield
+    yield
+    yield dut.issue_i.eq(0)
+    yield
+    yield dut.go_read_i.eq(1)
+    yield
+    yield dut.go_read_i.eq(0)
+    yield
+    yield dut.go_write_i.eq(1)
+    yield
+    yield dut.go_write_i.eq(0)
+    yield
+
+def test_g_vec():
+    vecs = []
+    for i in range(3):
+        vecs.append(Signal(32, name="fu%d" % i))
+    dut = GlobalPending(32, vecs)
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("test_global_pending.il", "w") as f:
+        f.write(vl)
+
+    run_simulation(dut, g_vec_sim(dut), vcd_name='test_global_pending.vcd')
+
+if __name__ == '__main__':
+    test_g_vec()
-- 
2.30.2