From 936798bf6e272b26c149021fc558de44922ebae1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Apr 2022 13:49:01 +0100 Subject: [PATCH] add second hyperram module, for arty-a7, which does not break things --- src/ls2.py | 49 ++++++++++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 38110d0..5a35a8d 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -590,11 +590,14 @@ class DDR3SoC(SoC, Elaboratable): # HyperRAM modules *plural*. Assumes using a Quad PMOD by Piotr # Esden, sold by 1bitsquared, only doing one CS_N enable at the # moment - if hyperram_pins is not None: - self.hyperram = HyperRAM(io=hyperram_pins, phy_kls=HyperRAMPHY, - features={'stall'}, - latency=7) # Winbond W956D8MBYA - self._decoder.add(self.hyperram.bus, addr=hyperram_addr) + self.hyperram = [] + for i, (pins, hraddr) in enumerate(zip(hyperram_pins, hyperram_addr)): + hr = HyperRAM(io=pins, phy_kls=HyperRAMPHY, + name="hyperram%d" % i, + features={'stall'}, + latency=7) # Winbond W956D8MBYA + self._decoder.add(hr.bus, addr=hraddr) + self.hyperram.append(hr) self.memory_map = self._decoder.bus.memory_map @@ -683,13 +686,13 @@ class DDR3SoC(SoC, Elaboratable): self.drambone_async_br.add_verilog_source(fname, platform) # add hyperram module - if hasattr(self, "hyperram"): - m.submodules.hyperram = hyperram = self.hyperram + for i, hr in enumerate(self.hyperram): + m.submodules["hyperram%d" % i] = hr # grrr, same problem with hyperram: not WB4-pipe compliant - comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack) - # set 3 top CSn lines to zero for now + comb += hr.bus.stall.eq(hr.bus.cyc & ~hr.bus.ack) + # reset if self.fpga == 'arty_a7': - comb += hyperram.phy.rst_n.eq(ResetSignal()) + comb += hr.phy.rst_n.eq(ResetSignal()) # add blinky lights so we know FPGA is alive if platform is not None: @@ -811,7 +814,7 @@ class DDR3SoC(SoC, Elaboratable): def build_platform(fpga, firmware): - # create a platform selected from the toolchain. + # create a platform selected from the toolchain. platform_kls = {'versa_ecp5': VersaECP5Platform, 'versa_ecp5_85': VersaECP5Platform85, 'ulx3s': ULX3S_85F_Platform, @@ -902,7 +905,7 @@ def build_platform(fpga, firmware): # get DDR resource pins, disable if clock frequency is below 50 mhz for now ddr_pins = None if (enable_dram and platform is not None and - fpga in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']): + fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']): # not yet 'arty_a7', ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, xdr={"rst": 4, "clk":4, "a":4, @@ -992,26 +995,33 @@ def build_platform(fpga, firmware): print ("ethmac pins", ethmac_0_pins) # Get HyperRAM pins - hyperram_pins = None + hyperram_pins = [] if platform is None: - hyperram_pins = HyperRAMPads() + hyperram_pins = [HyperRAMPads()] elif fpga in ['isim']: hyperram_ios = HyperRAMResource(0, cs_n="B13", dq="E14 C10 B10 E12 D12 A9 D11 D14", rwds="C14", rst_n="E13", ck_p="D13", attrs=Attrs(IO_TYPE="LVCMOS33")) platform.add_resources(hyperram_ios) - hyperram_pins = platform.request("hyperram") + hyperram_pins = [platform.request("hyperram")] print ("isim a7 hyperram", hyperram_ios) # Digilent Arty A7-100t elif platform is not None and fpga in ['arty_a7']: - hyperram_ios = HyperRAMResource(0, cs_n="V12 V14 U12 U14", + hyperram_ios = HyperRAMResource(0, cs_n="B11 B18 G13 D13", + dq="E15 E16 D15 C15 J15 K15 J18 J17", + rwds="K16", rst_n="A18", ck_p="A11", + # ck_n="D12" - for later (DDR) + attrs=Attrs(IOSTANDARD="LVCMOS33")) + platform.add_resources(hyperram_ios) + hyperram_ios = HyperRAMResource(1, cs_n="V12 V14 U12 U14", dq="D4 D3 F4 F3 G2 H2 D2 E2", rwds="U13", rst_n="T13", ck_p="V10", # ck_n="V11" - for later (DDR) attrs=Attrs(IOSTANDARD="LVCMOS33")) platform.add_resources(hyperram_ios) - hyperram_pins = platform.request("hyperram") + hyperram_pins = [platform.request("hyperram", 0), + platform.request("hyperram", 1)] print ("arty a7 hyperram", hyperram_ios) # VERSA ECP5 elif False and platform is not None and fpga in \ @@ -1021,7 +1031,7 @@ def build_platform(fpga, firmware): rwds="C14", rst_n="E13", ck_p="D13", attrs=Attrs(IO_TYPE="LVCMOS33")) platform.add_resources(hyperram_ios) - hyperram_pins = platform.request("hyperram") + hyperram_pins = [platform.request("hyperram")] print ("versa ecp5 hyperram", hyperram_ios) print ("hyperram pins", hyperram_pins) @@ -1035,7 +1045,8 @@ def build_platform(fpga, firmware): spi0_cfg_addr=0xc0006000, # SPI0_CTRL_BASE eth0_cfg_addr=0xc000c000, # ETH0_CTRL_BASE (4k) eth0_irqno=1, # ETH0_IRQ number (match microwatt) - hyperram_addr=0xa0000000, # HYPERRAM_BASE + hyperram_addr=[0xa0000000, # HYPERRAM_BASE1 + 0xa2000000], # HYPERRAM_BASE2 fw_addr=fw_addr, #fw_addr=None, ddr_pins=ddr_pins, -- 2.30.2