From 936a9d57b3520c297b81222edce14712c0b846ee Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Mar 2021 07:18:29 +0000
Subject: [PATCH] aaagh found bug in litex setup, 64 bit WB bus was truncated

---
 experiments9/non_generated/full_core_ls180.il | 29248 ++++++++--------
 1 file changed, 14234 insertions(+), 15014 deletions(-)

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index d757b00..b1f7178 100644
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -238711,1550 +238711,1464 @@ module \logical_pipe2
   connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
   connect \output_muxid \muxid
 end
-attribute \src "ls180.v:4.1-5982.10"
+attribute \src "ls180.v:4.1-5951.10"
 attribute \cells_not_processed 1
 module \ls180
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 3 $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 25 $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 25 $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 3 $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 25 $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 3 $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 25 $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 3 $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 25 $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 4 $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 10 $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 4 $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 10 $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619
-  attribute \src "ls180.v:3964.1-3980.4"
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 3 $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 25 $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 25 $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 3 $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 3 $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 3 $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 4 $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 4 $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539
+  attribute \src "ls180.v:3949.1-3965.4"
   wire width 2 $0\array_muxed0[1:0]
-  attribute \src "ls180.v:3981.1-3997.4"
+  attribute \src "ls180.v:3966.1-3982.4"
   wire width 13 $0\array_muxed1[12:0]
-  attribute \src "ls180.v:3998.1-4014.4"
+  attribute \src "ls180.v:3983.1-3999.4"
   wire $0\array_muxed2[0:0]
-  attribute \src "ls180.v:4015.1-4031.4"
+  attribute \src "ls180.v:4000.1-4016.4"
   wire $0\array_muxed3[0:0]
-  attribute \src "ls180.v:4032.1-4048.4"
+  attribute \src "ls180.v:4017.1-4033.4"
   wire $0\array_muxed4[0:0]
-  attribute \src "ls180.v:4049.1-4065.4"
+  attribute \src "ls180.v:4034.1-4050.4"
   wire $0\array_muxed5[0:0]
-  attribute \src "ls180.v:4066.1-4082.4"
+  attribute \src "ls180.v:4051.1-4067.4"
   wire $0\array_muxed6[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\cmd_consumed[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire $0\converter0_counter[0:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\converter0_counter_subfragments_converter0_next_value[0:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\converter0_counter_subfragments_converter0_next_value_ce[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire width 64 $0\converter0_dat_r[63:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\converter0_skip[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire $0\converter1_counter[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\converter1_counter_subfragments_converter1_next_value[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\converter1_counter_subfragments_converter1_next_value_ce[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire width 64 $0\converter1_dat_r[63:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\converter1_skip[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\converter_counter[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\converter_counter_subfragments_next_value[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\converter_counter_subfragments_next_value_ce[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\converter_dat_r[31:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\converter_skip[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 16 $0\dfi_p0_rddata[15:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\dfi_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 36 $0\dummy[35:0]
-  attribute \src "ls180.v:1506.1-1511.4"
+  attribute \src "ls180.v:1499.1-1504.4"
   wire width 3 $0\eint_tmp[2:0]
-  attribute \src "ls180.v:2918.1-2922.4"
+  attribute \src "ls180.v:2903.1-2907.4"
   wire width 2 $0\eventmanager_pending_w[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\eventmanager_re[0:0]
-  attribute \src "ls180.v:2907.1-2911.4"
+  attribute \src "ls180.v:2892.1-2896.4"
   wire width 2 $0\eventmanager_status_w[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\eventmanager_storage[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\gpio0_oe_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\gpio0_oe_storage[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\gpio0_out_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\gpio0_out_storage[7:0]
-  attribute \src "ls180.v:2986.1-2996.4"
+  attribute \src "ls180.v:2971.1-2981.4"
   wire width 8 $0\gpio0_pads_gpio0i[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio0_pads_gpio0o[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio0_pads_gpio0oe[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio0_status[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\gpio1_oe_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\gpio1_oe_storage[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\gpio1_out_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\gpio1_out_storage[7:0]
-  attribute \src "ls180.v:2997.1-3007.4"
+  attribute \src "ls180.v:2982.1-2992.4"
   wire width 8 $0\gpio1_pads_gpio1i[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio1_pads_gpio1o[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio1_pads_gpio1oe[7:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 8 $0\gpio1_status[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\i2c_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\i2c_storage[2:0]
-  attribute \src "ls180.v:4189.1-4191.4"
+  attribute \src "ls180.v:4174.1-4176.4"
   wire $0\int_rst[0:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\interface0_converted_interface_ack[0:0]
-  attribute \src "ls180.v:212.5-212.46"
-  wire $0\interface0_converted_interface_err[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\interface1_converted_interface_ack[0:0]
-  attribute \src "ls180.v:227.5-227.46"
-  wire $0\interface1_converted_interface_err[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_bus_errors[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire $0\libresocsim_converter0_counter[0:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire width 64 $0\libresocsim_converter0_dat_r[63:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_converter0_skip[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire $0\libresocsim_converter1_counter[0:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire width 64 $0\libresocsim_converter1_dat_r[63:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_converter1_skip[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire $0\libresocsim_converter2_counter[0:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
+  wire width 64 $0\libresocsim_converter2_dat_r[63:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_converter2_skip[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 20 $0\libresocsim_count[19:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_en_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_en_storage[0:0]
-  attribute \src "ls180.v:3164.1-3175.4"
+  attribute \src "ls180.v:3149.1-3160.4"
   wire $0\libresocsim_error[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_eventmanager_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_eventmanager_storage[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\libresocsim_grant[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire width 30 $0\libresocsim_interface0_converted_interface_adr[29:0]
+  attribute \src "ls180.v:152.11-152.64"
+  wire width 2 $0\libresocsim_interface0_converted_interface_bte[1:0]
+  attribute \src "ls180.v:151.11-151.64"
+  wire width 3 $0\libresocsim_interface0_converted_interface_cti[2:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_interface0_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:1520.1-1530.4"
+  wire width 32 $0\libresocsim_interface0_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire width 4 $0\libresocsim_interface0_converted_interface_sel[3:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_interface0_converted_interface_stb[0:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_interface0_converted_interface_we[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire width 30 $0\libresocsim_interface1_converted_interface_adr[29:0]
+  attribute \src "ls180.v:167.11-167.64"
+  wire width 2 $0\libresocsim_interface1_converted_interface_bte[1:0]
+  attribute \src "ls180.v:166.11-166.64"
+  wire width 3 $0\libresocsim_interface1_converted_interface_cti[2:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_interface1_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:1580.1-1590.4"
+  wire width 32 $0\libresocsim_interface1_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire width 4 $0\libresocsim_interface1_converted_interface_sel[3:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_interface1_converted_interface_stb[0:0]
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_interface1_converted_interface_we[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire width 30 $0\libresocsim_interface2_converted_interface_adr[29:0]
+  attribute \src "ls180.v:182.11-182.64"
+  wire width 2 $0\libresocsim_interface2_converted_interface_bte[1:0]
+  attribute \src "ls180.v:181.11-181.64"
+  wire width 3 $0\libresocsim_interface2_converted_interface_cti[2:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_interface2_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:1640.1-1650.4"
+  wire width 32 $0\libresocsim_interface2_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire width 4 $0\libresocsim_interface2_converted_interface_sel[3:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_interface2_converted_interface_stb[0:0]
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_interface2_converted_interface_we[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:3008.1-3026.4"
+  attribute \src "ls180.v:2993.1-3011.4"
   wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
-  attribute \src "ls180.v:3027.1-3045.4"
+  attribute \src "ls180.v:3012.1-3030.4"
   wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 13 $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire width 16 $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
-  attribute \src "ls180.v:4193.1-4298.4"
+  attribute \src "ls180.v:4178.1-4283.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
-  attribute \src "ls180.v:134.5-134.64"
+  attribute \src "ls180.v:136.5-136.64"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
-  attribute \src "ls180.v:136.5-136.65"
+  attribute \src "ls180.v:138.5-138.65"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
-  attribute \src "ls180.v:135.5-135.65"
+  attribute \src "ls180.v:137.5-137.65"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
-  attribute \src "ls180.v:121.5-121.58"
+  attribute \src "ls180.v:116.5-116.58"
   wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
-  attribute \src "ls180.v:65.11-65.47"
-  wire width 2 $0\libresocsim_libresoc_dbus_bte[1:0]
-  attribute \src "ls180.v:64.11-64.47"
-  wire width 3 $0\libresocsim_libresoc_dbus_cti[2:0]
-  attribute \src "ls180.v:76.11-76.47"
-  wire width 2 $0\libresocsim_libresoc_ibus_bte[1:0]
-  attribute \src "ls180.v:75.11-75.47"
-  wire width 3 $0\libresocsim_libresoc_ibus_cti[2:0]
-  attribute \src "ls180.v:1518.1-1525.4"
+  attribute \src "ls180.v:1592.1-1638.4"
+  wire $0\libresocsim_libresoc_dbus_ack[0:0]
+  attribute \src "ls180.v:64.5-64.41"
+  wire $0\libresocsim_libresoc_dbus_err[0:0]
+  attribute \src "ls180.v:1532.1-1578.4"
+  wire $0\libresocsim_libresoc_ibus_ack[0:0]
+  attribute \src "ls180.v:73.5-73.41"
+  wire $0\libresocsim_libresoc_ibus_err[0:0]
+  attribute \src "ls180.v:1511.1-1518.4"
   wire width 16 $0\libresocsim_libresoc_interrupt[15:0]
-  attribute \src "ls180.v:105.11-105.50"
-  wire width 2 $0\libresocsim_libresoc_jtag_wb_bte[1:0]
-  attribute \src "ls180.v:104.11-104.50"
-  wire width 3 $0\libresocsim_libresoc_jtag_wb_cti[2:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire width 30 $0\libresocsim_libresoc_xics_icp_adr[29:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\libresocsim_libresoc_xics_icp_cyc[0:0]
-  attribute \src "ls180.v:1527.1-1537.4"
-  wire width 32 $0\libresocsim_libresoc_xics_icp_dat_w[31:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire width 4 $0\libresocsim_libresoc_xics_icp_sel[3:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\libresocsim_libresoc_xics_icp_stb[0:0]
-  attribute \src "ls180.v:1539.1-1585.4"
-  wire $0\libresocsim_libresoc_xics_icp_we[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire width 30 $0\libresocsim_libresoc_xics_ics_adr[29:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\libresocsim_libresoc_xics_ics_cyc[0:0]
-  attribute \src "ls180.v:1587.1-1597.4"
-  wire width 32 $0\libresocsim_libresoc_xics_ics_dat_w[31:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire width 4 $0\libresocsim_libresoc_xics_ics_sel[3:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\libresocsim_libresoc_xics_ics_stb[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
-  wire $0\libresocsim_libresoc_xics_ics_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1652.1-1698.4"
+  wire $0\libresocsim_libresoc_jtag_wb_ack[0:0]
+  attribute \src "ls180.v:104.5-104.44"
+  wire $0\libresocsim_libresoc_jtag_wb_err[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 14 $0\libresocsim_libresocsim_adr[13:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
-  attribute \src "ls180.v:1074.5-1074.59"
-  wire $0\libresocsim_libresocsim_converted_interface_ack[0:0]
-  attribute \src "ls180.v:1070.12-1070.69"
-  wire width 64 $0\libresocsim_libresocsim_converted_interface_dat_r[63:0]
-  attribute \src "ls180.v:1078.5-1078.59"
-  wire $0\libresocsim_libresocsim_converted_interface_err[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\libresocsim_libresocsim_dat_w[7:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_libresocsim_we[0:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire $0\libresocsim_libresocsim_wishbone_ack[0:0]
-  attribute \src "ls180.v:1060.12-1060.56"
-  wire width 30 $0\libresocsim_libresocsim_wishbone_adr[29:0]
-  attribute \src "ls180.v:1064.5-1064.48"
-  wire $0\libresocsim_libresocsim_wishbone_cyc[0:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0]
-  attribute \src "ls180.v:1061.12-1061.58"
-  wire width 32 $0\libresocsim_libresocsim_wishbone_dat_w[31:0]
-  attribute \src "ls180.v:1063.11-1063.54"
-  wire width 4 $0\libresocsim_libresocsim_wishbone_sel[3:0]
-  attribute \src "ls180.v:1065.5-1065.48"
-  wire $0\libresocsim_libresocsim_wishbone_stb[0:0]
-  attribute \src "ls180.v:1067.5-1067.47"
-  wire $0\libresocsim_libresocsim_wishbone_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1071.5-1071.48"
+  wire $0\libresocsim_libresocsim_wishbone_err[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_load_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_load_storage[31:0]
-  attribute \src "ls180.v:3050.1-3086.4"
+  attribute \src "ls180.v:3035.1-3071.4"
   wire width 2 $0\libresocsim_next_state[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_ram_bus_ack[0:0]
-  attribute \src "ls180.v:155.5-155.35"
+  attribute \src "ls180.v:198.5-198.35"
   wire $0\libresocsim_ram_bus_err[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_reload_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_reload_storage[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_reset_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_reset_storage[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_scratch_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_scratch_storage[31:0]
-  attribute \src "ls180.v:3164.1-3175.4"
+  attribute \src "ls180.v:3149.1-3160.4"
   wire $0\libresocsim_shared_ack[0:0]
-  attribute \src "ls180.v:3164.1-3175.4"
+  attribute \src "ls180.v:3149.1-3160.4"
   wire width 32 $0\libresocsim_shared_dat_r[31:0]
-  attribute \src "ls180.v:3105.1-3113.4"
+  attribute \src "ls180.v:3090.1-3098.4"
   wire width 6 $0\libresocsim_slave_sel[5:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 6 $0\libresocsim_slave_sel_r[5:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\libresocsim_state[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_update_value_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_update_value_storage[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_value[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\libresocsim_value_status[31:0]
-  attribute \src "ls180.v:1708.1-1718.4"
-  wire width 8 $0\libresocsim_we[7:0]
-  attribute \src "ls180.v:1724.1-1729.4"
+  attribute \src "ls180.v:1701.1-1707.4"
+  wire width 4 $0\libresocsim_we[3:0]
+  attribute \src "ls180.v:1713.1-1718.4"
   wire $0\libresocsim_zero_clear[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_zero_old_trigger[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\libresocsim_zero_pending[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire width 30 $0\litedram_wb_adr[29:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\litedram_wb_cyc[0:0]
-  attribute \src "ls180.v:2798.1-2808.4"
+  attribute \src "ls180.v:2783.1-2793.4"
   wire width 16 $0\litedram_wb_dat_w[15:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire width 2 $0\litedram_wb_sel[1:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\litedram_wb_stb[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\litedram_wb_we[0:0]
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $0\memadr[5:0]
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $0\memadr_1[3:0]
-  attribute \src "ls180.v:5566.1-5570.4"
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $0\memadr[6:0]
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $0\memadr_1[4:0]
+  attribute \src "ls180.v:5535.1-5539.4"
   wire width 25 $0\memdat[24:0]
-  attribute \src "ls180.v:5580.1-5584.4"
+  attribute \src "ls180.v:5549.1-5553.4"
   wire width 25 $0\memdat_1[24:0]
-  attribute \src "ls180.v:5594.1-5598.4"
+  attribute \src "ls180.v:5563.1-5567.4"
   wire width 25 $0\memdat_2[24:0]
-  attribute \src "ls180.v:5608.1-5612.4"
+  attribute \src "ls180.v:5577.1-5581.4"
   wire width 25 $0\memdat_3[24:0]
-  attribute \src "ls180.v:5623.1-5627.4"
+  attribute \src "ls180.v:5592.1-5596.4"
   wire width 10 $0\memdat_4[9:0]
-  attribute \src "ls180.v:5629.1-5632.4"
+  attribute \src "ls180.v:5598.1-5601.4"
   wire width 10 $0\memdat_5[9:0]
-  attribute \src "ls180.v:5640.1-5644.4"
+  attribute \src "ls180.v:5609.1-5613.4"
   wire width 10 $0\memdat_6[9:0]
-  attribute \src "ls180.v:5646.1-5649.4"
+  attribute \src "ls180.v:5615.1-5618.4"
   wire width 10 $0\memdat_7[9:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\ram_bus_ram_bus_ack[0:0]
-  attribute \src "ls180.v:197.5-197.31"
+  attribute \src "ls180.v:240.5-240.31"
   wire $0\ram_bus_ram_bus_err[0:0]
-  attribute \src "ls180.v:1733.1-1743.4"
-  wire width 8 $0\ram_we[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:1722.1-1728.4"
+  wire width 4 $0\ram_we[3:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\rddata_en[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\regs0[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\regs1[0:0]
-  attribute \src "ls180.v:977.5-977.17"
+  attribute \src "ls180.v:978.5-978.17"
   wire $0\reset[0:0]
-  attribute \src "ls180.v:3450.1-3466.4"
+  attribute \src "ls180.v:3435.1-3451.4"
   wire $0\rhs_array_muxed0[0:0]
-  attribute \src "ls180.v:3671.1-3687.4"
+  attribute \src "ls180.v:3656.1-3672.4"
   wire $0\rhs_array_muxed10[0:0]
-  attribute \src "ls180.v:3688.1-3704.4"
+  attribute \src "ls180.v:3673.1-3689.4"
   wire $0\rhs_array_muxed11[0:0]
-  attribute \src "ls180.v:3756.1-3763.4"
+  attribute \src "ls180.v:3741.1-3748.4"
   wire width 22 $0\rhs_array_muxed12[21:0]
-  attribute \src "ls180.v:3764.1-3771.4"
+  attribute \src "ls180.v:3749.1-3756.4"
   wire $0\rhs_array_muxed13[0:0]
-  attribute \src "ls180.v:3772.1-3779.4"
+  attribute \src "ls180.v:3757.1-3764.4"
   wire $0\rhs_array_muxed14[0:0]
-  attribute \src "ls180.v:3780.1-3787.4"
+  attribute \src "ls180.v:3765.1-3772.4"
   wire width 22 $0\rhs_array_muxed15[21:0]
-  attribute \src "ls180.v:3788.1-3795.4"
+  attribute \src "ls180.v:3773.1-3780.4"
   wire $0\rhs_array_muxed16[0:0]
-  attribute \src "ls180.v:3796.1-3803.4"
+  attribute \src "ls180.v:3781.1-3788.4"
   wire $0\rhs_array_muxed17[0:0]
-  attribute \src "ls180.v:3804.1-3811.4"
+  attribute \src "ls180.v:3789.1-3796.4"
   wire width 22 $0\rhs_array_muxed18[21:0]
-  attribute \src "ls180.v:3812.1-3819.4"
+  attribute \src "ls180.v:3797.1-3804.4"
   wire $0\rhs_array_muxed19[0:0]
-  attribute \src "ls180.v:3467.1-3483.4"
+  attribute \src "ls180.v:3452.1-3468.4"
   wire width 13 $0\rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:3820.1-3827.4"
+  attribute \src "ls180.v:3805.1-3812.4"
   wire $0\rhs_array_muxed20[0:0]
-  attribute \src "ls180.v:3828.1-3835.4"
+  attribute \src "ls180.v:3813.1-3820.4"
   wire width 22 $0\rhs_array_muxed21[21:0]
-  attribute \src "ls180.v:3836.1-3843.4"
+  attribute \src "ls180.v:3821.1-3828.4"
   wire $0\rhs_array_muxed22[0:0]
-  attribute \src "ls180.v:3844.1-3851.4"
+  attribute \src "ls180.v:3829.1-3836.4"
   wire $0\rhs_array_muxed23[0:0]
-  attribute \src "ls180.v:3852.1-3865.4"
-  wire width 29 $0\rhs_array_muxed24[28:0]
-  attribute \src "ls180.v:3866.1-3879.4"
-  wire width 64 $0\rhs_array_muxed25[63:0]
-  attribute \src "ls180.v:3880.1-3893.4"
-  wire width 8 $0\rhs_array_muxed26[7:0]
-  attribute \src "ls180.v:3894.1-3907.4"
+  attribute \src "ls180.v:3837.1-3850.4"
+  wire width 30 $0\rhs_array_muxed24[29:0]
+  attribute \src "ls180.v:3851.1-3864.4"
+  wire width 32 $0\rhs_array_muxed25[31:0]
+  attribute \src "ls180.v:3865.1-3878.4"
+  wire width 4 $0\rhs_array_muxed26[3:0]
+  attribute \src "ls180.v:3879.1-3892.4"
   wire $0\rhs_array_muxed27[0:0]
-  attribute \src "ls180.v:3908.1-3921.4"
+  attribute \src "ls180.v:3893.1-3906.4"
   wire $0\rhs_array_muxed28[0:0]
-  attribute \src "ls180.v:3922.1-3935.4"
+  attribute \src "ls180.v:3907.1-3920.4"
   wire $0\rhs_array_muxed29[0:0]
-  attribute \src "ls180.v:3484.1-3500.4"
+  attribute \src "ls180.v:3469.1-3485.4"
   wire width 2 $0\rhs_array_muxed2[1:0]
-  attribute \src "ls180.v:3936.1-3949.4"
+  attribute \src "ls180.v:3921.1-3934.4"
   wire width 3 $0\rhs_array_muxed30[2:0]
-  attribute \src "ls180.v:3950.1-3963.4"
+  attribute \src "ls180.v:3935.1-3948.4"
   wire width 2 $0\rhs_array_muxed31[1:0]
-  attribute \src "ls180.v:3501.1-3517.4"
+  attribute \src "ls180.v:3486.1-3502.4"
   wire $0\rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:3518.1-3534.4"
+  attribute \src "ls180.v:3503.1-3519.4"
   wire $0\rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:3535.1-3551.4"
+  attribute \src "ls180.v:3520.1-3536.4"
   wire $0\rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:3603.1-3619.4"
+  attribute \src "ls180.v:3588.1-3604.4"
   wire $0\rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:3620.1-3636.4"
+  attribute \src "ls180.v:3605.1-3621.4"
   wire width 13 $0\rhs_array_muxed7[12:0]
-  attribute \src "ls180.v:3637.1-3653.4"
+  attribute \src "ls180.v:3622.1-3638.4"
   wire width 2 $0\rhs_array_muxed8[1:0]
-  attribute \src "ls180.v:3654.1-3670.4"
+  attribute \src "ls180.v:3639.1-3655.4"
   wire $0\rhs_array_muxed9[0:0]
-  attribute \src "ls180.v:2912.1-2917.4"
+  attribute \src "ls180.v:2897.1-2902.4"
   wire $0\rx_clear[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\rx_fifo_consume[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 5 $0\rx_fifo_level0[4:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\rx_fifo_produce[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\rx_fifo_readable[0:0]
-  attribute \src "ls180.v:959.5-959.27"
+  attribute \src "ls180.v:960.5-960.27"
   wire $0\rx_fifo_replace[0:0]
-  attribute \src "ls180.v:2970.1-2977.4"
+  attribute \src "ls180.v:2955.1-2962.4"
   wire width 4 $0\rx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\rx_old_trigger[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\rx_pending[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_address_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_address_storage[12:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_baddress_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\sdram_baddress_storage[1:0]
-  attribute \src "ls180.v:1955.1-1962.4"
+  attribute \src "ls180.v:1940.1-1947.4"
   wire $0\sdram_bankmachine0_auto_precharge[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:432.5-432.59"
+  attribute \src "ls180.v:445.5-445.59"
   wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:415.5-415.62"
+  attribute \src "ls180.v:428.5-428.62"
   wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:416.5-416.61"
+  attribute \src "ls180.v:429.5-429.61"
   wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:1977.1-1984.4"
+  attribute \src "ls180.v:1962.1-1969.4"
   wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:1944.1-1951.4"
+  attribute \src "ls180.v:1929.1-1936.4"
   wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2642.1-2650.4"
+  attribute \src "ls180.v:2627.1-2635.4"
   wire $0\sdram_bankmachine0_cmd_ready[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_cmd_valid[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_refresh_gnt[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_req_rdata_valid[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_req_wdata_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_bankmachine0_row[12:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_row_close[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire $0\sdram_bankmachine0_row_open[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_row_opened[0:0]
-  attribute \src "ls180.v:474.32-474.71"
+  attribute \src "ls180.v:487.32-487.71"
   wire $0\sdram_bankmachine0_trascon_ready[0:0]
-  attribute \src "ls180.v:472.32-472.70"
+  attribute \src "ls180.v:485.32-485.70"
   wire $0\sdram_bankmachine0_trccon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine0_twtpcon_ready[0:0]
-  attribute \src "ls180.v:2112.1-2119.4"
+  attribute \src "ls180.v:2097.1-2104.4"
   wire $0\sdram_bankmachine1_auto_precharge[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:514.5-514.59"
+  attribute \src "ls180.v:527.5-527.59"
   wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:497.5-497.62"
+  attribute \src "ls180.v:510.5-510.62"
   wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:498.5-498.61"
+  attribute \src "ls180.v:511.5-511.61"
   wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:2134.1-2141.4"
+  attribute \src "ls180.v:2119.1-2126.4"
   wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:2101.1-2108.4"
+  attribute \src "ls180.v:2086.1-2093.4"
   wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2651.1-2659.4"
+  attribute \src "ls180.v:2636.1-2644.4"
   wire $0\sdram_bankmachine1_cmd_ready[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_cmd_valid[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_refresh_gnt[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_req_rdata_valid[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_req_wdata_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_bankmachine1_row[12:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_row_close[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire $0\sdram_bankmachine1_row_open[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_row_opened[0:0]
-  attribute \src "ls180.v:556.32-556.71"
+  attribute \src "ls180.v:569.32-569.71"
   wire $0\sdram_bankmachine1_trascon_ready[0:0]
-  attribute \src "ls180.v:554.32-554.70"
+  attribute \src "ls180.v:567.32-567.70"
   wire $0\sdram_bankmachine1_trccon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine1_twtpcon_ready[0:0]
-  attribute \src "ls180.v:2269.1-2276.4"
+  attribute \src "ls180.v:2254.1-2261.4"
   wire $0\sdram_bankmachine2_auto_precharge[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:596.5-596.59"
+  attribute \src "ls180.v:609.5-609.59"
   wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:579.5-579.62"
+  attribute \src "ls180.v:592.5-592.62"
   wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:580.5-580.61"
+  attribute \src "ls180.v:593.5-593.61"
   wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:2291.1-2298.4"
+  attribute \src "ls180.v:2276.1-2283.4"
   wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:2258.1-2265.4"
+  attribute \src "ls180.v:2243.1-2250.4"
   wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2660.1-2668.4"
+  attribute \src "ls180.v:2645.1-2653.4"
   wire $0\sdram_bankmachine2_cmd_ready[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_cmd_valid[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_refresh_gnt[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_req_rdata_valid[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_req_wdata_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_bankmachine2_row[12:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_row_close[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire $0\sdram_bankmachine2_row_open[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_row_opened[0:0]
-  attribute \src "ls180.v:638.32-638.71"
+  attribute \src "ls180.v:651.32-651.71"
   wire $0\sdram_bankmachine2_trascon_ready[0:0]
-  attribute \src "ls180.v:636.32-636.70"
+  attribute \src "ls180.v:649.32-649.70"
   wire $0\sdram_bankmachine2_trccon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine2_twtpcon_ready[0:0]
-  attribute \src "ls180.v:2426.1-2433.4"
+  attribute \src "ls180.v:2411.1-2418.4"
   wire $0\sdram_bankmachine3_auto_precharge[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:678.5-678.59"
+  attribute \src "ls180.v:691.5-691.59"
   wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
-  attribute \src "ls180.v:661.5-661.62"
+  attribute \src "ls180.v:674.5-674.62"
   wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
-  attribute \src "ls180.v:662.5-662.61"
+  attribute \src "ls180.v:675.5-675.61"
   wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
-  attribute \src "ls180.v:2448.1-2455.4"
+  attribute \src "ls180.v:2433.1-2440.4"
   wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:2415.1-2422.4"
+  attribute \src "ls180.v:2400.1-2407.4"
   wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2669.1-2677.4"
+  attribute \src "ls180.v:2654.1-2662.4"
   wire $0\sdram_bankmachine3_cmd_ready[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_cmd_valid[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_refresh_gnt[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_req_rdata_valid[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_req_wdata_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_bankmachine3_row[12:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_row_close[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire $0\sdram_bankmachine3_row_open[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_row_opened[0:0]
-  attribute \src "ls180.v:720.32-720.71"
+  attribute \src "ls180.v:733.32-733.71"
   wire $0\sdram_bankmachine3_trascon_ready[0:0]
-  attribute \src "ls180.v:718.32-718.70"
+  attribute \src "ls180.v:731.32-731.70"
   wire $0\sdram_bankmachine3_trccon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_bankmachine3_twtpcon_ready[0:0]
-  attribute \src "ls180.v:2591.1-2596.4"
+  attribute \src "ls180.v:2576.1-2581.4"
   wire $0\sdram_choose_cmd_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:2597.1-2602.4"
+  attribute \src "ls180.v:2582.1-2587.4"
   wire $0\sdram_choose_cmd_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:2603.1-2608.4"
+  attribute \src "ls180.v:2588.1-2593.4"
   wire $0\sdram_choose_cmd_cmd_payload_we[0:0]
-  attribute \src "ls180.v:728.5-728.38"
+  attribute \src "ls180.v:741.5-741.38"
   wire $0\sdram_choose_cmd_cmd_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\sdram_choose_cmd_grant[1:0]
-  attribute \src "ls180.v:2577.1-2583.4"
+  attribute \src "ls180.v:2562.1-2568.4"
   wire width 4 $0\sdram_choose_cmd_valids[3:0]
-  attribute \src "ls180.v:726.5-726.43"
+  attribute \src "ls180.v:739.5-739.43"
   wire $0\sdram_choose_cmd_want_activates[0:0]
-  attribute \src "ls180.v:725.5-725.38"
+  attribute \src "ls180.v:738.5-738.38"
   wire $0\sdram_choose_cmd_want_cmds[0:0]
-  attribute \src "ls180.v:723.5-723.39"
+  attribute \src "ls180.v:736.5-736.39"
   wire $0\sdram_choose_cmd_want_reads[0:0]
-  attribute \src "ls180.v:724.5-724.40"
+  attribute \src "ls180.v:737.5-737.40"
   wire $0\sdram_choose_cmd_want_writes[0:0]
-  attribute \src "ls180.v:2624.1-2629.4"
+  attribute \src "ls180.v:2609.1-2614.4"
   wire $0\sdram_choose_req_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:2630.1-2635.4"
+  attribute \src "ls180.v:2615.1-2620.4"
   wire $0\sdram_choose_req_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:2636.1-2641.4"
+  attribute \src "ls180.v:2621.1-2626.4"
   wire $0\sdram_choose_req_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_choose_req_cmd_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\sdram_choose_req_grant[1:0]
-  attribute \src "ls180.v:2610.1-2616.4"
+  attribute \src "ls180.v:2595.1-2601.4"
   wire width 4 $0\sdram_choose_req_valids[3:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_choose_req_want_activates[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_choose_req_want_reads[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_choose_req_want_writes[0:0]
-  attribute \src "ls180.v:1899.1-1929.4"
+  attribute \src "ls180.v:1884.1-1914.4"
   wire $0\sdram_cmd_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_cmd_payload_a[12:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\sdram_cmd_payload_ba[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:376.5-376.37"
+  attribute \src "ls180.v:389.5-389.37"
   wire $0\sdram_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:377.5-377.38"
+  attribute \src "ls180.v:390.5-390.38"
   wire $0\sdram_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_cmd_payload_we[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_cmd_ready[0:0]
-  attribute \src "ls180.v:1899.1-1929.4"
+  attribute \src "ls180.v:1884.1-1914.4"
   wire $0\sdram_cmd_valid[0:0]
-  attribute \src "ls180.v:312.5-312.33"
+  attribute \src "ls180.v:325.5-325.33"
   wire $0\sdram_command_issue_w[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_command_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 6 $0\sdram_command_storage[5:0]
-  attribute \src "ls180.v:361.5-361.30"
+  attribute \src "ls180.v:374.5-374.30"
   wire $0\sdram_dfi_p0_act_n[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 13 $0\sdram_dfi_p0_address[12:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\sdram_dfi_p0_bank[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_cas_n[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_cs_n[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_ras_n[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_rddata_en[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_we_n[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_dfi_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_en0[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire $0\sdram_en1[0:0]
-  attribute \src "ls180.v:2778.1-2791.4"
+  attribute \src "ls180.v:2763.1-2776.4"
   wire width 16 $0\sdram_interface_wdata[15:0]
-  attribute \src "ls180.v:2778.1-2791.4"
+  attribute \src "ls180.v:2763.1-2776.4"
   wire width 2 $0\sdram_interface_wdata_we[1:0]
-  attribute \src "ls180.v:262.5-262.31"
+  attribute \src "ls180.v:275.5-275.31"
   wire $0\sdram_inti_p0_act_n[0:0]
-  attribute \src "ls180.v:1840.1-1856.4"
+  attribute \src "ls180.v:1825.1-1841.4"
   wire $0\sdram_inti_p0_cas_n[0:0]
-  attribute \src "ls180.v:1840.1-1856.4"
+  attribute \src "ls180.v:1825.1-1841.4"
   wire $0\sdram_inti_p0_cs_n[0:0]
-  attribute \src "ls180.v:1840.1-1856.4"
+  attribute \src "ls180.v:1825.1-1841.4"
   wire $0\sdram_inti_p0_ras_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 16 $0\sdram_inti_p0_rddata[15:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_inti_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:1840.1-1856.4"
+  attribute \src "ls180.v:1825.1-1841.4"
   wire $0\sdram_inti_p0_we_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_act_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 13 $0\sdram_master_p0_address[12:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 2 $0\sdram_master_p0_bank[1:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_cas_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_cke[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_cs_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_odt[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_ras_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_rddata_en[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_reset_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_we_n[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 16 $0\sdram_master_p0_wrdata[15:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_master_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 2 $0\sdram_master_p0_wrdata_mask[1:0]
-  attribute \src "ls180.v:759.12-759.31"
+  attribute \src "ls180.v:772.12-772.31"
   wire width 13 $0\sdram_nop_a[12:0]
-  attribute \src "ls180.v:760.11-760.30"
+  attribute \src "ls180.v:773.11-773.30"
   wire width 2 $0\sdram_nop_ba[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_postponer_count[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_postponer_req_o[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_sequencer_count[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_sequencer_counter[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_sequencer_done1[0:0]
-  attribute \src "ls180.v:1899.1-1929.4"
+  attribute \src "ls180.v:1884.1-1914.4"
   wire $0\sdram_sequencer_start0[0:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire width 16 $0\sdram_slave_p0_rddata[15:0]
-  attribute \src "ls180.v:1782.1-1836.4"
+  attribute \src "ls180.v:1767.1-1821.4"
   wire $0\sdram_slave_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 16 $0\sdram_status[15:0]
-  attribute \src "ls180.v:762.5-762.26"
+  attribute \src "ls180.v:775.5-775.26"
   wire $0\sdram_steerer0[0:0]
-  attribute \src "ls180.v:763.5-763.26"
+  attribute \src "ls180.v:776.5-776.26"
   wire $0\sdram_steerer1[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire width 2 $0\sdram_steerer_sel[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_storage[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_tccdcon_count[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_tccdcon_ready[0:0]
-  attribute \src "ls180.v:767.32-767.58"
+  attribute \src "ls180.v:780.32-780.58"
   wire $0\sdram_tfawcon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 5 $0\sdram_time0[4:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\sdram_time1[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 10 $0\sdram_timer_count1[9:0]
-  attribute \src "ls180.v:765.32-765.58"
+  attribute \src "ls180.v:778.32-778.58"
   wire $0\sdram_trrdcon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\sdram_twtrcon_count[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_twtrcon_ready[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\sdram_wrdata_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 16 $0\sdram_wrdata_storage[15:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\socbushandler_converted_interface_ack[0:0]
-  attribute \src "ls180.v:814.5-814.49"
-  wire $0\socbushandler_converted_interface_err[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire $0\socbushandler_counter[0:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\socbushandler_counter_subfragments_converter2_next_value[0:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
-  wire width 64 $0\socbushandler_dat_r[63:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\socbushandler_skip[0:0]
-  attribute \src "ls180.v:1993.1-2086.4"
+  attribute \src "ls180.v:1978.1-2071.4"
   wire width 3 $0\subfragments_bankmachine0_next_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\subfragments_bankmachine0_state[2:0]
-  attribute \src "ls180.v:2150.1-2243.4"
+  attribute \src "ls180.v:2135.1-2228.4"
   wire width 3 $0\subfragments_bankmachine1_next_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\subfragments_bankmachine1_state[2:0]
-  attribute \src "ls180.v:2307.1-2400.4"
+  attribute \src "ls180.v:2292.1-2385.4"
   wire width 3 $0\subfragments_bankmachine2_next_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\subfragments_bankmachine2_state[2:0]
-  attribute \src "ls180.v:2464.1-2557.4"
+  attribute \src "ls180.v:2449.1-2542.4"
   wire width 3 $0\subfragments_bankmachine3_next_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\subfragments_bankmachine3_state[2:0]
-  attribute \src "ls180.v:1539.1-1585.4"
+  attribute \src "ls180.v:1532.1-1578.4"
   wire $0\subfragments_converter0_next_state[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_converter0_state[0:0]
-  attribute \src "ls180.v:1599.1-1645.4"
+  attribute \src "ls180.v:1592.1-1638.4"
   wire $0\subfragments_converter1_next_state[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_converter1_state[0:0]
-  attribute \src "ls180.v:1659.1-1705.4"
+  attribute \src "ls180.v:1652.1-1698.4"
   wire $0\subfragments_converter2_next_state[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_converter2_state[0:0]
-  attribute \src "ls180.v:1043.5-1043.32"
-  wire $0\subfragments_locked0[0:0]
   attribute \src "ls180.v:1044.5-1044.32"
-  wire $0\subfragments_locked1[0:0]
+  wire $0\subfragments_locked0[0:0]
   attribute \src "ls180.v:1045.5-1045.32"
-  wire $0\subfragments_locked2[0:0]
+  wire $0\subfragments_locked1[0:0]
   attribute \src "ls180.v:1046.5-1046.32"
+  wire $0\subfragments_locked2[0:0]
+  attribute \src "ls180.v:1047.5-1047.32"
   wire $0\subfragments_locked3[0:0]
-  attribute \src "ls180.v:2682.1-2754.4"
+  attribute \src "ls180.v:2667.1-2739.4"
   wire width 3 $0\subfragments_multiplexer_next_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 3 $0\subfragments_multiplexer_state[2:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_new_master_rdata_valid0[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_new_master_rdata_valid1[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_new_master_rdata_valid2[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_new_master_rdata_valid3[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_new_master_wdata_ready[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\subfragments_next_state[0:0]
-  attribute \src "ls180.v:1899.1-1929.4"
+  attribute \src "ls180.v:1884.1-1914.4"
   wire width 2 $0\subfragments_refresher_next_state[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 2 $0\subfragments_refresher_state[1:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\subfragments_state[0:0]
-  attribute \src "ls180.v:3552.1-3568.4"
+  attribute \src "ls180.v:3537.1-3553.4"
   wire $0\t_array_muxed0[0:0]
-  attribute \src "ls180.v:3569.1-3585.4"
+  attribute \src "ls180.v:3554.1-3570.4"
   wire $0\t_array_muxed1[0:0]
-  attribute \src "ls180.v:3586.1-3602.4"
+  attribute \src "ls180.v:3571.1-3587.4"
   wire $0\t_array_muxed2[0:0]
-  attribute \src "ls180.v:3705.1-3721.4"
+  attribute \src "ls180.v:3690.1-3706.4"
   wire $0\t_array_muxed3[0:0]
-  attribute \src "ls180.v:3722.1-3738.4"
+  attribute \src "ls180.v:3707.1-3723.4"
   wire $0\t_array_muxed4[0:0]
-  attribute \src "ls180.v:3739.1-3755.4"
+  attribute \src "ls180.v:3724.1-3740.4"
   wire $0\t_array_muxed5[0:0]
-  attribute \src "ls180.v:2901.1-2906.4"
+  attribute \src "ls180.v:2886.1-2891.4"
   wire $0\tx_clear[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\tx_fifo_consume[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 5 $0\tx_fifo_level0[4:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\tx_fifo_produce[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\tx_fifo_readable[0:0]
-  attribute \src "ls180.v:922.5-922.27"
+  attribute \src "ls180.v:923.5-923.27"
   wire $0\tx_fifo_replace[0:0]
-  attribute \src "ls180.v:905.5-905.30"
+  attribute \src "ls180.v:906.5-906.30"
   wire $0\tx_fifo_sink_first[0:0]
-  attribute \src "ls180.v:906.5-906.29"
+  attribute \src "ls180.v:907.5-907.29"
   wire $0\tx_fifo_sink_last[0:0]
-  attribute \src "ls180.v:2940.1-2947.4"
+  attribute \src "ls180.v:2925.1-2932.4"
   wire width 4 $0\tx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\tx_old_trigger[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\tx_pending[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\uart_phy_phase_accumulator_rx[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\uart_phy_phase_accumulator_tx[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_re[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\uart_phy_rx_bitcount[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_rx_busy[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_rx_r[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\uart_phy_rx_reg[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_sink_ready[0:0]
-  attribute \src "ls180.v:850.5-850.33"
+  attribute \src "ls180.v:851.5-851.33"
   wire $0\uart_phy_source_first[0:0]
-  attribute \src "ls180.v:851.5-851.32"
+  attribute \src "ls180.v:852.5-852.32"
   wire $0\uart_phy_source_last[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\uart_phy_source_payload_data[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_source_valid[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 32 $0\uart_phy_storage[31:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 4 $0\uart_phy_tx_bitcount[3:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_tx_busy[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire width 8 $0\uart_phy_tx_reg[7:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_uart_clk_rxen[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\uart_phy_uart_clk_txen[0:0]
-  attribute \src "ls180.v:2810.1-2856.4"
+  attribute \src "ls180.v:2795.1-2841.4"
   wire $0\wb_sdram_ack[0:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire width 30 $0\wb_sdram_adr[29:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\wb_sdram_cyc[0:0]
-  attribute \src "ls180.v:1647.1-1657.4"
-  wire width 32 $0\wb_sdram_dat_w[31:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire width 4 $0\wb_sdram_sel[3:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\wb_sdram_stb[0:0]
-  attribute \src "ls180.v:1659.1-1705.4"
-  wire $0\wb_sdram_we[0:0]
-  attribute \src "ls180.v:4300.1-5506.4"
+  attribute \src "ls180.v:819.5-819.24"
+  wire $0\wb_sdram_err[0:0]
+  attribute \src "ls180.v:4285.1-5491.4"
   wire $0\wdata_consumed[0:0]
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 6 $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513
-  attribute \src "ls180.v:5510.1-5528.4"
-  wire width 64 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 4 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563
-  attribute \src "ls180.v:5538.1-5556.4"
-  wire width 64 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 3 $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 25 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571
-  attribute \src "ls180.v:5566.1-5570.4"
-  wire width 25 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 3 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 25 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581
-  attribute \src "ls180.v:5580.1-5584.4"
-  wire width 25 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 3 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 25 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591
-  attribute \src "ls180.v:5594.1-5598.4"
-  wire width 25 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 3 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 25 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601
-  attribute \src "ls180.v:5608.1-5612.4"
-  wire width 25 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 4 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 10 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611
-  attribute \src "ls180.v:5623.1-5627.4"
-  wire width 10 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 4 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 10 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621
-  attribute \src "ls180.v:5640.1-5644.4"
-  wire width 10 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622
-  attribute \src "ls180.v:1388.11-1388.30"
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 7 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457
+  attribute \src "ls180.v:5495.1-5505.4"
+  wire width 32 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 5 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483
+  attribute \src "ls180.v:5515.1-5525.4"
+  wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 3 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 25 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491
+  attribute \src "ls180.v:5535.1-5539.4"
+  wire width 25 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 3 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501
+  attribute \src "ls180.v:5549.1-5553.4"
+  wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 3 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511
+  attribute \src "ls180.v:5563.1-5567.4"
+  wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521
+  attribute \src "ls180.v:5577.1-5581.4"
+  wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531
+  attribute \src "ls180.v:5592.1-5596.4"
+  wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 4 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541
+  attribute \src "ls180.v:5609.1-5613.4"
+  wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542
+  attribute \src "ls180.v:1381.11-1381.30"
   wire width 2 $1\array_muxed0[1:0]
-  attribute \src "ls180.v:1389.12-1389.32"
+  attribute \src "ls180.v:1382.12-1382.32"
   wire width 13 $1\array_muxed1[12:0]
-  attribute \src "ls180.v:1390.5-1390.24"
+  attribute \src "ls180.v:1383.5-1383.24"
   wire $1\array_muxed2[0:0]
-  attribute \src "ls180.v:1391.5-1391.24"
+  attribute \src "ls180.v:1384.5-1384.24"
   wire $1\array_muxed3[0:0]
-  attribute \src "ls180.v:1392.5-1392.24"
+  attribute \src "ls180.v:1385.5-1385.24"
   wire $1\array_muxed4[0:0]
-  attribute \src "ls180.v:1393.5-1393.24"
+  attribute \src "ls180.v:1386.5-1386.24"
   wire $1\array_muxed5[0:0]
-  attribute \src "ls180.v:1394.5-1394.24"
+  attribute \src "ls180.v:1387.5-1387.24"
   wire $1\array_muxed6[0:0]
-  attribute \src "ls180.v:831.5-831.24"
+  attribute \src "ls180.v:832.5-832.24"
   wire $1\cmd_consumed[0:0]
-  attribute \src "ls180.v:214.5-214.30"
-  wire $1\converter0_counter[0:0]
-  attribute \src "ls180.v:1009.5-1009.65"
-  wire $1\converter0_counter_subfragments_converter0_next_value[0:0]
-  attribute \src "ls180.v:1010.5-1010.68"
-  wire $1\converter0_counter_subfragments_converter0_next_value_ce[0:0]
-  attribute \src "ls180.v:216.12-216.36"
-  wire width 64 $1\converter0_dat_r[63:0]
-  attribute \src "ls180.v:213.5-213.27"
-  wire $1\converter0_skip[0:0]
-  attribute \src "ls180.v:229.5-229.30"
-  wire $1\converter1_counter[0:0]
-  attribute \src "ls180.v:1013.5-1013.65"
-  wire $1\converter1_counter_subfragments_converter1_next_value[0:0]
-  attribute \src "ls180.v:1014.5-1014.68"
-  wire $1\converter1_counter_subfragments_converter1_next_value_ce[0:0]
-  attribute \src "ls180.v:231.12-231.36"
-  wire width 64 $1\converter1_dat_r[63:0]
-  attribute \src "ls180.v:228.5-228.27"
-  wire $1\converter1_skip[0:0]
-  attribute \src "ls180.v:828.5-828.29"
+  attribute \src "ls180.v:829.5-829.29"
   wire $1\converter_counter[0:0]
-  attribute \src "ls180.v:1054.5-1054.53"
+  attribute \src "ls180.v:1055.5-1055.53"
   wire $1\converter_counter_subfragments_next_value[0:0]
-  attribute \src "ls180.v:1055.5-1055.56"
+  attribute \src "ls180.v:1056.5-1056.56"
   wire $1\converter_counter_subfragments_next_value_ce[0:0]
-  attribute \src "ls180.v:830.12-830.35"
+  attribute \src "ls180.v:831.12-831.35"
   wire width 32 $1\converter_dat_r[31:0]
-  attribute \src "ls180.v:827.5-827.26"
+  attribute \src "ls180.v:828.5-828.26"
   wire $1\converter_skip[0:0]
-  attribute \src "ls180.v:250.12-250.33"
+  attribute \src "ls180.v:263.12-263.33"
   wire width 16 $1\dfi_p0_rddata[15:0]
-  attribute \src "ls180.v:251.5-251.31"
+  attribute \src "ls180.v:264.5-264.31"
   wire $1\dfi_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:998.12-998.25"
+  attribute \src "ls180.v:999.12-999.25"
   wire width 36 $1\dummy[35:0]
-  attribute \src "ls180.v:996.11-996.26"
+  attribute \src "ls180.v:997.11-997.26"
   wire width 3 $1\eint_tmp[2:0]
-  attribute \src "ls180.v:886.11-886.40"
+  attribute \src "ls180.v:887.11-887.40"
   wire width 2 $1\eventmanager_pending_w[1:0]
-  attribute \src "ls180.v:888.5-888.27"
+  attribute \src "ls180.v:889.5-889.27"
   wire $1\eventmanager_re[0:0]
-  attribute \src "ls180.v:882.11-882.39"
+  attribute \src "ls180.v:883.11-883.39"
   wire width 2 $1\eventmanager_status_w[1:0]
-  attribute \src "ls180.v:887.11-887.38"
+  attribute \src "ls180.v:888.11-888.38"
   wire width 2 $1\eventmanager_storage[1:0]
-  attribute \src "ls180.v:979.5-979.23"
+  attribute \src "ls180.v:980.5-980.23"
   wire $1\gpio0_oe_re[0:0]
-  attribute \src "ls180.v:978.11-978.34"
+  attribute \src "ls180.v:979.11-979.34"
   wire width 8 $1\gpio0_oe_storage[7:0]
-  attribute \src "ls180.v:983.5-983.24"
+  attribute \src "ls180.v:984.5-984.24"
   wire $1\gpio0_out_re[0:0]
-  attribute \src "ls180.v:982.11-982.35"
+  attribute \src "ls180.v:983.11-983.35"
   wire width 8 $1\gpio0_out_storage[7:0]
-  attribute \src "ls180.v:984.11-984.35"
-  wire width 8 $1\gpio0_pads_gpio0i[7:0]
   attribute \src "ls180.v:985.11-985.35"
+  wire width 8 $1\gpio0_pads_gpio0i[7:0]
+  attribute \src "ls180.v:986.11-986.35"
   wire width 8 $1\gpio0_pads_gpio0o[7:0]
-  attribute \src "ls180.v:986.11-986.36"
+  attribute \src "ls180.v:987.11-987.36"
   wire width 8 $1\gpio0_pads_gpio0oe[7:0]
-  attribute \src "ls180.v:980.11-980.30"
+  attribute \src "ls180.v:981.11-981.30"
   wire width 8 $1\gpio0_status[7:0]
-  attribute \src "ls180.v:988.5-988.23"
+  attribute \src "ls180.v:989.5-989.23"
   wire $1\gpio1_oe_re[0:0]
-  attribute \src "ls180.v:987.11-987.34"
+  attribute \src "ls180.v:988.11-988.34"
   wire width 8 $1\gpio1_oe_storage[7:0]
-  attribute \src "ls180.v:992.5-992.24"
+  attribute \src "ls180.v:993.5-993.24"
   wire $1\gpio1_out_re[0:0]
-  attribute \src "ls180.v:991.11-991.35"
+  attribute \src "ls180.v:992.11-992.35"
   wire width 8 $1\gpio1_out_storage[7:0]
-  attribute \src "ls180.v:993.11-993.35"
-  wire width 8 $1\gpio1_pads_gpio1i[7:0]
   attribute \src "ls180.v:994.11-994.35"
+  wire width 8 $1\gpio1_pads_gpio1i[7:0]
+  attribute \src "ls180.v:995.11-995.35"
   wire width 8 $1\gpio1_pads_gpio1o[7:0]
-  attribute \src "ls180.v:995.11-995.36"
+  attribute \src "ls180.v:996.11-996.36"
   wire width 8 $1\gpio1_pads_gpio1oe[7:0]
-  attribute \src "ls180.v:989.11-989.30"
+  attribute \src "ls180.v:990.11-990.30"
   wire width 8 $1\gpio1_status[7:0]
-  attribute \src "ls180.v:1003.5-1003.18"
+  attribute \src "ls180.v:1004.5-1004.18"
   wire $1\i2c_re[0:0]
-  attribute \src "ls180.v:1002.11-1002.29"
+  attribute \src "ls180.v:1003.11-1003.29"
   wire width 3 $1\i2c_storage[2:0]
-  attribute \src "ls180.v:235.5-235.19"
+  attribute \src "ls180.v:248.5-248.19"
   wire $1\int_rst[0:0]
-  attribute \src "ls180.v:208.5-208.46"
-  wire $1\interface0_converted_interface_ack[0:0]
-  attribute \src "ls180.v:223.5-223.46"
-  wire $1\interface1_converted_interface_ack[0:0]
   attribute \src "ls180.v:53.12-53.42"
   wire width 32 $1\libresocsim_bus_errors[31:0]
-  attribute \src "ls180.v:1097.12-1097.43"
+  attribute \src "ls180.v:155.5-155.42"
+  wire $1\libresocsim_converter0_counter[0:0]
+  attribute \src "ls180.v:1010.5-1010.77"
+  wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0]
+  attribute \src "ls180.v:1011.5-1011.80"
+  wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0]
+  attribute \src "ls180.v:157.12-157.48"
+  wire width 64 $1\libresocsim_converter0_dat_r[63:0]
+  attribute \src "ls180.v:154.5-154.39"
+  wire $1\libresocsim_converter0_skip[0:0]
+  attribute \src "ls180.v:170.5-170.42"
+  wire $1\libresocsim_converter1_counter[0:0]
+  attribute \src "ls180.v:1014.5-1014.77"
+  wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0]
+  attribute \src "ls180.v:1015.5-1015.80"
+  wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0]
+  attribute \src "ls180.v:172.12-172.48"
+  wire width 64 $1\libresocsim_converter1_dat_r[63:0]
+  attribute \src "ls180.v:169.5-169.39"
+  wire $1\libresocsim_converter1_skip[0:0]
+  attribute \src "ls180.v:185.5-185.42"
+  wire $1\libresocsim_converter2_counter[0:0]
+  attribute \src "ls180.v:1018.5-1018.77"
+  wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0]
+  attribute \src "ls180.v:1019.5-1019.80"
+  wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0]
+  attribute \src "ls180.v:187.12-187.48"
+  wire width 64 $1\libresocsim_converter2_dat_r[63:0]
+  attribute \src "ls180.v:184.5-184.39"
+  wire $1\libresocsim_converter2_skip[0:0]
+  attribute \src "ls180.v:1090.12-1090.43"
   wire width 20 $1\libresocsim_count[19:0]
-  attribute \src "ls180.v:165.5-165.29"
+  attribute \src "ls180.v:208.5-208.29"
   wire $1\libresocsim_en_re[0:0]
-  attribute \src "ls180.v:164.5-164.34"
+  attribute \src "ls180.v:207.5-207.34"
   wire $1\libresocsim_en_storage[0:0]
-  attribute \src "ls180.v:1094.5-1094.29"
+  attribute \src "ls180.v:1087.5-1087.29"
   wire $1\libresocsim_error[0:0]
-  attribute \src "ls180.v:185.5-185.39"
+  attribute \src "ls180.v:228.5-228.39"
   wire $1\libresocsim_eventmanager_re[0:0]
-  attribute \src "ls180.v:184.5-184.44"
+  attribute \src "ls180.v:227.5-227.44"
   wire $1\libresocsim_eventmanager_storage[0:0]
-  attribute \src "ls180.v:1091.11-1091.35"
+  attribute \src "ls180.v:1084.11-1084.35"
   wire width 2 $1\libresocsim_grant[1:0]
-  attribute \src "ls180.v:1101.11-1101.55"
+  attribute \src "ls180.v:1094.11-1094.55"
   wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1142.11-1142.55"
+  attribute \src "ls180.v:143.12-143.66"
+  wire width 30 $1\libresocsim_interface0_converted_interface_adr[29:0]
+  attribute \src "ls180.v:147.5-147.58"
+  wire $1\libresocsim_interface0_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:144.12-144.68"
+  wire width 32 $1\libresocsim_interface0_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:146.11-146.64"
+  wire width 4 $1\libresocsim_interface0_converted_interface_sel[3:0]
+  attribute \src "ls180.v:148.5-148.58"
+  wire $1\libresocsim_interface0_converted_interface_stb[0:0]
+  attribute \src "ls180.v:150.5-150.57"
+  wire $1\libresocsim_interface0_converted_interface_we[0:0]
+  attribute \src "ls180.v:1135.11-1135.55"
   wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1159.11-1159.55"
+  attribute \src "ls180.v:158.12-158.66"
+  wire width 30 $1\libresocsim_interface1_converted_interface_adr[29:0]
+  attribute \src "ls180.v:162.5-162.58"
+  wire $1\libresocsim_interface1_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:159.12-159.68"
+  wire width 32 $1\libresocsim_interface1_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:161.11-161.64"
+  wire width 4 $1\libresocsim_interface1_converted_interface_sel[3:0]
+  attribute \src "ls180.v:163.5-163.58"
+  wire $1\libresocsim_interface1_converted_interface_stb[0:0]
+  attribute \src "ls180.v:165.5-165.57"
+  wire $1\libresocsim_interface1_converted_interface_we[0:0]
+  attribute \src "ls180.v:1152.11-1152.55"
   wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1176.11-1176.55"
+  attribute \src "ls180.v:173.12-173.66"
+  wire width 30 $1\libresocsim_interface2_converted_interface_adr[29:0]
+  attribute \src "ls180.v:177.5-177.58"
+  wire $1\libresocsim_interface2_converted_interface_cyc[0:0]
+  attribute \src "ls180.v:174.12-174.68"
+  wire width 32 $1\libresocsim_interface2_converted_interface_dat_w[31:0]
+  attribute \src "ls180.v:176.11-176.64"
+  wire width 4 $1\libresocsim_interface2_converted_interface_sel[3:0]
+  attribute \src "ls180.v:178.5-178.58"
+  wire $1\libresocsim_interface2_converted_interface_stb[0:0]
+  attribute \src "ls180.v:180.5-180.57"
+  wire $1\libresocsim_interface2_converted_interface_we[0:0]
+  attribute \src "ls180.v:1169.11-1169.55"
   wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1189.11-1189.55"
+  attribute \src "ls180.v:1182.11-1182.55"
   wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1230.11-1230.55"
+  attribute \src "ls180.v:1223.11-1223.55"
   wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1295.11-1295.55"
+  attribute \src "ls180.v:1288.11-1288.55"
   wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:1320.11-1320.55"
+  attribute \src "ls180.v:1313.11-1313.55"
   wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:118.12-118.65"
+  attribute \src "ls180.v:141.12-141.65"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
-  attribute \src "ls180.v:119.12-119.66"
+  attribute \src "ls180.v:142.12-142.66"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
-  attribute \src "ls180.v:122.12-122.66"
+  attribute \src "ls180.v:120.12-120.66"
   wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
-  attribute \src "ls180.v:131.11-131.65"
+  attribute \src "ls180.v:129.11-129.65"
   wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
-  attribute \src "ls180.v:128.5-128.62"
+  attribute \src "ls180.v:126.5-126.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
-  attribute \src "ls180.v:130.5-130.60"
+  attribute \src "ls180.v:128.5-128.60"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
-  attribute \src "ls180.v:133.5-133.62"
+  attribute \src "ls180.v:131.5-131.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
-  attribute \src "ls180.v:129.5-129.61"
+  attribute \src "ls180.v:127.5-127.61"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
-  attribute \src "ls180.v:132.11-132.65"
+  attribute \src "ls180.v:130.11-130.65"
   wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
-  attribute \src "ls180.v:124.12-124.69"
+  attribute \src "ls180.v:122.12-122.69"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
-  attribute \src "ls180.v:125.5-125.62"
+  attribute \src "ls180.v:123.5-123.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
-  attribute \src "ls180.v:127.5-127.62"
+  attribute \src "ls180.v:125.5-125.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
-  attribute \src "ls180.v:126.5-126.61"
+  attribute \src "ls180.v:124.5-124.61"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
-  attribute \src "ls180.v:120.5-120.58"
+  attribute \src "ls180.v:115.5-115.58"
   wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+  attribute \src "ls180.v:62.5-62.41"
+  wire $1\libresocsim_libresoc_dbus_ack[0:0]
+  attribute \src "ls180.v:71.5-71.41"
+  wire $1\libresocsim_libresoc_ibus_ack[0:0]
   attribute \src "ls180.v:55.12-55.50"
   wire width 16 $1\libresocsim_libresoc_interrupt[15:0]
-  attribute \src "ls180.v:78.12-78.53"
-  wire width 30 $1\libresocsim_libresoc_xics_icp_adr[29:0]
-  attribute \src "ls180.v:82.5-82.45"
-  wire $1\libresocsim_libresoc_xics_icp_cyc[0:0]
-  attribute \src "ls180.v:79.12-79.55"
-  wire width 32 $1\libresocsim_libresoc_xics_icp_dat_w[31:0]
-  attribute \src "ls180.v:81.11-81.51"
-  wire width 4 $1\libresocsim_libresoc_xics_icp_sel[3:0]
-  attribute \src "ls180.v:83.5-83.45"
-  wire $1\libresocsim_libresoc_xics_icp_stb[0:0]
-  attribute \src "ls180.v:85.5-85.44"
-  wire $1\libresocsim_libresoc_xics_icp_we[0:0]
-  attribute \src "ls180.v:87.12-87.53"
-  wire width 30 $1\libresocsim_libresoc_xics_ics_adr[29:0]
-  attribute \src "ls180.v:91.5-91.45"
-  wire $1\libresocsim_libresoc_xics_ics_cyc[0:0]
-  attribute \src "ls180.v:88.12-88.55"
-  wire width 32 $1\libresocsim_libresoc_xics_ics_dat_w[31:0]
-  attribute \src "ls180.v:90.11-90.51"
-  wire width 4 $1\libresocsim_libresoc_xics_ics_sel[3:0]
-  attribute \src "ls180.v:92.5-92.45"
-  wire $1\libresocsim_libresoc_xics_ics_stb[0:0]
-  attribute \src "ls180.v:94.5-94.44"
-  wire $1\libresocsim_libresoc_xics_ics_we[0:0]
-  attribute \src "ls180.v:1056.12-1056.47"
+  attribute \src "ls180.v:102.5-102.44"
+  wire $1\libresocsim_libresoc_jtag_wb_ack[0:0]
+  attribute \src "ls180.v:1057.12-1057.47"
   wire width 14 $1\libresocsim_libresocsim_adr[13:0]
-  attribute \src "ls180.v:1346.12-1346.71"
+  attribute \src "ls180.v:1339.12-1339.71"
   wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
-  attribute \src "ls180.v:1347.5-1347.66"
+  attribute \src "ls180.v:1340.5-1340.66"
   wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
-  attribute \src "ls180.v:1058.11-1058.47"
+  attribute \src "ls180.v:1059.11-1059.47"
   wire width 8 $1\libresocsim_libresocsim_dat_w[7:0]
-  attribute \src "ls180.v:1344.11-1344.71"
+  attribute \src "ls180.v:1337.11-1337.71"
   wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
-  attribute \src "ls180.v:1345.5-1345.68"
+  attribute \src "ls180.v:1338.5-1338.68"
   wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
-  attribute \src "ls180.v:1057.5-1057.38"
+  attribute \src "ls180.v:1058.5-1058.38"
   wire $1\libresocsim_libresocsim_we[0:0]
-  attribute \src "ls180.v:1348.5-1348.62"
+  attribute \src "ls180.v:1341.5-1341.62"
   wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
-  attribute \src "ls180.v:1349.5-1349.65"
+  attribute \src "ls180.v:1342.5-1342.65"
   wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
-  attribute \src "ls180.v:1066.5-1066.48"
+  attribute \src "ls180.v:1067.5-1067.48"
   wire $1\libresocsim_libresocsim_wishbone_ack[0:0]
-  attribute \src "ls180.v:1062.12-1062.58"
+  attribute \src "ls180.v:1063.12-1063.58"
   wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0]
-  attribute \src "ls180.v:161.5-161.31"
+  attribute \src "ls180.v:204.5-204.31"
   wire $1\libresocsim_load_re[0:0]
-  attribute \src "ls180.v:160.12-160.44"
+  attribute \src "ls180.v:203.12-203.44"
   wire width 32 $1\libresocsim_load_storage[31:0]
-  attribute \src "ls180.v:1343.11-1343.40"
+  attribute \src "ls180.v:1336.11-1336.40"
   wire width 2 $1\libresocsim_next_state[1:0]
-  attribute \src "ls180.v:151.5-151.35"
+  attribute \src "ls180.v:194.5-194.35"
   wire $1\libresocsim_ram_bus_ack[0:0]
-  attribute \src "ls180.v:163.5-163.33"
+  attribute \src "ls180.v:206.5-206.33"
   wire $1\libresocsim_reload_re[0:0]
-  attribute \src "ls180.v:162.12-162.46"
+  attribute \src "ls180.v:205.12-205.46"
   wire width 32 $1\libresocsim_reload_storage[31:0]
   attribute \src "ls180.v:46.5-46.32"
   wire $1\libresocsim_reset_re[0:0]
@@ -240264,3733 +240178,3545 @@ module \ls180
   wire $1\libresocsim_scratch_re[0:0]
   attribute \src "ls180.v:47.12-47.55"
   wire width 32 $1\libresocsim_scratch_storage[31:0]
-  attribute \src "ls180.v:1085.5-1085.34"
+  attribute \src "ls180.v:1078.5-1078.34"
   wire $1\libresocsim_shared_ack[0:0]
-  attribute \src "ls180.v:1081.12-1081.44"
+  attribute \src "ls180.v:1074.12-1074.44"
   wire width 32 $1\libresocsim_shared_dat_r[31:0]
-  attribute \src "ls180.v:1092.11-1092.39"
+  attribute \src "ls180.v:1085.11-1085.39"
   wire width 6 $1\libresocsim_slave_sel[5:0]
-  attribute \src "ls180.v:1093.11-1093.41"
+  attribute \src "ls180.v:1086.11-1086.41"
   wire width 6 $1\libresocsim_slave_sel_r[5:0]
-  attribute \src "ls180.v:1342.11-1342.35"
+  attribute \src "ls180.v:1335.11-1335.35"
   wire width 2 $1\libresocsim_state[1:0]
-  attribute \src "ls180.v:167.5-167.39"
+  attribute \src "ls180.v:210.5-210.39"
   wire $1\libresocsim_update_value_re[0:0]
-  attribute \src "ls180.v:166.5-166.44"
+  attribute \src "ls180.v:209.5-209.44"
   wire $1\libresocsim_update_value_storage[0:0]
-  attribute \src "ls180.v:186.12-186.37"
+  attribute \src "ls180.v:229.12-229.37"
   wire width 32 $1\libresocsim_value[31:0]
-  attribute \src "ls180.v:168.12-168.44"
+  attribute \src "ls180.v:211.12-211.44"
   wire width 32 $1\libresocsim_value_status[31:0]
-  attribute \src "ls180.v:158.11-158.32"
-  wire width 8 $1\libresocsim_we[7:0]
-  attribute \src "ls180.v:174.5-174.34"
+  attribute \src "ls180.v:201.11-201.32"
+  wire width 4 $1\libresocsim_we[3:0]
+  attribute \src "ls180.v:217.5-217.34"
   wire $1\libresocsim_zero_clear[0:0]
-  attribute \src "ls180.v:175.5-175.40"
+  attribute \src "ls180.v:218.5-218.40"
   wire $1\libresocsim_zero_old_trigger[0:0]
-  attribute \src "ls180.v:172.5-172.36"
+  attribute \src "ls180.v:215.5-215.36"
   wire $1\libresocsim_zero_pending[0:0]
-  attribute \src "ls180.v:819.12-819.35"
+  attribute \src "ls180.v:820.12-820.35"
   wire width 30 $1\litedram_wb_adr[29:0]
-  attribute \src "ls180.v:823.5-823.27"
+  attribute \src "ls180.v:824.5-824.27"
   wire $1\litedram_wb_cyc[0:0]
-  attribute \src "ls180.v:820.12-820.37"
+  attribute \src "ls180.v:821.12-821.37"
   wire width 16 $1\litedram_wb_dat_w[15:0]
-  attribute \src "ls180.v:822.11-822.33"
+  attribute \src "ls180.v:823.11-823.33"
   wire width 2 $1\litedram_wb_sel[1:0]
-  attribute \src "ls180.v:824.5-824.27"
+  attribute \src "ls180.v:825.5-825.27"
   wire $1\litedram_wb_stb[0:0]
-  attribute \src "ls180.v:826.5-826.26"
+  attribute \src "ls180.v:827.5-827.26"
   wire $1\litedram_wb_we[0:0]
-  attribute \src "ls180.v:193.5-193.31"
+  attribute \src "ls180.v:236.5-236.31"
   wire $1\ram_bus_ram_bus_ack[0:0]
-  attribute \src "ls180.v:200.11-200.24"
-  wire width 8 $1\ram_we[7:0]
-  attribute \src "ls180.v:252.11-252.27"
+  attribute \src "ls180.v:243.11-243.24"
+  wire width 4 $1\ram_we[3:0]
+  attribute \src "ls180.v:265.11-265.27"
   wire width 3 $1\rddata_en[2:0]
-  attribute \src "ls180.v:1451.32-1451.44"
+  attribute \src "ls180.v:1444.32-1444.44"
   wire $1\regs0[0:0]
-  attribute \src "ls180.v:1452.32-1452.44"
+  attribute \src "ls180.v:1445.32-1445.44"
   wire $1\regs1[0:0]
-  attribute \src "ls180.v:1350.5-1350.28"
+  attribute \src "ls180.v:1343.5-1343.28"
   wire $1\rhs_array_muxed0[0:0]
-  attribute \src "ls180.v:1363.5-1363.29"
+  attribute \src "ls180.v:1356.5-1356.29"
   wire $1\rhs_array_muxed10[0:0]
-  attribute \src "ls180.v:1364.5-1364.29"
+  attribute \src "ls180.v:1357.5-1357.29"
   wire $1\rhs_array_muxed11[0:0]
-  attribute \src "ls180.v:1368.12-1368.37"
+  attribute \src "ls180.v:1361.12-1361.37"
   wire width 22 $1\rhs_array_muxed12[21:0]
-  attribute \src "ls180.v:1369.5-1369.29"
+  attribute \src "ls180.v:1362.5-1362.29"
   wire $1\rhs_array_muxed13[0:0]
-  attribute \src "ls180.v:1370.5-1370.29"
+  attribute \src "ls180.v:1363.5-1363.29"
   wire $1\rhs_array_muxed14[0:0]
-  attribute \src "ls180.v:1371.12-1371.37"
+  attribute \src "ls180.v:1364.12-1364.37"
   wire width 22 $1\rhs_array_muxed15[21:0]
-  attribute \src "ls180.v:1372.5-1372.29"
+  attribute \src "ls180.v:1365.5-1365.29"
   wire $1\rhs_array_muxed16[0:0]
-  attribute \src "ls180.v:1373.5-1373.29"
+  attribute \src "ls180.v:1366.5-1366.29"
   wire $1\rhs_array_muxed17[0:0]
-  attribute \src "ls180.v:1374.12-1374.37"
+  attribute \src "ls180.v:1367.12-1367.37"
   wire width 22 $1\rhs_array_muxed18[21:0]
-  attribute \src "ls180.v:1375.5-1375.29"
+  attribute \src "ls180.v:1368.5-1368.29"
   wire $1\rhs_array_muxed19[0:0]
-  attribute \src "ls180.v:1351.12-1351.36"
+  attribute \src "ls180.v:1344.12-1344.36"
   wire width 13 $1\rhs_array_muxed1[12:0]
-  attribute \src "ls180.v:1376.5-1376.29"
+  attribute \src "ls180.v:1369.5-1369.29"
   wire $1\rhs_array_muxed20[0:0]
-  attribute \src "ls180.v:1377.12-1377.37"
+  attribute \src "ls180.v:1370.12-1370.37"
   wire width 22 $1\rhs_array_muxed21[21:0]
-  attribute \src "ls180.v:1378.5-1378.29"
+  attribute \src "ls180.v:1371.5-1371.29"
   wire $1\rhs_array_muxed22[0:0]
-  attribute \src "ls180.v:1379.5-1379.29"
+  attribute \src "ls180.v:1372.5-1372.29"
   wire $1\rhs_array_muxed23[0:0]
-  attribute \src "ls180.v:1380.12-1380.37"
-  wire width 29 $1\rhs_array_muxed24[28:0]
-  attribute \src "ls180.v:1381.12-1381.37"
-  wire width 64 $1\rhs_array_muxed25[63:0]
-  attribute \src "ls180.v:1382.11-1382.35"
-  wire width 8 $1\rhs_array_muxed26[7:0]
-  attribute \src "ls180.v:1383.5-1383.29"
+  attribute \src "ls180.v:1373.12-1373.37"
+  wire width 30 $1\rhs_array_muxed24[29:0]
+  attribute \src "ls180.v:1374.12-1374.37"
+  wire width 32 $1\rhs_array_muxed25[31:0]
+  attribute \src "ls180.v:1375.11-1375.35"
+  wire width 4 $1\rhs_array_muxed26[3:0]
+  attribute \src "ls180.v:1376.5-1376.29"
   wire $1\rhs_array_muxed27[0:0]
-  attribute \src "ls180.v:1384.5-1384.29"
+  attribute \src "ls180.v:1377.5-1377.29"
   wire $1\rhs_array_muxed28[0:0]
-  attribute \src "ls180.v:1385.5-1385.29"
+  attribute \src "ls180.v:1378.5-1378.29"
   wire $1\rhs_array_muxed29[0:0]
-  attribute \src "ls180.v:1352.11-1352.34"
+  attribute \src "ls180.v:1345.11-1345.34"
   wire width 2 $1\rhs_array_muxed2[1:0]
-  attribute \src "ls180.v:1386.11-1386.35"
+  attribute \src "ls180.v:1379.11-1379.35"
   wire width 3 $1\rhs_array_muxed30[2:0]
-  attribute \src "ls180.v:1387.11-1387.35"
+  attribute \src "ls180.v:1380.11-1380.35"
   wire width 2 $1\rhs_array_muxed31[1:0]
-  attribute \src "ls180.v:1353.5-1353.28"
+  attribute \src "ls180.v:1346.5-1346.28"
   wire $1\rhs_array_muxed3[0:0]
-  attribute \src "ls180.v:1354.5-1354.28"
+  attribute \src "ls180.v:1347.5-1347.28"
   wire $1\rhs_array_muxed4[0:0]
-  attribute \src "ls180.v:1355.5-1355.28"
+  attribute \src "ls180.v:1348.5-1348.28"
   wire $1\rhs_array_muxed5[0:0]
-  attribute \src "ls180.v:1359.5-1359.28"
+  attribute \src "ls180.v:1352.5-1352.28"
   wire $1\rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:1360.12-1360.36"
+  attribute \src "ls180.v:1353.12-1353.36"
   wire width 13 $1\rhs_array_muxed7[12:0]
-  attribute \src "ls180.v:1361.11-1361.34"
+  attribute \src "ls180.v:1354.11-1354.34"
   wire width 2 $1\rhs_array_muxed8[1:0]
-  attribute \src "ls180.v:1362.5-1362.28"
+  attribute \src "ls180.v:1355.5-1355.28"
   wire $1\rhs_array_muxed9[0:0]
-  attribute \src "ls180.v:877.5-877.20"
+  attribute \src "ls180.v:878.5-878.20"
   wire $1\rx_clear[0:0]
-  attribute \src "ls180.v:961.11-961.33"
+  attribute \src "ls180.v:962.11-962.33"
   wire width 4 $1\rx_fifo_consume[3:0]
-  attribute \src "ls180.v:958.11-958.32"
+  attribute \src "ls180.v:959.11-959.32"
   wire width 5 $1\rx_fifo_level0[4:0]
-  attribute \src "ls180.v:960.11-960.33"
+  attribute \src "ls180.v:961.11-961.33"
   wire width 4 $1\rx_fifo_produce[3:0]
-  attribute \src "ls180.v:951.5-951.28"
+  attribute \src "ls180.v:952.5-952.28"
   wire $1\rx_fifo_readable[0:0]
-  attribute \src "ls180.v:962.11-962.36"
+  attribute \src "ls180.v:963.11-963.36"
   wire width 4 $1\rx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:878.5-878.26"
+  attribute \src "ls180.v:879.5-879.26"
   wire $1\rx_old_trigger[0:0]
-  attribute \src "ls180.v:875.5-875.22"
+  attribute \src "ls180.v:876.5-876.22"
   wire $1\rx_pending[0:0]
-  attribute \src "ls180.v:314.5-314.28"
+  attribute \src "ls180.v:327.5-327.28"
   wire $1\sdram_address_re[0:0]
-  attribute \src "ls180.v:313.12-313.41"
+  attribute \src "ls180.v:326.12-326.41"
   wire width 13 $1\sdram_address_storage[12:0]
-  attribute \src "ls180.v:316.5-316.29"
+  attribute \src "ls180.v:329.5-329.29"
   wire $1\sdram_baddress_re[0:0]
-  attribute \src "ls180.v:315.11-315.40"
+  attribute \src "ls180.v:328.11-328.40"
   wire width 2 $1\sdram_baddress_storage[1:0]
-  attribute \src "ls180.v:412.5-412.45"
+  attribute \src "ls180.v:425.5-425.45"
   wire $1\sdram_bankmachine0_auto_precharge[0:0]
-  attribute \src "ls180.v:434.11-434.65"
+  attribute \src "ls180.v:447.11-447.65"
   wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:431.11-431.63"
+  attribute \src "ls180.v:444.11-444.63"
   wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:433.11-433.65"
+  attribute \src "ls180.v:446.11-446.65"
   wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:435.11-435.68"
+  attribute \src "ls180.v:448.11-448.68"
   wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:458.5-458.54"
+  attribute \src "ls180.v:471.5-471.54"
   wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:459.5-459.53"
+  attribute \src "ls180.v:472.5-472.53"
   wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:461.12-461.69"
+  attribute \src "ls180.v:474.12-474.69"
   wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:460.5-460.59"
+  attribute \src "ls180.v:473.5-473.59"
   wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:456.5-456.54"
+  attribute \src "ls180.v:469.5-469.54"
   wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:404.12-404.52"
+  attribute \src "ls180.v:417.12-417.52"
   wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0]
-  attribute \src "ls180.v:406.5-406.46"
+  attribute \src "ls180.v:419.5-419.46"
   wire $1\sdram_bankmachine0_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:409.5-409.49"
+  attribute \src "ls180.v:422.5-422.49"
   wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:410.5-410.50"
+  attribute \src "ls180.v:423.5-423.50"
   wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:411.5-411.51"
+  attribute \src "ls180.v:424.5-424.51"
   wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:407.5-407.46"
+  attribute \src "ls180.v:420.5-420.46"
   wire $1\sdram_bankmachine0_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:408.5-408.45"
+  attribute \src "ls180.v:421.5-421.45"
   wire $1\sdram_bankmachine0_cmd_payload_we[0:0]
-  attribute \src "ls180.v:403.5-403.40"
+  attribute \src "ls180.v:416.5-416.40"
   wire $1\sdram_bankmachine0_cmd_ready[0:0]
-  attribute \src "ls180.v:402.5-402.40"
+  attribute \src "ls180.v:415.5-415.40"
   wire $1\sdram_bankmachine0_cmd_valid[0:0]
-  attribute \src "ls180.v:401.5-401.42"
+  attribute \src "ls180.v:414.5-414.42"
   wire $1\sdram_bankmachine0_refresh_gnt[0:0]
-  attribute \src "ls180.v:399.5-399.46"
+  attribute \src "ls180.v:412.5-412.46"
   wire $1\sdram_bankmachine0_req_rdata_valid[0:0]
-  attribute \src "ls180.v:398.5-398.46"
+  attribute \src "ls180.v:411.5-411.46"
   wire $1\sdram_bankmachine0_req_wdata_ready[0:0]
-  attribute \src "ls180.v:462.12-462.42"
+  attribute \src "ls180.v:475.12-475.42"
   wire width 13 $1\sdram_bankmachine0_row[12:0]
-  attribute \src "ls180.v:466.5-466.40"
+  attribute \src "ls180.v:479.5-479.40"
   wire $1\sdram_bankmachine0_row_close[0:0]
-  attribute \src "ls180.v:467.5-467.49"
+  attribute \src "ls180.v:480.5-480.49"
   wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:465.5-465.39"
+  attribute \src "ls180.v:478.5-478.39"
   wire $1\sdram_bankmachine0_row_open[0:0]
-  attribute \src "ls180.v:463.5-463.41"
+  attribute \src "ls180.v:476.5-476.41"
   wire $1\sdram_bankmachine0_row_opened[0:0]
-  attribute \src "ls180.v:470.11-470.50"
+  attribute \src "ls180.v:483.11-483.50"
   wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0]
-  attribute \src "ls180.v:469.32-469.71"
+  attribute \src "ls180.v:482.32-482.71"
   wire $1\sdram_bankmachine0_twtpcon_ready[0:0]
-  attribute \src "ls180.v:494.5-494.45"
+  attribute \src "ls180.v:507.5-507.45"
   wire $1\sdram_bankmachine1_auto_precharge[0:0]
-  attribute \src "ls180.v:516.11-516.65"
+  attribute \src "ls180.v:529.11-529.65"
   wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:513.11-513.63"
+  attribute \src "ls180.v:526.11-526.63"
   wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:515.11-515.65"
+  attribute \src "ls180.v:528.11-528.65"
   wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:517.11-517.68"
+  attribute \src "ls180.v:530.11-530.68"
   wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:540.5-540.54"
+  attribute \src "ls180.v:553.5-553.54"
   wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:541.5-541.53"
+  attribute \src "ls180.v:554.5-554.53"
   wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:543.12-543.69"
+  attribute \src "ls180.v:556.12-556.69"
   wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:542.5-542.59"
+  attribute \src "ls180.v:555.5-555.59"
   wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:538.5-538.54"
+  attribute \src "ls180.v:551.5-551.54"
   wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:486.12-486.52"
+  attribute \src "ls180.v:499.12-499.52"
   wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0]
-  attribute \src "ls180.v:488.5-488.46"
+  attribute \src "ls180.v:501.5-501.46"
   wire $1\sdram_bankmachine1_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:491.5-491.49"
+  attribute \src "ls180.v:504.5-504.49"
   wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:492.5-492.50"
+  attribute \src "ls180.v:505.5-505.50"
   wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:493.5-493.51"
+  attribute \src "ls180.v:506.5-506.51"
   wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:489.5-489.46"
+  attribute \src "ls180.v:502.5-502.46"
   wire $1\sdram_bankmachine1_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:490.5-490.45"
+  attribute \src "ls180.v:503.5-503.45"
   wire $1\sdram_bankmachine1_cmd_payload_we[0:0]
-  attribute \src "ls180.v:485.5-485.40"
+  attribute \src "ls180.v:498.5-498.40"
   wire $1\sdram_bankmachine1_cmd_ready[0:0]
-  attribute \src "ls180.v:484.5-484.40"
+  attribute \src "ls180.v:497.5-497.40"
   wire $1\sdram_bankmachine1_cmd_valid[0:0]
-  attribute \src "ls180.v:483.5-483.42"
+  attribute \src "ls180.v:496.5-496.42"
   wire $1\sdram_bankmachine1_refresh_gnt[0:0]
-  attribute \src "ls180.v:481.5-481.46"
+  attribute \src "ls180.v:494.5-494.46"
   wire $1\sdram_bankmachine1_req_rdata_valid[0:0]
-  attribute \src "ls180.v:480.5-480.46"
+  attribute \src "ls180.v:493.5-493.46"
   wire $1\sdram_bankmachine1_req_wdata_ready[0:0]
-  attribute \src "ls180.v:544.12-544.42"
+  attribute \src "ls180.v:557.12-557.42"
   wire width 13 $1\sdram_bankmachine1_row[12:0]
-  attribute \src "ls180.v:548.5-548.40"
+  attribute \src "ls180.v:561.5-561.40"
   wire $1\sdram_bankmachine1_row_close[0:0]
-  attribute \src "ls180.v:549.5-549.49"
+  attribute \src "ls180.v:562.5-562.49"
   wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:547.5-547.39"
+  attribute \src "ls180.v:560.5-560.39"
   wire $1\sdram_bankmachine1_row_open[0:0]
-  attribute \src "ls180.v:545.5-545.41"
+  attribute \src "ls180.v:558.5-558.41"
   wire $1\sdram_bankmachine1_row_opened[0:0]
-  attribute \src "ls180.v:552.11-552.50"
+  attribute \src "ls180.v:565.11-565.50"
   wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0]
-  attribute \src "ls180.v:551.32-551.71"
+  attribute \src "ls180.v:564.32-564.71"
   wire $1\sdram_bankmachine1_twtpcon_ready[0:0]
-  attribute \src "ls180.v:576.5-576.45"
+  attribute \src "ls180.v:589.5-589.45"
   wire $1\sdram_bankmachine2_auto_precharge[0:0]
-  attribute \src "ls180.v:598.11-598.65"
+  attribute \src "ls180.v:611.11-611.65"
   wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:595.11-595.63"
+  attribute \src "ls180.v:608.11-608.63"
   wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:597.11-597.65"
+  attribute \src "ls180.v:610.11-610.65"
   wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:599.11-599.68"
+  attribute \src "ls180.v:612.11-612.68"
   wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:622.5-622.54"
+  attribute \src "ls180.v:635.5-635.54"
   wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:623.5-623.53"
+  attribute \src "ls180.v:636.5-636.53"
   wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:625.12-625.69"
+  attribute \src "ls180.v:638.12-638.69"
   wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:624.5-624.59"
+  attribute \src "ls180.v:637.5-637.59"
   wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:620.5-620.54"
+  attribute \src "ls180.v:633.5-633.54"
   wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:568.12-568.52"
+  attribute \src "ls180.v:581.12-581.52"
   wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0]
-  attribute \src "ls180.v:570.5-570.46"
+  attribute \src "ls180.v:583.5-583.46"
   wire $1\sdram_bankmachine2_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:573.5-573.49"
+  attribute \src "ls180.v:586.5-586.49"
   wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:574.5-574.50"
+  attribute \src "ls180.v:587.5-587.50"
   wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:575.5-575.51"
+  attribute \src "ls180.v:588.5-588.51"
   wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:571.5-571.46"
+  attribute \src "ls180.v:584.5-584.46"
   wire $1\sdram_bankmachine2_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:572.5-572.45"
+  attribute \src "ls180.v:585.5-585.45"
   wire $1\sdram_bankmachine2_cmd_payload_we[0:0]
-  attribute \src "ls180.v:567.5-567.40"
+  attribute \src "ls180.v:580.5-580.40"
   wire $1\sdram_bankmachine2_cmd_ready[0:0]
-  attribute \src "ls180.v:566.5-566.40"
+  attribute \src "ls180.v:579.5-579.40"
   wire $1\sdram_bankmachine2_cmd_valid[0:0]
-  attribute \src "ls180.v:565.5-565.42"
+  attribute \src "ls180.v:578.5-578.42"
   wire $1\sdram_bankmachine2_refresh_gnt[0:0]
-  attribute \src "ls180.v:563.5-563.46"
+  attribute \src "ls180.v:576.5-576.46"
   wire $1\sdram_bankmachine2_req_rdata_valid[0:0]
-  attribute \src "ls180.v:562.5-562.46"
+  attribute \src "ls180.v:575.5-575.46"
   wire $1\sdram_bankmachine2_req_wdata_ready[0:0]
-  attribute \src "ls180.v:626.12-626.42"
+  attribute \src "ls180.v:639.12-639.42"
   wire width 13 $1\sdram_bankmachine2_row[12:0]
-  attribute \src "ls180.v:630.5-630.40"
+  attribute \src "ls180.v:643.5-643.40"
   wire $1\sdram_bankmachine2_row_close[0:0]
-  attribute \src "ls180.v:631.5-631.49"
+  attribute \src "ls180.v:644.5-644.49"
   wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:629.5-629.39"
+  attribute \src "ls180.v:642.5-642.39"
   wire $1\sdram_bankmachine2_row_open[0:0]
-  attribute \src "ls180.v:627.5-627.41"
+  attribute \src "ls180.v:640.5-640.41"
   wire $1\sdram_bankmachine2_row_opened[0:0]
-  attribute \src "ls180.v:634.11-634.50"
+  attribute \src "ls180.v:647.11-647.50"
   wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0]
-  attribute \src "ls180.v:633.32-633.71"
+  attribute \src "ls180.v:646.32-646.71"
   wire $1\sdram_bankmachine2_twtpcon_ready[0:0]
-  attribute \src "ls180.v:658.5-658.45"
+  attribute \src "ls180.v:671.5-671.45"
   wire $1\sdram_bankmachine3_auto_precharge[0:0]
-  attribute \src "ls180.v:680.11-680.65"
+  attribute \src "ls180.v:693.11-693.65"
   wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
-  attribute \src "ls180.v:677.11-677.63"
+  attribute \src "ls180.v:690.11-690.63"
   wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
-  attribute \src "ls180.v:679.11-679.65"
+  attribute \src "ls180.v:692.11-692.65"
   wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
-  attribute \src "ls180.v:681.11-681.68"
+  attribute \src "ls180.v:694.11-694.68"
   wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
-  attribute \src "ls180.v:704.5-704.54"
+  attribute \src "ls180.v:717.5-717.54"
   wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0]
-  attribute \src "ls180.v:705.5-705.53"
+  attribute \src "ls180.v:718.5-718.53"
   wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0]
-  attribute \src "ls180.v:707.12-707.69"
+  attribute \src "ls180.v:720.12-720.69"
   wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
-  attribute \src "ls180.v:706.5-706.59"
+  attribute \src "ls180.v:719.5-719.59"
   wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
-  attribute \src "ls180.v:702.5-702.54"
+  attribute \src "ls180.v:715.5-715.54"
   wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
-  attribute \src "ls180.v:650.12-650.52"
+  attribute \src "ls180.v:663.12-663.52"
   wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0]
-  attribute \src "ls180.v:652.5-652.46"
+  attribute \src "ls180.v:665.5-665.46"
   wire $1\sdram_bankmachine3_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:655.5-655.49"
+  attribute \src "ls180.v:668.5-668.49"
   wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
-  attribute \src "ls180.v:656.5-656.50"
+  attribute \src "ls180.v:669.5-669.50"
   wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0]
-  attribute \src "ls180.v:657.5-657.51"
+  attribute \src "ls180.v:670.5-670.51"
   wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0]
-  attribute \src "ls180.v:653.5-653.46"
+  attribute \src "ls180.v:666.5-666.46"
   wire $1\sdram_bankmachine3_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:654.5-654.45"
+  attribute \src "ls180.v:667.5-667.45"
   wire $1\sdram_bankmachine3_cmd_payload_we[0:0]
-  attribute \src "ls180.v:649.5-649.40"
+  attribute \src "ls180.v:662.5-662.40"
   wire $1\sdram_bankmachine3_cmd_ready[0:0]
-  attribute \src "ls180.v:648.5-648.40"
+  attribute \src "ls180.v:661.5-661.40"
   wire $1\sdram_bankmachine3_cmd_valid[0:0]
-  attribute \src "ls180.v:647.5-647.42"
+  attribute \src "ls180.v:660.5-660.42"
   wire $1\sdram_bankmachine3_refresh_gnt[0:0]
-  attribute \src "ls180.v:645.5-645.46"
+  attribute \src "ls180.v:658.5-658.46"
   wire $1\sdram_bankmachine3_req_rdata_valid[0:0]
-  attribute \src "ls180.v:644.5-644.46"
+  attribute \src "ls180.v:657.5-657.46"
   wire $1\sdram_bankmachine3_req_wdata_ready[0:0]
-  attribute \src "ls180.v:708.12-708.42"
+  attribute \src "ls180.v:721.12-721.42"
   wire width 13 $1\sdram_bankmachine3_row[12:0]
-  attribute \src "ls180.v:712.5-712.40"
+  attribute \src "ls180.v:725.5-725.40"
   wire $1\sdram_bankmachine3_row_close[0:0]
-  attribute \src "ls180.v:713.5-713.49"
+  attribute \src "ls180.v:726.5-726.49"
   wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0]
-  attribute \src "ls180.v:711.5-711.39"
+  attribute \src "ls180.v:724.5-724.39"
   wire $1\sdram_bankmachine3_row_open[0:0]
-  attribute \src "ls180.v:709.5-709.41"
+  attribute \src "ls180.v:722.5-722.41"
   wire $1\sdram_bankmachine3_row_opened[0:0]
-  attribute \src "ls180.v:716.11-716.50"
+  attribute \src "ls180.v:729.11-729.50"
   wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0]
-  attribute \src "ls180.v:715.32-715.71"
+  attribute \src "ls180.v:728.32-728.71"
   wire $1\sdram_bankmachine3_twtpcon_ready[0:0]
-  attribute \src "ls180.v:731.5-731.44"
+  attribute \src "ls180.v:744.5-744.44"
   wire $1\sdram_choose_cmd_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:732.5-732.44"
+  attribute \src "ls180.v:745.5-745.44"
   wire $1\sdram_choose_cmd_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:733.5-733.43"
+  attribute \src "ls180.v:746.5-746.43"
   wire $1\sdram_choose_cmd_cmd_payload_we[0:0]
-  attribute \src "ls180.v:739.11-739.40"
+  attribute \src "ls180.v:752.11-752.40"
   wire width 2 $1\sdram_choose_cmd_grant[1:0]
-  attribute \src "ls180.v:737.11-737.41"
+  attribute \src "ls180.v:750.11-750.41"
   wire width 4 $1\sdram_choose_cmd_valids[3:0]
-  attribute \src "ls180.v:749.5-749.44"
+  attribute \src "ls180.v:762.5-762.44"
   wire $1\sdram_choose_req_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:750.5-750.44"
+  attribute \src "ls180.v:763.5-763.44"
   wire $1\sdram_choose_req_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:751.5-751.43"
+  attribute \src "ls180.v:764.5-764.43"
   wire $1\sdram_choose_req_cmd_payload_we[0:0]
-  attribute \src "ls180.v:746.5-746.38"
+  attribute \src "ls180.v:759.5-759.38"
   wire $1\sdram_choose_req_cmd_ready[0:0]
-  attribute \src "ls180.v:757.11-757.40"
+  attribute \src "ls180.v:770.11-770.40"
   wire width 2 $1\sdram_choose_req_grant[1:0]
-  attribute \src "ls180.v:755.11-755.41"
+  attribute \src "ls180.v:768.11-768.41"
   wire width 4 $1\sdram_choose_req_valids[3:0]
-  attribute \src "ls180.v:744.5-744.43"
+  attribute \src "ls180.v:757.5-757.43"
   wire $1\sdram_choose_req_want_activates[0:0]
-  attribute \src "ls180.v:741.5-741.39"
+  attribute \src "ls180.v:754.5-754.39"
   wire $1\sdram_choose_req_want_reads[0:0]
-  attribute \src "ls180.v:742.5-742.40"
+  attribute \src "ls180.v:755.5-755.40"
   wire $1\sdram_choose_req_want_writes[0:0]
-  attribute \src "ls180.v:370.5-370.26"
+  attribute \src "ls180.v:383.5-383.26"
   wire $1\sdram_cmd_last[0:0]
-  attribute \src "ls180.v:371.12-371.39"
+  attribute \src "ls180.v:384.12-384.39"
   wire width 13 $1\sdram_cmd_payload_a[12:0]
-  attribute \src "ls180.v:372.11-372.38"
+  attribute \src "ls180.v:385.11-385.38"
   wire width 2 $1\sdram_cmd_payload_ba[1:0]
-  attribute \src "ls180.v:373.5-373.33"
+  attribute \src "ls180.v:386.5-386.33"
   wire $1\sdram_cmd_payload_cas[0:0]
-  attribute \src "ls180.v:374.5-374.33"
+  attribute \src "ls180.v:387.5-387.33"
   wire $1\sdram_cmd_payload_ras[0:0]
-  attribute \src "ls180.v:375.5-375.32"
+  attribute \src "ls180.v:388.5-388.32"
   wire $1\sdram_cmd_payload_we[0:0]
-  attribute \src "ls180.v:369.5-369.27"
+  attribute \src "ls180.v:382.5-382.27"
   wire $1\sdram_cmd_ready[0:0]
-  attribute \src "ls180.v:368.5-368.27"
+  attribute \src "ls180.v:381.5-381.27"
   wire $1\sdram_cmd_valid[0:0]
-  attribute \src "ls180.v:308.5-308.28"
+  attribute \src "ls180.v:321.5-321.28"
   wire $1\sdram_command_re[0:0]
-  attribute \src "ls180.v:307.11-307.39"
+  attribute \src "ls180.v:320.11-320.39"
   wire width 6 $1\sdram_command_storage[5:0]
-  attribute \src "ls180.v:352.12-352.40"
+  attribute \src "ls180.v:365.12-365.40"
   wire width 13 $1\sdram_dfi_p0_address[12:0]
-  attribute \src "ls180.v:353.11-353.35"
+  attribute \src "ls180.v:366.11-366.35"
   wire width 2 $1\sdram_dfi_p0_bank[1:0]
-  attribute \src "ls180.v:354.5-354.30"
+  attribute \src "ls180.v:367.5-367.30"
   wire $1\sdram_dfi_p0_cas_n[0:0]
-  attribute \src "ls180.v:355.5-355.29"
+  attribute \src "ls180.v:368.5-368.29"
   wire $1\sdram_dfi_p0_cs_n[0:0]
-  attribute \src "ls180.v:356.5-356.30"
+  attribute \src "ls180.v:369.5-369.30"
   wire $1\sdram_dfi_p0_ras_n[0:0]
-  attribute \src "ls180.v:365.5-365.34"
+  attribute \src "ls180.v:378.5-378.34"
   wire $1\sdram_dfi_p0_rddata_en[0:0]
-  attribute \src "ls180.v:357.5-357.29"
+  attribute \src "ls180.v:370.5-370.29"
   wire $1\sdram_dfi_p0_we_n[0:0]
-  attribute \src "ls180.v:363.5-363.34"
+  attribute \src "ls180.v:376.5-376.34"
   wire $1\sdram_dfi_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:776.5-776.21"
+  attribute \src "ls180.v:789.5-789.21"
   wire $1\sdram_en0[0:0]
-  attribute \src "ls180.v:779.5-779.21"
+  attribute \src "ls180.v:792.5-792.21"
   wire $1\sdram_en1[0:0]
-  attribute \src "ls180.v:349.12-349.41"
+  attribute \src "ls180.v:362.12-362.41"
   wire width 16 $1\sdram_interface_wdata[15:0]
-  attribute \src "ls180.v:350.11-350.42"
+  attribute \src "ls180.v:363.11-363.42"
   wire width 2 $1\sdram_interface_wdata_we[1:0]
-  attribute \src "ls180.v:255.5-255.31"
+  attribute \src "ls180.v:268.5-268.31"
   wire $1\sdram_inti_p0_cas_n[0:0]
-  attribute \src "ls180.v:256.5-256.30"
+  attribute \src "ls180.v:269.5-269.30"
   wire $1\sdram_inti_p0_cs_n[0:0]
-  attribute \src "ls180.v:257.5-257.31"
+  attribute \src "ls180.v:270.5-270.31"
   wire $1\sdram_inti_p0_ras_n[0:0]
-  attribute \src "ls180.v:267.12-267.40"
+  attribute \src "ls180.v:280.12-280.40"
   wire width 16 $1\sdram_inti_p0_rddata[15:0]
-  attribute \src "ls180.v:268.5-268.38"
+  attribute \src "ls180.v:281.5-281.38"
   wire $1\sdram_inti_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:258.5-258.30"
+  attribute \src "ls180.v:271.5-271.30"
   wire $1\sdram_inti_p0_we_n[0:0]
-  attribute \src "ls180.v:294.5-294.33"
+  attribute \src "ls180.v:307.5-307.33"
   wire $1\sdram_master_p0_act_n[0:0]
-  attribute \src "ls180.v:285.12-285.43"
+  attribute \src "ls180.v:298.12-298.43"
   wire width 13 $1\sdram_master_p0_address[12:0]
-  attribute \src "ls180.v:286.11-286.38"
+  attribute \src "ls180.v:299.11-299.38"
   wire width 2 $1\sdram_master_p0_bank[1:0]
-  attribute \src "ls180.v:287.5-287.33"
+  attribute \src "ls180.v:300.5-300.33"
   wire $1\sdram_master_p0_cas_n[0:0]
-  attribute \src "ls180.v:291.5-291.31"
+  attribute \src "ls180.v:304.5-304.31"
   wire $1\sdram_master_p0_cke[0:0]
-  attribute \src "ls180.v:288.5-288.32"
+  attribute \src "ls180.v:301.5-301.32"
   wire $1\sdram_master_p0_cs_n[0:0]
-  attribute \src "ls180.v:292.5-292.31"
+  attribute \src "ls180.v:305.5-305.31"
   wire $1\sdram_master_p0_odt[0:0]
-  attribute \src "ls180.v:289.5-289.33"
+  attribute \src "ls180.v:302.5-302.33"
   wire $1\sdram_master_p0_ras_n[0:0]
-  attribute \src "ls180.v:298.5-298.37"
+  attribute \src "ls180.v:311.5-311.37"
   wire $1\sdram_master_p0_rddata_en[0:0]
-  attribute \src "ls180.v:293.5-293.35"
+  attribute \src "ls180.v:306.5-306.35"
   wire $1\sdram_master_p0_reset_n[0:0]
-  attribute \src "ls180.v:290.5-290.32"
+  attribute \src "ls180.v:303.5-303.32"
   wire $1\sdram_master_p0_we_n[0:0]
-  attribute \src "ls180.v:295.12-295.42"
+  attribute \src "ls180.v:308.12-308.42"
   wire width 16 $1\sdram_master_p0_wrdata[15:0]
-  attribute \src "ls180.v:296.5-296.37"
+  attribute \src "ls180.v:309.5-309.37"
   wire $1\sdram_master_p0_wrdata_en[0:0]
-  attribute \src "ls180.v:297.11-297.45"
+  attribute \src "ls180.v:310.11-310.45"
   wire width 2 $1\sdram_master_p0_wrdata_mask[1:0]
-  attribute \src "ls180.v:386.5-386.33"
+  attribute \src "ls180.v:399.5-399.33"
   wire $1\sdram_postponer_count[0:0]
-  attribute \src "ls180.v:385.5-385.33"
+  attribute \src "ls180.v:398.5-398.33"
   wire $1\sdram_postponer_req_o[0:0]
-  attribute \src "ls180.v:306.5-306.20"
+  attribute \src "ls180.v:319.5-319.20"
   wire $1\sdram_re[0:0]
-  attribute \src "ls180.v:392.5-392.33"
+  attribute \src "ls180.v:405.5-405.33"
   wire $1\sdram_sequencer_count[0:0]
-  attribute \src "ls180.v:391.11-391.41"
+  attribute \src "ls180.v:404.11-404.41"
   wire width 4 $1\sdram_sequencer_counter[3:0]
-  attribute \src "ls180.v:390.5-390.33"
+  attribute \src "ls180.v:403.5-403.33"
   wire $1\sdram_sequencer_done1[0:0]
-  attribute \src "ls180.v:387.5-387.34"
+  attribute \src "ls180.v:400.5-400.34"
   wire $1\sdram_sequencer_start0[0:0]
-  attribute \src "ls180.v:283.12-283.41"
+  attribute \src "ls180.v:296.12-296.41"
   wire width 16 $1\sdram_slave_p0_rddata[15:0]
-  attribute \src "ls180.v:284.5-284.39"
+  attribute \src "ls180.v:297.5-297.39"
   wire $1\sdram_slave_p0_rddata_valid[0:0]
-  attribute \src "ls180.v:319.12-319.32"
+  attribute \src "ls180.v:332.12-332.32"
   wire width 16 $1\sdram_status[15:0]
-  attribute \src "ls180.v:761.11-761.35"
+  attribute \src "ls180.v:774.11-774.35"
   wire width 2 $1\sdram_steerer_sel[1:0]
-  attribute \src "ls180.v:305.11-305.31"
+  attribute \src "ls180.v:318.11-318.31"
   wire width 4 $1\sdram_storage[3:0]
-  attribute \src "ls180.v:770.5-770.31"
+  attribute \src "ls180.v:783.5-783.31"
   wire $1\sdram_tccdcon_count[0:0]
-  attribute \src "ls180.v:769.32-769.58"
+  attribute \src "ls180.v:782.32-782.58"
   wire $1\sdram_tccdcon_ready[0:0]
-  attribute \src "ls180.v:778.11-778.29"
+  attribute \src "ls180.v:791.11-791.29"
   wire width 5 $1\sdram_time0[4:0]
-  attribute \src "ls180.v:781.11-781.29"
+  attribute \src "ls180.v:794.11-794.29"
   wire width 4 $1\sdram_time1[3:0]
-  attribute \src "ls180.v:383.11-383.39"
+  attribute \src "ls180.v:396.11-396.39"
   wire width 10 $1\sdram_timer_count1[9:0]
-  attribute \src "ls180.v:773.11-773.37"
+  attribute \src "ls180.v:786.11-786.37"
   wire width 3 $1\sdram_twtrcon_count[2:0]
-  attribute \src "ls180.v:772.32-772.58"
+  attribute \src "ls180.v:785.32-785.58"
   wire $1\sdram_twtrcon_ready[0:0]
-  attribute \src "ls180.v:318.5-318.27"
+  attribute \src "ls180.v:331.5-331.27"
   wire $1\sdram_wrdata_re[0:0]
-  attribute \src "ls180.v:317.12-317.40"
+  attribute \src "ls180.v:330.12-330.40"
   wire width 16 $1\sdram_wrdata_storage[15:0]
-  attribute \src "ls180.v:810.5-810.49"
-  wire $1\socbushandler_converted_interface_ack[0:0]
-  attribute \src "ls180.v:816.5-816.33"
-  wire $1\socbushandler_counter[0:0]
-  attribute \src "ls180.v:1017.5-1017.68"
-  wire $1\socbushandler_counter_subfragments_converter2_next_value[0:0]
-  attribute \src "ls180.v:1018.5-1018.71"
-  wire $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
-  attribute \src "ls180.v:818.12-818.39"
-  wire width 64 $1\socbushandler_dat_r[63:0]
-  attribute \src "ls180.v:815.5-815.30"
-  wire $1\socbushandler_skip[0:0]
-  attribute \src "ls180.v:1022.11-1022.54"
+  attribute \src "ls180.v:1023.11-1023.54"
   wire width 3 $1\subfragments_bankmachine0_next_state[2:0]
-  attribute \src "ls180.v:1021.11-1021.49"
+  attribute \src "ls180.v:1022.11-1022.49"
   wire width 3 $1\subfragments_bankmachine0_state[2:0]
-  attribute \src "ls180.v:1024.11-1024.54"
+  attribute \src "ls180.v:1025.11-1025.54"
   wire width 3 $1\subfragments_bankmachine1_next_state[2:0]
-  attribute \src "ls180.v:1023.11-1023.49"
+  attribute \src "ls180.v:1024.11-1024.49"
   wire width 3 $1\subfragments_bankmachine1_state[2:0]
-  attribute \src "ls180.v:1026.11-1026.54"
+  attribute \src "ls180.v:1027.11-1027.54"
   wire width 3 $1\subfragments_bankmachine2_next_state[2:0]
-  attribute \src "ls180.v:1025.11-1025.49"
+  attribute \src "ls180.v:1026.11-1026.49"
   wire width 3 $1\subfragments_bankmachine2_state[2:0]
-  attribute \src "ls180.v:1028.11-1028.54"
+  attribute \src "ls180.v:1029.11-1029.54"
   wire width 3 $1\subfragments_bankmachine3_next_state[2:0]
-  attribute \src "ls180.v:1027.11-1027.49"
+  attribute \src "ls180.v:1028.11-1028.49"
   wire width 3 $1\subfragments_bankmachine3_state[2:0]
-  attribute \src "ls180.v:1008.5-1008.46"
+  attribute \src "ls180.v:1009.5-1009.46"
   wire $1\subfragments_converter0_next_state[0:0]
-  attribute \src "ls180.v:1007.5-1007.41"
+  attribute \src "ls180.v:1008.5-1008.41"
   wire $1\subfragments_converter0_state[0:0]
-  attribute \src "ls180.v:1012.5-1012.46"
+  attribute \src "ls180.v:1013.5-1013.46"
   wire $1\subfragments_converter1_next_state[0:0]
-  attribute \src "ls180.v:1011.5-1011.41"
+  attribute \src "ls180.v:1012.5-1012.41"
   wire $1\subfragments_converter1_state[0:0]
-  attribute \src "ls180.v:1016.5-1016.46"
+  attribute \src "ls180.v:1017.5-1017.46"
   wire $1\subfragments_converter2_next_state[0:0]
-  attribute \src "ls180.v:1015.5-1015.41"
+  attribute \src "ls180.v:1016.5-1016.41"
   wire $1\subfragments_converter2_state[0:0]
-  attribute \src "ls180.v:1030.11-1030.53"
+  attribute \src "ls180.v:1031.11-1031.53"
   wire width 3 $1\subfragments_multiplexer_next_state[2:0]
-  attribute \src "ls180.v:1029.11-1029.48"
+  attribute \src "ls180.v:1030.11-1030.48"
   wire width 3 $1\subfragments_multiplexer_state[2:0]
-  attribute \src "ls180.v:1048.5-1048.48"
-  wire $1\subfragments_new_master_rdata_valid0[0:0]
   attribute \src "ls180.v:1049.5-1049.48"
-  wire $1\subfragments_new_master_rdata_valid1[0:0]
+  wire $1\subfragments_new_master_rdata_valid0[0:0]
   attribute \src "ls180.v:1050.5-1050.48"
-  wire $1\subfragments_new_master_rdata_valid2[0:0]
+  wire $1\subfragments_new_master_rdata_valid1[0:0]
   attribute \src "ls180.v:1051.5-1051.48"
+  wire $1\subfragments_new_master_rdata_valid2[0:0]
+  attribute \src "ls180.v:1052.5-1052.48"
   wire $1\subfragments_new_master_rdata_valid3[0:0]
-  attribute \src "ls180.v:1047.5-1047.47"
+  attribute \src "ls180.v:1048.5-1048.47"
   wire $1\subfragments_new_master_wdata_ready[0:0]
-  attribute \src "ls180.v:1053.5-1053.35"
+  attribute \src "ls180.v:1054.5-1054.35"
   wire $1\subfragments_next_state[0:0]
-  attribute \src "ls180.v:1020.11-1020.51"
+  attribute \src "ls180.v:1021.11-1021.51"
   wire width 2 $1\subfragments_refresher_next_state[1:0]
-  attribute \src "ls180.v:1019.11-1019.46"
+  attribute \src "ls180.v:1020.11-1020.46"
   wire width 2 $1\subfragments_refresher_state[1:0]
-  attribute \src "ls180.v:1052.5-1052.30"
+  attribute \src "ls180.v:1053.5-1053.30"
   wire $1\subfragments_state[0:0]
-  attribute \src "ls180.v:1356.5-1356.26"
+  attribute \src "ls180.v:1349.5-1349.26"
   wire $1\t_array_muxed0[0:0]
-  attribute \src "ls180.v:1357.5-1357.26"
+  attribute \src "ls180.v:1350.5-1350.26"
   wire $1\t_array_muxed1[0:0]
-  attribute \src "ls180.v:1358.5-1358.26"
+  attribute \src "ls180.v:1351.5-1351.26"
   wire $1\t_array_muxed2[0:0]
-  attribute \src "ls180.v:1365.5-1365.26"
+  attribute \src "ls180.v:1358.5-1358.26"
   wire $1\t_array_muxed3[0:0]
-  attribute \src "ls180.v:1366.5-1366.26"
+  attribute \src "ls180.v:1359.5-1359.26"
   wire $1\t_array_muxed4[0:0]
-  attribute \src "ls180.v:1367.5-1367.26"
+  attribute \src "ls180.v:1360.5-1360.26"
   wire $1\t_array_muxed5[0:0]
-  attribute \src "ls180.v:872.5-872.20"
+  attribute \src "ls180.v:873.5-873.20"
   wire $1\tx_clear[0:0]
-  attribute \src "ls180.v:924.11-924.33"
+  attribute \src "ls180.v:925.11-925.33"
   wire width 4 $1\tx_fifo_consume[3:0]
-  attribute \src "ls180.v:921.11-921.32"
+  attribute \src "ls180.v:922.11-922.32"
   wire width 5 $1\tx_fifo_level0[4:0]
-  attribute \src "ls180.v:923.11-923.33"
+  attribute \src "ls180.v:924.11-924.33"
   wire width 4 $1\tx_fifo_produce[3:0]
-  attribute \src "ls180.v:914.5-914.28"
+  attribute \src "ls180.v:915.5-915.28"
   wire $1\tx_fifo_readable[0:0]
-  attribute \src "ls180.v:925.11-925.36"
+  attribute \src "ls180.v:926.11-926.36"
   wire width 4 $1\tx_fifo_wrport_adr[3:0]
-  attribute \src "ls180.v:873.5-873.26"
+  attribute \src "ls180.v:874.5-874.26"
   wire $1\tx_old_trigger[0:0]
-  attribute \src "ls180.v:870.5-870.22"
+  attribute \src "ls180.v:871.5-871.22"
   wire $1\tx_pending[0:0]
-  attribute \src "ls180.v:854.12-854.49"
+  attribute \src "ls180.v:855.12-855.49"
   wire width 32 $1\uart_phy_phase_accumulator_rx[31:0]
-  attribute \src "ls180.v:844.12-844.49"
+  attribute \src "ls180.v:845.12-845.49"
   wire width 32 $1\uart_phy_phase_accumulator_tx[31:0]
-  attribute \src "ls180.v:837.5-837.23"
+  attribute \src "ls180.v:838.5-838.23"
   wire $1\uart_phy_re[0:0]
-  attribute \src "ls180.v:858.11-858.38"
+  attribute \src "ls180.v:859.11-859.38"
   wire width 4 $1\uart_phy_rx_bitcount[3:0]
-  attribute \src "ls180.v:859.5-859.28"
+  attribute \src "ls180.v:860.5-860.28"
   wire $1\uart_phy_rx_busy[0:0]
-  attribute \src "ls180.v:856.5-856.25"
+  attribute \src "ls180.v:857.5-857.25"
   wire $1\uart_phy_rx_r[0:0]
-  attribute \src "ls180.v:857.11-857.33"
+  attribute \src "ls180.v:858.11-858.33"
   wire width 8 $1\uart_phy_rx_reg[7:0]
-  attribute \src "ls180.v:839.5-839.31"
+  attribute \src "ls180.v:840.5-840.31"
   wire $1\uart_phy_sink_ready[0:0]
-  attribute \src "ls180.v:852.11-852.46"
+  attribute \src "ls180.v:853.11-853.46"
   wire width 8 $1\uart_phy_source_payload_data[7:0]
-  attribute \src "ls180.v:848.5-848.33"
+  attribute \src "ls180.v:849.5-849.33"
   wire $1\uart_phy_source_valid[0:0]
-  attribute \src "ls180.v:836.12-836.42"
+  attribute \src "ls180.v:837.12-837.42"
   wire width 32 $1\uart_phy_storage[31:0]
-  attribute \src "ls180.v:846.11-846.38"
+  attribute \src "ls180.v:847.11-847.38"
   wire width 4 $1\uart_phy_tx_bitcount[3:0]
-  attribute \src "ls180.v:847.5-847.28"
+  attribute \src "ls180.v:848.5-848.28"
   wire $1\uart_phy_tx_busy[0:0]
-  attribute \src "ls180.v:845.11-845.33"
+  attribute \src "ls180.v:846.11-846.33"
   wire width 8 $1\uart_phy_tx_reg[7:0]
-  attribute \src "ls180.v:853.5-853.34"
+  attribute \src "ls180.v:854.5-854.34"
   wire $1\uart_phy_uart_clk_rxen[0:0]
-  attribute \src "ls180.v:843.5-843.34"
+  attribute \src "ls180.v:844.5-844.34"
   wire $1\uart_phy_uart_clk_txen[0:0]
-  attribute \src "ls180.v:802.5-802.24"
+  attribute \src "ls180.v:815.5-815.24"
   wire $1\wb_sdram_ack[0:0]
-  attribute \src "ls180.v:796.12-796.32"
-  wire width 30 $1\wb_sdram_adr[29:0]
-  attribute \src "ls180.v:800.5-800.24"
-  wire $1\wb_sdram_cyc[0:0]
-  attribute \src "ls180.v:797.12-797.34"
-  wire width 32 $1\wb_sdram_dat_w[31:0]
-  attribute \src "ls180.v:799.11-799.30"
-  wire width 4 $1\wb_sdram_sel[3:0]
-  attribute \src "ls180.v:801.5-801.24"
-  wire $1\wb_sdram_stb[0:0]
-  attribute \src "ls180.v:803.5-803.23"
-  wire $1\wb_sdram_we[0:0]
-  attribute \src "ls180.v:832.5-832.26"
+  attribute \src "ls180.v:833.5-833.26"
   wire $1\wdata_consumed[0:0]
-  attribute \src "ls180.v:1568.64-1568.89"
-  wire $add$ls180.v:1568$33_Y
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+  attribute \src "ls180.v:3338.46-3338.166"
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+  attribute \src "ls180.v:3357.20-3357.81"
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+  wire $and$ls180.v:3358$998_Y
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+  attribute \src "ls180.v:4030.21-4030.79"
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+  attribute \src "ls180.v:4044.21-4044.117"
+  wire $and$ls180.v:4044$1201_Y
+  attribute \src "ls180.v:4047.22-4047.55"
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+  attribute \src "ls180.v:4047.21-4047.84"
+  wire $and$ls180.v:4047$1203_Y
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+  wire $and$ls180.v:4061$1208_Y
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+  attribute \src "ls180.v:4233.57-4233.97"
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+  attribute \src "ls180.v:4361.8-4361.57"
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+  attribute \src "ls180.v:4361.7-4361.87"
+  wire $and$ls180.v:4361$1259_Y
+  attribute \src "ls180.v:4380.7-4380.65"
+  wire $and$ls180.v:4380$1263_Y
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+  attribute \src "ls180.v:4392.7-4392.46"
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+  attribute \src "ls180.v:4420.7-4420.65"
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+  wire $and$ls180.v:4508$1299_Y
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+  wire $and$ls180.v:4554$1315_Y
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+  wire $and$ls180.v:4560$1320_Y
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+  wire $and$ls180.v:4600$1331_Y
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+  wire $and$ls180.v:4606$1336_Y
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+  wire $and$ls180.v:4803$1364_Y
+  attribute \src "ls180.v:4803.217-4803.293"
+  wire $and$ls180.v:4803$1367_Y
+  attribute \src "ls180.v:4803.299-4803.375"
+  wire $and$ls180.v:4803$1370_Y
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+  wire $and$ls180.v:4804$1376_Y
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+  wire $and$ls180.v:4804$1379_Y
+  attribute \src "ls180.v:4804.300-4804.376"
+  wire $and$ls180.v:4804$1382_Y
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+  wire $and$ls180.v:4831$1390_Y
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+  wire $and$ls180.v:4917$1414_Y
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+  wire $and$ls180.v:4933$1420_Y
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+  wire $and$ls180.v:4939$1425_Y
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+  attribute \src "ls180.v:1676.37-1676.91"
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+  attribute \src "ls180.v:1683.11-1683.49"
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+  attribute \src "ls180.v:2599.373-2599.444"
+  wire $eq$ls180.v:2599$347_Y
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+  attribute \src "ls180.v:2600.373-2600.444"
+  wire $eq$ls180.v:2600$360_Y
+  attribute \src "ls180.v:2629.68-2629.98"
+  wire $eq$ls180.v:2629$369_Y
+  attribute \src "ls180.v:2632.68-2632.98"
+  wire $eq$ls180.v:2632$372_Y
+  attribute \src "ls180.v:2638.68-2638.98"
+  wire $eq$ls180.v:2638$376_Y
+  attribute \src "ls180.v:2641.68-2641.98"
+  wire $eq$ls180.v:2641$379_Y
   attribute \src "ls180.v:2647.68-2647.98"
-  wire $eq$ls180.v:2647$404_Y
-  attribute \src "ls180.v:2653.68-2653.98"
-  wire $eq$ls180.v:2653$408_Y
+  wire $eq$ls180.v:2647$383_Y
+  attribute \src "ls180.v:2650.68-2650.98"
+  wire $eq$ls180.v:2650$386_Y
   attribute \src "ls180.v:2656.68-2656.98"
-  wire $eq$ls180.v:2656$411_Y
-  attribute \src "ls180.v:2662.68-2662.98"
-  wire $eq$ls180.v:2662$415_Y
-  attribute \src "ls180.v:2665.68-2665.98"
-  wire $eq$ls180.v:2665$418_Y
-  attribute \src "ls180.v:2671.68-2671.98"
-  wire $eq$ls180.v:2671$422_Y
-  attribute \src "ls180.v:2674.68-2674.98"
-  wire $eq$ls180.v:2674$425_Y
+  wire $eq$ls180.v:2656$390_Y
+  attribute \src "ls180.v:2659.68-2659.98"
+  wire $eq$ls180.v:2659$393_Y
+  attribute \src "ls180.v:2740.47-2740.82"
+  wire $eq$ls180.v:2740$416_Y
+  attribute \src "ls180.v:2740.145-2740.183"
+  wire $eq$ls180.v:2740$417_Y
+  attribute \src "ls180.v:2740.220-2740.258"
+  wire $eq$ls180.v:2740$420_Y
+  attribute \src "ls180.v:2740.295-2740.333"
+  wire $eq$ls180.v:2740$423_Y
+  attribute \src "ls180.v:2745.47-2745.82"
+  wire $eq$ls180.v:2745$432_Y
+  attribute \src "ls180.v:2745.145-2745.183"
+  wire $eq$ls180.v:2745$433_Y
+  attribute \src "ls180.v:2745.220-2745.258"
+  wire $eq$ls180.v:2745$436_Y
+  attribute \src "ls180.v:2745.295-2745.333"
+  wire $eq$ls180.v:2745$439_Y
+  attribute \src "ls180.v:2750.47-2750.82"
+  wire $eq$ls180.v:2750$448_Y
+  attribute \src "ls180.v:2750.145-2750.183"
+  wire $eq$ls180.v:2750$449_Y
+  attribute \src "ls180.v:2750.220-2750.258"
+  wire $eq$ls180.v:2750$452_Y
+  attribute \src "ls180.v:2750.295-2750.333"
+  wire $eq$ls180.v:2750$455_Y
   attribute \src "ls180.v:2755.47-2755.82"
-  wire $eq$ls180.v:2755$448_Y
+  wire $eq$ls180.v:2755$464_Y
   attribute \src "ls180.v:2755.145-2755.183"
-  wire $eq$ls180.v:2755$449_Y
+  wire $eq$ls180.v:2755$465_Y
   attribute \src "ls180.v:2755.220-2755.258"
-  wire $eq$ls180.v:2755$452_Y
+  wire $eq$ls180.v:2755$468_Y
   attribute \src "ls180.v:2755.295-2755.333"
-  wire $eq$ls180.v:2755$455_Y
-  attribute \src "ls180.v:2760.47-2760.82"
-  wire $eq$ls180.v:2760$464_Y
-  attribute \src "ls180.v:2760.145-2760.183"
-  wire $eq$ls180.v:2760$465_Y
-  attribute \src "ls180.v:2760.220-2760.258"
-  wire $eq$ls180.v:2760$468_Y
-  attribute \src "ls180.v:2760.295-2760.333"
-  wire $eq$ls180.v:2760$471_Y
-  attribute \src "ls180.v:2765.47-2765.82"
-  wire $eq$ls180.v:2765$480_Y
-  attribute \src "ls180.v:2765.145-2765.183"
-  wire $eq$ls180.v:2765$481_Y
-  attribute \src "ls180.v:2765.220-2765.258"
-  wire $eq$ls180.v:2765$484_Y
-  attribute \src "ls180.v:2765.295-2765.333"
-  wire $eq$ls180.v:2765$487_Y
-  attribute \src "ls180.v:2770.47-2770.82"
-  wire $eq$ls180.v:2770$496_Y
-  attribute \src "ls180.v:2770.145-2770.183"
-  wire $eq$ls180.v:2770$497_Y
-  attribute \src "ls180.v:2770.220-2770.258"
-  wire $eq$ls180.v:2770$500_Y
-  attribute \src "ls180.v:2770.295-2770.333"
-  wire $eq$ls180.v:2770$503_Y
-  attribute \src "ls180.v:2775.39-2775.77"
-  wire $eq$ls180.v:2775$512_Y
-  attribute \src "ls180.v:2775.83-2775.118"
-  wire $eq$ls180.v:2775$513_Y
-  attribute \src "ls180.v:2775.181-2775.219"
-  wire $eq$ls180.v:2775$514_Y
-  attribute \src "ls180.v:2775.256-2775.294"
-  wire $eq$ls180.v:2775$517_Y
-  attribute \src "ls180.v:2775.331-2775.369"
-  wire $eq$ls180.v:2775$520_Y
-  attribute \src "ls180.v:2775.413-2775.451"
-  wire $eq$ls180.v:2775$528_Y
-  attribute \src "ls180.v:2775.457-2775.492"
-  wire $eq$ls180.v:2775$529_Y
-  attribute \src "ls180.v:2775.555-2775.593"
-  wire $eq$ls180.v:2775$530_Y
-  attribute \src "ls180.v:2775.630-2775.668"
-  wire $eq$ls180.v:2775$533_Y
-  attribute \src "ls180.v:2775.705-2775.743"
-  wire $eq$ls180.v:2775$536_Y
-  attribute \src "ls180.v:2775.787-2775.825"
-  wire $eq$ls180.v:2775$544_Y
-  attribute \src "ls180.v:2775.831-2775.866"
-  wire $eq$ls180.v:2775$545_Y
-  attribute \src "ls180.v:2775.929-2775.967"
-  wire $eq$ls180.v:2775$546_Y
-  attribute \src "ls180.v:2775.1004-2775.1042"
-  wire $eq$ls180.v:2775$549_Y
-  attribute \src "ls180.v:2775.1079-2775.1117"
-  wire $eq$ls180.v:2775$552_Y
-  attribute \src "ls180.v:2775.1161-2775.1199"
-  wire $eq$ls180.v:2775$560_Y
-  attribute \src "ls180.v:2775.1205-2775.1240"
-  wire $eq$ls180.v:2775$561_Y
-  attribute \src "ls180.v:2775.1303-2775.1341"
-  wire $eq$ls180.v:2775$562_Y
-  attribute \src "ls180.v:2775.1378-2775.1416"
-  wire $eq$ls180.v:2775$565_Y
-  attribute \src "ls180.v:2775.1453-2775.1491"
-  wire $eq$ls180.v:2775$568_Y
-  attribute \src "ls180.v:2834.24-2834.47"
-  wire $eq$ls180.v:2834$581_Y
-  attribute \src "ls180.v:2841.11-2841.36"
-  wire $eq$ls180.v:2841$586_Y
-  attribute \src "ls180.v:3098.67-3098.92"
-  wire $eq$ls180.v:3098$658_Y
-  attribute \src "ls180.v:3099.67-3099.92"
-  wire $eq$ls180.v:3099$660_Y
-  attribute \src "ls180.v:3100.70-3100.95"
-  wire $eq$ls180.v:3100$662_Y
-  attribute \src "ls180.v:3101.67-3101.92"
-  wire $eq$ls180.v:3101$664_Y
-  attribute \src "ls180.v:3102.67-3102.92"
-  wire $eq$ls180.v:3102$666_Y
-  attribute \src "ls180.v:3103.70-3103.95"
-  wire $eq$ls180.v:3103$668_Y
-  attribute \src "ls180.v:3107.31-3107.67"
-  wire $eq$ls180.v:3107$671_Y
-  attribute \src "ls180.v:3108.31-3108.68"
-  wire $eq$ls180.v:3108$672_Y
-  attribute \src "ls180.v:3109.31-3109.76"
-  wire $eq$ls180.v:3109$673_Y
-  attribute \src "ls180.v:3110.31-3110.73"
-  wire $eq$ls180.v:3110$674_Y
-  attribute \src "ls180.v:3111.31-3111.69"
-  wire $eq$ls180.v:3111$675_Y
-  attribute \src "ls180.v:3112.31-3112.73"
-  wire $eq$ls180.v:3112$676_Y
-  attribute \src "ls180.v:3176.28-3176.53"
-  wire $eq$ls180.v:3176$708_Y
-  attribute \src "ls180.v:3177.36-3177.85"
-  wire $eq$ls180.v:3177$709_Y
-  attribute \src "ls180.v:3179.109-3179.157"
-  wire $eq$ls180.v:3179$711_Y
-  attribute \src "ls180.v:3180.112-3180.160"
-  wire $eq$ls180.v:3180$715_Y
-  attribute \src "ls180.v:3182.111-3182.159"
-  wire $eq$ls180.v:3182$718_Y
-  attribute \src "ls180.v:3183.114-3183.162"
-  wire $eq$ls180.v:3183$722_Y
-  attribute \src "ls180.v:3185.111-3185.159"
-  wire $eq$ls180.v:3185$725_Y
-  attribute \src "ls180.v:3186.114-3186.162"
-  wire $eq$ls180.v:3186$729_Y
-  attribute \src "ls180.v:3188.111-3188.159"
-  wire $eq$ls180.v:3188$732_Y
-  attribute \src "ls180.v:3189.114-3189.162"
-  wire $eq$ls180.v:3189$736_Y
-  attribute \src "ls180.v:3191.111-3191.159"
-  wire $eq$ls180.v:3191$739_Y
-  attribute \src "ls180.v:3192.114-3192.162"
-  wire $eq$ls180.v:3192$743_Y
-  attribute \src "ls180.v:3194.114-3194.162"
-  wire $eq$ls180.v:3194$746_Y
-  attribute \src "ls180.v:3195.117-3195.165"
-  wire $eq$ls180.v:3195$750_Y
-  attribute \src "ls180.v:3197.114-3197.162"
-  wire $eq$ls180.v:3197$753_Y
-  attribute \src "ls180.v:3198.117-3198.165"
-  wire $eq$ls180.v:3198$757_Y
-  attribute \src "ls180.v:3200.114-3200.162"
-  wire $eq$ls180.v:3200$760_Y
-  attribute \src "ls180.v:3201.117-3201.165"
-  wire $eq$ls180.v:3201$764_Y
-  attribute \src "ls180.v:3203.114-3203.162"
-  wire $eq$ls180.v:3203$767_Y
-  attribute \src "ls180.v:3204.117-3204.165"
-  wire $eq$ls180.v:3204$771_Y
-  attribute \src "ls180.v:3215.36-3215.85"
-  wire $eq$ls180.v:3215$773_Y
-  attribute \src "ls180.v:3217.106-3217.154"
-  wire $eq$ls180.v:3217$775_Y
-  attribute \src "ls180.v:3218.109-3218.157"
-  wire $eq$ls180.v:3218$779_Y
-  attribute \src "ls180.v:3220.105-3220.153"
-  wire $eq$ls180.v:3220$782_Y
-  attribute \src "ls180.v:3221.108-3221.156"
-  wire $eq$ls180.v:3221$786_Y
-  attribute \src "ls180.v:3223.107-3223.155"
-  wire $eq$ls180.v:3223$789_Y
-  attribute \src "ls180.v:3224.110-3224.158"
-  wire $eq$ls180.v:3224$793_Y
-  attribute \src "ls180.v:3229.36-3229.85"
-  wire $eq$ls180.v:3229$795_Y
-  attribute \src "ls180.v:3231.106-3231.154"
-  wire $eq$ls180.v:3231$797_Y
-  attribute \src "ls180.v:3232.109-3232.157"
-  wire $eq$ls180.v:3232$801_Y
-  attribute \src "ls180.v:3234.105-3234.153"
-  wire $eq$ls180.v:3234$804_Y
-  attribute \src "ls180.v:3235.108-3235.156"
-  wire $eq$ls180.v:3235$808_Y
-  attribute \src "ls180.v:3237.107-3237.155"
-  wire $eq$ls180.v:3237$811_Y
-  attribute \src "ls180.v:3238.110-3238.158"
-  wire $eq$ls180.v:3238$815_Y
-  attribute \src "ls180.v:3243.36-3243.85"
-  wire $eq$ls180.v:3243$817_Y
-  attribute \src "ls180.v:3245.105-3245.151"
-  wire $eq$ls180.v:3245$819_Y
-  attribute \src "ls180.v:3246.108-3246.154"
-  wire $eq$ls180.v:3246$823_Y
-  attribute \src "ls180.v:3248.104-3248.150"
-  wire $eq$ls180.v:3248$826_Y
-  attribute \src "ls180.v:3249.107-3249.153"
-  wire $eq$ls180.v:3249$830_Y
-  attribute \src "ls180.v:3257.36-3257.85"
-  wire $eq$ls180.v:3257$832_Y
-  attribute \src "ls180.v:3259.116-3259.164"
-  wire $eq$ls180.v:3259$834_Y
-  attribute \src "ls180.v:3260.119-3260.167"
-  wire $eq$ls180.v:3260$838_Y
-  attribute \src "ls180.v:3262.120-3262.168"
-  wire $eq$ls180.v:3262$841_Y
-  attribute \src "ls180.v:3263.123-3263.171"
-  wire $eq$ls180.v:3263$845_Y
-  attribute \src "ls180.v:3265.101-3265.149"
-  wire $eq$ls180.v:3265$848_Y
-  attribute \src "ls180.v:3266.104-3266.152"
-  wire $eq$ls180.v:3266$852_Y
-  attribute \src "ls180.v:3268.120-3268.168"
-  wire $eq$ls180.v:3268$855_Y
-  attribute \src "ls180.v:3269.123-3269.171"
-  wire $eq$ls180.v:3269$859_Y
-  attribute \src "ls180.v:3271.120-3271.168"
-  wire $eq$ls180.v:3271$862_Y
-  attribute \src "ls180.v:3272.123-3272.171"
-  wire $eq$ls180.v:3272$866_Y
-  attribute \src "ls180.v:3274.121-3274.169"
-  wire $eq$ls180.v:3274$869_Y
-  attribute \src "ls180.v:3275.124-3275.172"
-  wire $eq$ls180.v:3275$873_Y
-  attribute \src "ls180.v:3277.119-3277.167"
-  wire $eq$ls180.v:3277$876_Y
-  attribute \src "ls180.v:3278.122-3278.170"
-  wire $eq$ls180.v:3278$880_Y
-  attribute \src "ls180.v:3280.119-3280.167"
-  wire $eq$ls180.v:3280$883_Y
-  attribute \src "ls180.v:3281.122-3281.170"
-  wire $eq$ls180.v:3281$887_Y
-  attribute \src "ls180.v:3283.119-3283.167"
-  wire $eq$ls180.v:3283$890_Y
-  attribute \src "ls180.v:3284.122-3284.170"
-  wire $eq$ls180.v:3284$894_Y
-  attribute \src "ls180.v:3286.119-3286.167"
-  wire $eq$ls180.v:3286$897_Y
-  attribute \src "ls180.v:3287.122-3287.170"
-  wire $eq$ls180.v:3287$901_Y
-  attribute \src "ls180.v:3302.36-3302.85"
-  wire $eq$ls180.v:3302$903_Y
-  attribute \src "ls180.v:3304.108-3304.156"
-  wire $eq$ls180.v:3304$905_Y
-  attribute \src "ls180.v:3305.111-3305.159"
-  wire $eq$ls180.v:3305$909_Y
-  attribute \src "ls180.v:3307.108-3307.156"
-  wire $eq$ls180.v:3307$912_Y
-  attribute \src "ls180.v:3308.111-3308.159"
-  wire $eq$ls180.v:3308$916_Y
-  attribute \src "ls180.v:3310.108-3310.156"
-  wire $eq$ls180.v:3310$919_Y
-  attribute \src "ls180.v:3311.111-3311.159"
-  wire $eq$ls180.v:3311$923_Y
-  attribute \src "ls180.v:3313.108-3313.156"
-  wire $eq$ls180.v:3313$926_Y
-  attribute \src "ls180.v:3314.111-3314.159"
-  wire $eq$ls180.v:3314$930_Y
-  attribute \src "ls180.v:3316.110-3316.158"
-  wire $eq$ls180.v:3316$933_Y
-  attribute \src "ls180.v:3317.113-3317.161"
-  wire $eq$ls180.v:3317$937_Y
-  attribute \src "ls180.v:3319.110-3319.158"
-  wire $eq$ls180.v:3319$940_Y
-  attribute \src "ls180.v:3320.113-3320.161"
-  wire $eq$ls180.v:3320$944_Y
-  attribute \src "ls180.v:3322.110-3322.158"
-  wire $eq$ls180.v:3322$947_Y
-  attribute \src "ls180.v:3323.113-3323.161"
-  wire $eq$ls180.v:3323$951_Y
-  attribute \src "ls180.v:3325.110-3325.158"
-  wire $eq$ls180.v:3325$954_Y
-  attribute \src "ls180.v:3326.113-3326.161"
-  wire $eq$ls180.v:3326$958_Y
-  attribute \src "ls180.v:3328.106-3328.154"
-  wire $eq$ls180.v:3328$961_Y
-  attribute \src "ls180.v:3329.109-3329.157"
-  wire $eq$ls180.v:3329$965_Y
-  attribute \src "ls180.v:3331.116-3331.164"
-  wire $eq$ls180.v:3331$968_Y
-  attribute \src "ls180.v:3332.119-3332.167"
-  wire $eq$ls180.v:3332$972_Y
-  attribute \src "ls180.v:3334.109-3334.158"
-  wire $eq$ls180.v:3334$975_Y
-  attribute \src "ls180.v:3335.112-3335.161"
-  wire $eq$ls180.v:3335$979_Y
-  attribute \src "ls180.v:3337.109-3337.158"
-  wire $eq$ls180.v:3337$982_Y
-  attribute \src "ls180.v:3338.112-3338.161"
-  wire $eq$ls180.v:3338$986_Y
-  attribute \src "ls180.v:3340.109-3340.158"
-  wire $eq$ls180.v:3340$989_Y
-  attribute \src "ls180.v:3341.112-3341.161"
-  wire $eq$ls180.v:3341$993_Y
-  attribute \src "ls180.v:3343.109-3343.158"
-  wire $eq$ls180.v:3343$996_Y
-  attribute \src "ls180.v:3344.112-3344.161"
-  wire $eq$ls180.v:3344$1000_Y
-  attribute \src "ls180.v:3346.113-3346.162"
-  wire $eq$ls180.v:3346$1003_Y
-  attribute \src "ls180.v:3347.116-3347.165"
-  wire $eq$ls180.v:3347$1007_Y
-  attribute \src "ls180.v:3349.114-3349.163"
-  wire $eq$ls180.v:3349$1010_Y
-  attribute \src "ls180.v:3350.117-3350.166"
-  wire $eq$ls180.v:3350$1014_Y
-  attribute \src "ls180.v:3352.113-3352.162"
-  wire $eq$ls180.v:3352$1017_Y
-  attribute \src "ls180.v:3353.116-3353.165"
-  wire $eq$ls180.v:3353$1021_Y
-  attribute \src "ls180.v:3370.36-3370.85"
-  wire $eq$ls180.v:3370$1023_Y
-  attribute \src "ls180.v:3372.86-3372.134"
-  wire $eq$ls180.v:3372$1025_Y
-  attribute \src "ls180.v:3373.89-3373.137"
-  wire $eq$ls180.v:3373$1029_Y
-  attribute \src "ls180.v:3375.109-3375.157"
-  wire $eq$ls180.v:3375$1032_Y
-  attribute \src "ls180.v:3376.112-3376.160"
-  wire $eq$ls180.v:3376$1036_Y
-  attribute \src "ls180.v:3378.110-3378.158"
-  wire $eq$ls180.v:3378$1039_Y
-  attribute \src "ls180.v:3379.113-3379.161"
-  wire $eq$ls180.v:3379$1043_Y
-  attribute \src "ls180.v:3381.101-3381.149"
-  wire $eq$ls180.v:3381$1046_Y
-  attribute \src "ls180.v:3382.104-3382.152"
-  wire $eq$ls180.v:3382$1050_Y
-  attribute \src "ls180.v:3384.102-3384.150"
-  wire $eq$ls180.v:3384$1053_Y
-  attribute \src "ls180.v:3385.105-3385.153"
-  wire $eq$ls180.v:3385$1057_Y
-  attribute \src "ls180.v:3387.113-3387.161"
-  wire $eq$ls180.v:3387$1060_Y
-  attribute \src "ls180.v:3388.116-3388.164"
-  wire $eq$ls180.v:3388$1064_Y
-  attribute \src "ls180.v:3390.110-3390.158"
-  wire $eq$ls180.v:3390$1067_Y
-  attribute \src "ls180.v:3391.113-3391.161"
-  wire $eq$ls180.v:3391$1071_Y
-  attribute \src "ls180.v:3393.109-3393.157"
-  wire $eq$ls180.v:3393$1074_Y
-  attribute \src "ls180.v:3394.112-3394.160"
-  wire $eq$ls180.v:3394$1078_Y
-  attribute \src "ls180.v:3404.36-3404.85"
-  wire $eq$ls180.v:3404$1080_Y
-  attribute \src "ls180.v:3406.115-3406.163"
-  wire $eq$ls180.v:3406$1082_Y
-  attribute \src "ls180.v:3407.118-3407.166"
-  wire $eq$ls180.v:3407$1086_Y
-  attribute \src "ls180.v:3409.115-3409.163"
-  wire $eq$ls180.v:3409$1089_Y
-  attribute \src "ls180.v:3410.118-3410.166"
-  wire $eq$ls180.v:3410$1093_Y
-  attribute \src "ls180.v:3412.115-3412.163"
-  wire $eq$ls180.v:3412$1096_Y
-  attribute \src "ls180.v:3413.118-3413.166"
-  wire $eq$ls180.v:3413$1100_Y
-  attribute \src "ls180.v:3415.115-3415.163"
-  wire $eq$ls180.v:3415$1103_Y
-  attribute \src "ls180.v:3416.118-3416.166"
-  wire $eq$ls180.v:3416$1107_Y
-  attribute \src "ls180.v:3776.28-3776.63"
-  wire $eq$ls180.v:3776$1137_Y
-  attribute \src "ls180.v:3776.126-3776.164"
-  wire $eq$ls180.v:3776$1138_Y
-  attribute \src "ls180.v:3776.201-3776.239"
-  wire $eq$ls180.v:3776$1141_Y
-  attribute \src "ls180.v:3776.276-3776.314"
-  wire $eq$ls180.v:3776$1144_Y
-  attribute \src "ls180.v:3800.28-3800.63"
-  wire $eq$ls180.v:3800$1153_Y
-  attribute \src "ls180.v:3800.126-3800.164"
-  wire $eq$ls180.v:3800$1154_Y
-  attribute \src "ls180.v:3800.201-3800.239"
-  wire $eq$ls180.v:3800$1157_Y
-  attribute \src "ls180.v:3800.276-3800.314"
-  wire $eq$ls180.v:3800$1160_Y
-  attribute \src "ls180.v:3824.28-3824.63"
-  wire $eq$ls180.v:3824$1169_Y
-  attribute \src "ls180.v:3824.126-3824.164"
-  wire $eq$ls180.v:3824$1170_Y
-  attribute \src "ls180.v:3824.201-3824.239"
-  wire $eq$ls180.v:3824$1173_Y
-  attribute \src "ls180.v:3824.276-3824.314"
-  wire $eq$ls180.v:3824$1176_Y
-  attribute \src "ls180.v:3848.28-3848.63"
-  wire $eq$ls180.v:3848$1185_Y
-  attribute \src "ls180.v:3848.126-3848.164"
-  wire $eq$ls180.v:3848$1186_Y
-  attribute \src "ls180.v:3848.201-3848.239"
-  wire $eq$ls180.v:3848$1189_Y
-  attribute \src "ls180.v:3848.276-3848.314"
-  wire $eq$ls180.v:3848$1192_Y
-  attribute \src "ls180.v:4380.8-4380.33"
-  wire $eq$ls180.v:4380$1292_Y
-  attribute \src "ls180.v:4415.8-4415.37"
-  wire $eq$ls180.v:4415$1303_Y
-  attribute \src "ls180.v:4435.33-4435.64"
-  wire $eq$ls180.v:4435$1306_Y
+  wire $eq$ls180.v:2755$471_Y
+  attribute \src "ls180.v:2760.39-2760.77"
+  wire $eq$ls180.v:2760$480_Y
+  attribute \src "ls180.v:2760.83-2760.118"
+  wire $eq$ls180.v:2760$481_Y
+  attribute \src "ls180.v:2760.181-2760.219"
+  wire $eq$ls180.v:2760$482_Y
+  attribute \src "ls180.v:2760.256-2760.294"
+  wire $eq$ls180.v:2760$485_Y
+  attribute \src "ls180.v:2760.331-2760.369"
+  wire $eq$ls180.v:2760$488_Y
+  attribute \src "ls180.v:2760.413-2760.451"
+  wire $eq$ls180.v:2760$496_Y
+  attribute \src "ls180.v:2760.457-2760.492"
+  wire $eq$ls180.v:2760$497_Y
+  attribute \src "ls180.v:2760.555-2760.593"
+  wire $eq$ls180.v:2760$498_Y
+  attribute \src "ls180.v:2760.630-2760.668"
+  wire $eq$ls180.v:2760$501_Y
+  attribute \src "ls180.v:2760.705-2760.743"
+  wire $eq$ls180.v:2760$504_Y
+  attribute \src "ls180.v:2760.787-2760.825"
+  wire $eq$ls180.v:2760$512_Y
+  attribute \src "ls180.v:2760.831-2760.866"
+  wire $eq$ls180.v:2760$513_Y
+  attribute \src "ls180.v:2760.929-2760.967"
+  wire $eq$ls180.v:2760$514_Y
+  attribute \src "ls180.v:2760.1004-2760.1042"
+  wire $eq$ls180.v:2760$517_Y
+  attribute \src "ls180.v:2760.1079-2760.1117"
+  wire $eq$ls180.v:2760$520_Y
+  attribute \src "ls180.v:2760.1161-2760.1199"
+  wire $eq$ls180.v:2760$528_Y
+  attribute \src "ls180.v:2760.1205-2760.1240"
+  wire $eq$ls180.v:2760$529_Y
+  attribute \src "ls180.v:2760.1303-2760.1341"
+  wire $eq$ls180.v:2760$530_Y
+  attribute \src "ls180.v:2760.1378-2760.1416"
+  wire $eq$ls180.v:2760$533_Y
+  attribute \src "ls180.v:2760.1453-2760.1491"
+  wire $eq$ls180.v:2760$536_Y
+  attribute \src "ls180.v:2819.24-2819.47"
+  wire $eq$ls180.v:2819$549_Y
+  attribute \src "ls180.v:2826.11-2826.36"
+  wire $eq$ls180.v:2826$554_Y
+  attribute \src "ls180.v:3083.84-3083.109"
+  wire $eq$ls180.v:3083$626_Y
+  attribute \src "ls180.v:3084.84-3084.109"
+  wire $eq$ls180.v:3084$628_Y
+  attribute \src "ls180.v:3085.84-3085.109"
+  wire $eq$ls180.v:3085$630_Y
+  attribute \src "ls180.v:3086.84-3086.109"
+  wire $eq$ls180.v:3086$632_Y
+  attribute \src "ls180.v:3087.84-3087.109"
+  wire $eq$ls180.v:3087$634_Y
+  attribute \src "ls180.v:3088.84-3088.109"
+  wire $eq$ls180.v:3088$636_Y
+  attribute \src "ls180.v:3092.31-3092.67"
+  wire $eq$ls180.v:3092$639_Y
+  attribute \src "ls180.v:3093.31-3093.68"
+  wire $eq$ls180.v:3093$640_Y
+  attribute \src "ls180.v:3094.31-3094.76"
+  wire $eq$ls180.v:3094$641_Y
+  attribute \src "ls180.v:3095.31-3095.74"
+  wire $eq$ls180.v:3095$642_Y
+  attribute \src "ls180.v:3096.31-3096.69"
+  wire $eq$ls180.v:3096$643_Y
+  attribute \src "ls180.v:3097.31-3097.73"
+  wire $eq$ls180.v:3097$644_Y
+  attribute \src "ls180.v:3161.28-3161.53"
+  wire $eq$ls180.v:3161$676_Y
+  attribute \src "ls180.v:3162.36-3162.85"
+  wire $eq$ls180.v:3162$677_Y
+  attribute \src "ls180.v:3164.109-3164.157"
+  wire $eq$ls180.v:3164$679_Y
+  attribute \src "ls180.v:3165.112-3165.160"
+  wire $eq$ls180.v:3165$683_Y
+  attribute \src "ls180.v:3167.111-3167.159"
+  wire $eq$ls180.v:3167$686_Y
+  attribute \src "ls180.v:3168.114-3168.162"
+  wire $eq$ls180.v:3168$690_Y
+  attribute \src "ls180.v:3170.111-3170.159"
+  wire $eq$ls180.v:3170$693_Y
+  attribute \src "ls180.v:3171.114-3171.162"
+  wire $eq$ls180.v:3171$697_Y
+  attribute \src "ls180.v:3173.111-3173.159"
+  wire $eq$ls180.v:3173$700_Y
+  attribute \src "ls180.v:3174.114-3174.162"
+  wire $eq$ls180.v:3174$704_Y
+  attribute \src "ls180.v:3176.111-3176.159"
+  wire $eq$ls180.v:3176$707_Y
+  attribute \src "ls180.v:3177.114-3177.162"
+  wire $eq$ls180.v:3177$711_Y
+  attribute \src "ls180.v:3179.114-3179.162"
+  wire $eq$ls180.v:3179$714_Y
+  attribute \src "ls180.v:3180.117-3180.165"
+  wire $eq$ls180.v:3180$718_Y
+  attribute \src "ls180.v:3182.114-3182.162"
+  wire $eq$ls180.v:3182$721_Y
+  attribute \src "ls180.v:3183.117-3183.165"
+  wire $eq$ls180.v:3183$725_Y
+  attribute \src "ls180.v:3185.114-3185.162"
+  wire $eq$ls180.v:3185$728_Y
+  attribute \src "ls180.v:3186.117-3186.165"
+  wire $eq$ls180.v:3186$732_Y
+  attribute \src "ls180.v:3188.114-3188.162"
+  wire $eq$ls180.v:3188$735_Y
+  attribute \src "ls180.v:3189.117-3189.165"
+  wire $eq$ls180.v:3189$739_Y
+  attribute \src "ls180.v:3200.36-3200.85"
+  wire $eq$ls180.v:3200$741_Y
+  attribute \src "ls180.v:3202.106-3202.154"
+  wire $eq$ls180.v:3202$743_Y
+  attribute \src "ls180.v:3203.109-3203.157"
+  wire $eq$ls180.v:3203$747_Y
+  attribute \src "ls180.v:3205.105-3205.153"
+  wire $eq$ls180.v:3205$750_Y
+  attribute \src "ls180.v:3206.108-3206.156"
+  wire $eq$ls180.v:3206$754_Y
+  attribute \src "ls180.v:3208.107-3208.155"
+  wire $eq$ls180.v:3208$757_Y
+  attribute \src "ls180.v:3209.110-3209.158"
+  wire $eq$ls180.v:3209$761_Y
+  attribute \src "ls180.v:3214.36-3214.85"
+  wire $eq$ls180.v:3214$763_Y
+  attribute \src "ls180.v:3216.106-3216.154"
+  wire $eq$ls180.v:3216$765_Y
+  attribute \src "ls180.v:3217.109-3217.157"
+  wire $eq$ls180.v:3217$769_Y
+  attribute \src "ls180.v:3219.105-3219.153"
+  wire $eq$ls180.v:3219$772_Y
+  attribute \src "ls180.v:3220.108-3220.156"
+  wire $eq$ls180.v:3220$776_Y
+  attribute \src "ls180.v:3222.107-3222.155"
+  wire $eq$ls180.v:3222$779_Y
+  attribute \src "ls180.v:3223.110-3223.158"
+  wire $eq$ls180.v:3223$783_Y
+  attribute \src "ls180.v:3228.36-3228.85"
+  wire $eq$ls180.v:3228$785_Y
+  attribute \src "ls180.v:3230.105-3230.151"
+  wire $eq$ls180.v:3230$787_Y
+  attribute \src "ls180.v:3231.108-3231.154"
+  wire $eq$ls180.v:3231$791_Y
+  attribute \src "ls180.v:3233.104-3233.150"
+  wire $eq$ls180.v:3233$794_Y
+  attribute \src "ls180.v:3234.107-3234.153"
+  wire $eq$ls180.v:3234$798_Y
+  attribute \src "ls180.v:3242.36-3242.85"
+  wire $eq$ls180.v:3242$800_Y
+  attribute \src "ls180.v:3244.116-3244.164"
+  wire $eq$ls180.v:3244$802_Y
+  attribute \src "ls180.v:3245.119-3245.167"
+  wire $eq$ls180.v:3245$806_Y
+  attribute \src "ls180.v:3247.120-3247.168"
+  wire $eq$ls180.v:3247$809_Y
+  attribute \src "ls180.v:3248.123-3248.171"
+  wire $eq$ls180.v:3248$813_Y
+  attribute \src "ls180.v:3250.101-3250.149"
+  wire $eq$ls180.v:3250$816_Y
+  attribute \src "ls180.v:3251.104-3251.152"
+  wire $eq$ls180.v:3251$820_Y
+  attribute \src "ls180.v:3253.120-3253.168"
+  wire $eq$ls180.v:3253$823_Y
+  attribute \src "ls180.v:3254.123-3254.171"
+  wire $eq$ls180.v:3254$827_Y
+  attribute \src "ls180.v:3256.120-3256.168"
+  wire $eq$ls180.v:3256$830_Y
+  attribute \src "ls180.v:3257.123-3257.171"
+  wire $eq$ls180.v:3257$834_Y
+  attribute \src "ls180.v:3259.121-3259.169"
+  wire $eq$ls180.v:3259$837_Y
+  attribute \src "ls180.v:3260.124-3260.172"
+  wire $eq$ls180.v:3260$841_Y
+  attribute \src "ls180.v:3262.119-3262.167"
+  wire $eq$ls180.v:3262$844_Y
+  attribute \src "ls180.v:3263.122-3263.170"
+  wire $eq$ls180.v:3263$848_Y
+  attribute \src "ls180.v:3265.119-3265.167"
+  wire $eq$ls180.v:3265$851_Y
+  attribute \src "ls180.v:3266.122-3266.170"
+  wire $eq$ls180.v:3266$855_Y
+  attribute \src "ls180.v:3268.119-3268.167"
+  wire $eq$ls180.v:3268$858_Y
+  attribute \src "ls180.v:3269.122-3269.170"
+  wire $eq$ls180.v:3269$862_Y
+  attribute \src "ls180.v:3271.119-3271.167"
+  wire $eq$ls180.v:3271$865_Y
+  attribute \src "ls180.v:3272.122-3272.170"
+  wire $eq$ls180.v:3272$869_Y
+  attribute \src "ls180.v:3287.36-3287.85"
+  wire $eq$ls180.v:3287$871_Y
+  attribute \src "ls180.v:3289.108-3289.156"
+  wire $eq$ls180.v:3289$873_Y
+  attribute \src "ls180.v:3290.111-3290.159"
+  wire $eq$ls180.v:3290$877_Y
+  attribute \src "ls180.v:3292.108-3292.156"
+  wire $eq$ls180.v:3292$880_Y
+  attribute \src "ls180.v:3293.111-3293.159"
+  wire $eq$ls180.v:3293$884_Y
+  attribute \src "ls180.v:3295.108-3295.156"
+  wire $eq$ls180.v:3295$887_Y
+  attribute \src "ls180.v:3296.111-3296.159"
+  wire $eq$ls180.v:3296$891_Y
+  attribute \src "ls180.v:3298.108-3298.156"
+  wire $eq$ls180.v:3298$894_Y
+  attribute \src "ls180.v:3299.111-3299.159"
+  wire $eq$ls180.v:3299$898_Y
+  attribute \src "ls180.v:3301.110-3301.158"
+  wire $eq$ls180.v:3301$901_Y
+  attribute \src "ls180.v:3302.113-3302.161"
+  wire $eq$ls180.v:3302$905_Y
+  attribute \src "ls180.v:3304.110-3304.158"
+  wire $eq$ls180.v:3304$908_Y
+  attribute \src "ls180.v:3305.113-3305.161"
+  wire $eq$ls180.v:3305$912_Y
+  attribute \src "ls180.v:3307.110-3307.158"
+  wire $eq$ls180.v:3307$915_Y
+  attribute \src "ls180.v:3308.113-3308.161"
+  wire $eq$ls180.v:3308$919_Y
+  attribute \src "ls180.v:3310.110-3310.158"
+  wire $eq$ls180.v:3310$922_Y
+  attribute \src "ls180.v:3311.113-3311.161"
+  wire $eq$ls180.v:3311$926_Y
+  attribute \src "ls180.v:3313.106-3313.154"
+  wire $eq$ls180.v:3313$929_Y
+  attribute \src "ls180.v:3314.109-3314.157"
+  wire $eq$ls180.v:3314$933_Y
+  attribute \src "ls180.v:3316.116-3316.164"
+  wire $eq$ls180.v:3316$936_Y
+  attribute \src "ls180.v:3317.119-3317.167"
+  wire $eq$ls180.v:3317$940_Y
+  attribute \src "ls180.v:3319.109-3319.158"
+  wire $eq$ls180.v:3319$943_Y
+  attribute \src "ls180.v:3320.112-3320.161"
+  wire $eq$ls180.v:3320$947_Y
+  attribute \src "ls180.v:3322.109-3322.158"
+  wire $eq$ls180.v:3322$950_Y
+  attribute \src "ls180.v:3323.112-3323.161"
+  wire $eq$ls180.v:3323$954_Y
+  attribute \src "ls180.v:3325.109-3325.158"
+  wire $eq$ls180.v:3325$957_Y
+  attribute \src "ls180.v:3326.112-3326.161"
+  wire $eq$ls180.v:3326$961_Y
+  attribute \src "ls180.v:3328.109-3328.158"
+  wire $eq$ls180.v:3328$964_Y
+  attribute \src "ls180.v:3329.112-3329.161"
+  wire $eq$ls180.v:3329$968_Y
+  attribute \src "ls180.v:3331.113-3331.162"
+  wire $eq$ls180.v:3331$971_Y
+  attribute \src "ls180.v:3332.116-3332.165"
+  wire $eq$ls180.v:3332$975_Y
+  attribute \src "ls180.v:3334.114-3334.163"
+  wire $eq$ls180.v:3334$978_Y
+  attribute \src "ls180.v:3335.117-3335.166"
+  wire $eq$ls180.v:3335$982_Y
+  attribute \src "ls180.v:3337.113-3337.162"
+  wire $eq$ls180.v:3337$985_Y
+  attribute \src "ls180.v:3338.116-3338.165"
+  wire $eq$ls180.v:3338$989_Y
+  attribute \src "ls180.v:3355.36-3355.85"
+  wire $eq$ls180.v:3355$991_Y
+  attribute \src "ls180.v:3357.86-3357.134"
+  wire $eq$ls180.v:3357$993_Y
+  attribute \src "ls180.v:3358.89-3358.137"
+  wire $eq$ls180.v:3358$997_Y
+  attribute \src "ls180.v:3360.109-3360.157"
+  wire $eq$ls180.v:3360$1000_Y
+  attribute \src "ls180.v:3361.112-3361.160"
+  wire $eq$ls180.v:3361$1004_Y
+  attribute \src "ls180.v:3363.110-3363.158"
+  wire $eq$ls180.v:3363$1007_Y
+  attribute \src "ls180.v:3364.113-3364.161"
+  wire $eq$ls180.v:3364$1011_Y
+  attribute \src "ls180.v:3366.101-3366.149"
+  wire $eq$ls180.v:3366$1014_Y
+  attribute \src "ls180.v:3367.104-3367.152"
+  wire $eq$ls180.v:3367$1018_Y
+  attribute \src "ls180.v:3369.102-3369.150"
+  wire $eq$ls180.v:3369$1021_Y
+  attribute \src "ls180.v:3370.105-3370.153"
+  wire $eq$ls180.v:3370$1025_Y
+  attribute \src "ls180.v:3372.113-3372.161"
+  wire $eq$ls180.v:3372$1028_Y
+  attribute \src "ls180.v:3373.116-3373.164"
+  wire $eq$ls180.v:3373$1032_Y
+  attribute \src "ls180.v:3375.110-3375.158"
+  wire $eq$ls180.v:3375$1035_Y
+  attribute \src "ls180.v:3376.113-3376.161"
+  wire $eq$ls180.v:3376$1039_Y
+  attribute \src "ls180.v:3378.109-3378.157"
+  wire $eq$ls180.v:3378$1042_Y
+  attribute \src "ls180.v:3379.112-3379.160"
+  wire $eq$ls180.v:3379$1046_Y
+  attribute \src "ls180.v:3389.36-3389.85"
+  wire $eq$ls180.v:3389$1048_Y
+  attribute \src "ls180.v:3391.115-3391.163"
+  wire $eq$ls180.v:3391$1050_Y
+  attribute \src "ls180.v:3392.118-3392.166"
+  wire $eq$ls180.v:3392$1054_Y
+  attribute \src "ls180.v:3394.115-3394.163"
+  wire $eq$ls180.v:3394$1057_Y
+  attribute \src "ls180.v:3395.118-3395.166"
+  wire $eq$ls180.v:3395$1061_Y
+  attribute \src "ls180.v:3397.115-3397.163"
+  wire $eq$ls180.v:3397$1064_Y
+  attribute \src "ls180.v:3398.118-3398.166"
+  wire $eq$ls180.v:3398$1068_Y
+  attribute \src "ls180.v:3400.115-3400.163"
+  wire $eq$ls180.v:3400$1071_Y
+  attribute \src "ls180.v:3401.118-3401.166"
+  wire $eq$ls180.v:3401$1075_Y
+  attribute \src "ls180.v:3761.28-3761.63"
+  wire $eq$ls180.v:3761$1105_Y
+  attribute \src "ls180.v:3761.126-3761.164"
+  wire $eq$ls180.v:3761$1106_Y
+  attribute \src "ls180.v:3761.201-3761.239"
+  wire $eq$ls180.v:3761$1109_Y
+  attribute \src "ls180.v:3761.276-3761.314"
+  wire $eq$ls180.v:3761$1112_Y
+  attribute \src "ls180.v:3785.28-3785.63"
+  wire $eq$ls180.v:3785$1121_Y
+  attribute \src "ls180.v:3785.126-3785.164"
+  wire $eq$ls180.v:3785$1122_Y
+  attribute \src "ls180.v:3785.201-3785.239"
+  wire $eq$ls180.v:3785$1125_Y
+  attribute \src "ls180.v:3785.276-3785.314"
+  wire $eq$ls180.v:3785$1128_Y
+  attribute \src "ls180.v:3809.28-3809.63"
+  wire $eq$ls180.v:3809$1137_Y
+  attribute \src "ls180.v:3809.126-3809.164"
+  wire $eq$ls180.v:3809$1138_Y
+  attribute \src "ls180.v:3809.201-3809.239"
+  wire $eq$ls180.v:3809$1141_Y
+  attribute \src "ls180.v:3809.276-3809.314"
+  wire $eq$ls180.v:3809$1144_Y
+  attribute \src "ls180.v:3833.28-3833.63"
+  wire $eq$ls180.v:3833$1153_Y
+  attribute \src "ls180.v:3833.126-3833.164"
+  wire $eq$ls180.v:3833$1154_Y
+  attribute \src "ls180.v:3833.201-3833.239"
+  wire $eq$ls180.v:3833$1157_Y
+  attribute \src "ls180.v:3833.276-3833.314"
+  wire $eq$ls180.v:3833$1160_Y
+  attribute \src "ls180.v:4365.8-4365.33"
+  wire $eq$ls180.v:4365$1260_Y
+  attribute \src "ls180.v:4400.8-4400.37"
+  wire $eq$ls180.v:4400$1271_Y
+  attribute \src "ls180.v:4420.33-4420.64"
+  wire $eq$ls180.v:4420$1274_Y
+  attribute \src "ls180.v:4427.7-4427.38"
+  wire $eq$ls180.v:4427$1276_Y
+  attribute \src "ls180.v:4434.7-4434.38"
+  wire $eq$ls180.v:4434$1277_Y
   attribute \src "ls180.v:4442.7-4442.38"
-  wire $eq$ls180.v:4442$1308_Y
-  attribute \src "ls180.v:4449.7-4449.38"
-  wire $eq$ls180.v:4449$1309_Y
-  attribute \src "ls180.v:4457.7-4457.38"
-  wire $eq$ls180.v:4457$1310_Y
-  attribute \src "ls180.v:4509.9-4509.49"
-  wire $eq$ls180.v:4509$1328_Y
-  attribute \src "ls180.v:4555.9-4555.49"
-  wire $eq$ls180.v:4555$1344_Y
-  attribute \src "ls180.v:4601.9-4601.49"
-  wire $eq$ls180.v:4601$1360_Y
-  attribute \src "ls180.v:4647.9-4647.49"
-  wire $eq$ls180.v:4647$1376_Y
+  wire $eq$ls180.v:4442$1278_Y
+  attribute \src "ls180.v:4494.9-4494.49"
+  wire $eq$ls180.v:4494$1296_Y
+  attribute \src "ls180.v:4540.9-4540.49"
+  wire $eq$ls180.v:4540$1312_Y
+  attribute \src "ls180.v:4586.9-4586.49"
+  wire $eq$ls180.v:4586$1328_Y
+  attribute \src "ls180.v:4632.9-4632.49"
+  wire $eq$ls180.v:4632$1344_Y
+  attribute \src "ls180.v:4782.9-4782.36"
+  wire $eq$ls180.v:4782$1356_Y
   attribute \src "ls180.v:4797.9-4797.36"
-  wire $eq$ls180.v:4797$1388_Y
-  attribute \src "ls180.v:4812.9-4812.36"
-  wire $eq$ls180.v:4812$1391_Y
-  attribute \src "ls180.v:4818.54-4818.92"
-  wire $eq$ls180.v:4818$1392_Y
-  attribute \src "ls180.v:4818.136-4818.174"
-  wire $eq$ls180.v:4818$1395_Y
-  attribute \src "ls180.v:4818.218-4818.256"
-  wire $eq$ls180.v:4818$1398_Y
-  attribute \src "ls180.v:4818.300-4818.338"
-  wire $eq$ls180.v:4818$1401_Y
-  attribute \src "ls180.v:4819.55-4819.93"
-  wire $eq$ls180.v:4819$1404_Y
-  attribute \src "ls180.v:4819.137-4819.175"
-  wire $eq$ls180.v:4819$1407_Y
-  attribute \src "ls180.v:4819.219-4819.257"
-  wire $eq$ls180.v:4819$1410_Y
-  attribute \src "ls180.v:4819.301-4819.339"
-  wire $eq$ls180.v:4819$1413_Y
-  attribute \src "ls180.v:4854.9-4854.37"
-  wire $eq$ls180.v:4854$1425_Y
-  attribute \src "ls180.v:4857.10-4857.38"
-  wire $eq$ls180.v:4857$1426_Y
-  attribute \src "ls180.v:4883.9-4883.37"
-  wire $eq$ls180.v:4883$1432_Y
-  attribute \src "ls180.v:4888.10-4888.38"
-  wire $eq$ls180.v:4888$1433_Y
-  attribute \src "ls180.v:5530.28-5530.31"
-  wire width 64 $memrd$\mem$ls180.v:5530$1515_DATA
-  attribute \src "ls180.v:5558.20-5558.25"
-  wire width 64 $memrd$\mem_1$ls180.v:5558$1565_DATA
-  attribute \src "ls180.v:5569.12-5569.19"
-  wire width 25 $memrd$\storage$ls180.v:5569$1573_DATA
-  attribute \src "ls180.v:5576.63-5576.70"
-  wire width 25 $memrd$\storage$ls180.v:5576$1575_DATA
-  attribute \src "ls180.v:5583.14-5583.23"
-  wire width 25 $memrd$\storage_1$ls180.v:5583$1583_DATA
-  attribute \src "ls180.v:5590.63-5590.72"
-  wire width 25 $memrd$\storage_1$ls180.v:5590$1585_DATA
-  attribute \src "ls180.v:5597.14-5597.23"
-  wire width 25 $memrd$\storage_2$ls180.v:5597$1593_DATA
-  attribute \src "ls180.v:5604.63-5604.72"
-  wire width 25 $memrd$\storage_2$ls180.v:5604$1595_DATA
-  attribute \src "ls180.v:5611.14-5611.23"
-  wire width 25 $memrd$\storage_3$ls180.v:5611$1603_DATA
-  attribute \src "ls180.v:5618.63-5618.72"
-  wire width 25 $memrd$\storage_3$ls180.v:5618$1605_DATA
-  attribute \src "ls180.v:5626.14-5626.23"
-  wire width 10 $memrd$\storage_4$ls180.v:5626$1613_DATA
-  attribute \src "ls180.v:5631.15-5631.24"
-  wire width 10 $memrd$\storage_4$ls180.v:5631$1615_DATA
-  attribute \src "ls180.v:5643.14-5643.23"
-  wire width 10 $memrd$\storage_5$ls180.v:5643$1623_DATA
-  attribute \src "ls180.v:5648.15-5648.24"
-  wire width 10 $memrd$\storage_5$ls180.v:5648$1625_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5512$1_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5512$1_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5512$1_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5514$2_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5514$2_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5514$2_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5516$3_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5516$3_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5516$3_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5518$4_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5518$4_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5518$4_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5520$5_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5520$5_DATA
+  wire $eq$ls180.v:4797$1359_Y
+  attribute \src "ls180.v:4803.54-4803.92"
+  wire $eq$ls180.v:4803$1360_Y
+  attribute \src "ls180.v:4803.136-4803.174"
+  wire $eq$ls180.v:4803$1363_Y
+  attribute \src "ls180.v:4803.218-4803.256"
+  wire $eq$ls180.v:4803$1366_Y
+  attribute \src "ls180.v:4803.300-4803.338"
+  wire $eq$ls180.v:4803$1369_Y
+  attribute \src "ls180.v:4804.55-4804.93"
+  wire $eq$ls180.v:4804$1372_Y
+  attribute \src "ls180.v:4804.137-4804.175"
+  wire $eq$ls180.v:4804$1375_Y
+  attribute \src "ls180.v:4804.219-4804.257"
+  wire $eq$ls180.v:4804$1378_Y
+  attribute \src "ls180.v:4804.301-4804.339"
+  wire $eq$ls180.v:4804$1381_Y
+  attribute \src "ls180.v:4839.9-4839.37"
+  wire $eq$ls180.v:4839$1393_Y
+  attribute \src "ls180.v:4842.10-4842.38"
+  wire $eq$ls180.v:4842$1394_Y
+  attribute \src "ls180.v:4868.9-4868.37"
+  wire $eq$ls180.v:4868$1400_Y
+  attribute \src "ls180.v:4873.10-4873.38"
+  wire $eq$ls180.v:4873$1401_Y
+  attribute \src "ls180.v:5507.28-5507.31"
+  wire width 32 $memrd$\mem$ls180.v:5507$1459_DATA
+  attribute \src "ls180.v:5527.20-5527.25"
+  wire width 32 $memrd$\mem_1$ls180.v:5527$1485_DATA
+  attribute \src "ls180.v:5538.12-5538.19"
+  wire width 25 $memrd$\storage$ls180.v:5538$1493_DATA
+  attribute \src "ls180.v:5545.63-5545.70"
+  wire width 25 $memrd$\storage$ls180.v:5545$1495_DATA
+  attribute \src "ls180.v:5552.14-5552.23"
+  wire width 25 $memrd$\storage_1$ls180.v:5552$1503_DATA
+  attribute \src "ls180.v:5559.63-5559.72"
+  wire width 25 $memrd$\storage_1$ls180.v:5559$1505_DATA
+  attribute \src "ls180.v:5566.14-5566.23"
+  wire width 25 $memrd$\storage_2$ls180.v:5566$1513_DATA
+  attribute \src "ls180.v:5573.63-5573.72"
+  wire width 25 $memrd$\storage_2$ls180.v:5573$1515_DATA
+  attribute \src "ls180.v:5580.14-5580.23"
+  wire width 25 $memrd$\storage_3$ls180.v:5580$1523_DATA
+  attribute \src "ls180.v:5587.63-5587.72"
+  wire width 25 $memrd$\storage_3$ls180.v:5587$1525_DATA
+  attribute \src "ls180.v:5595.14-5595.23"
+  wire width 10 $memrd$\storage_4$ls180.v:5595$1533_DATA
+  attribute \src "ls180.v:5600.15-5600.24"
+  wire width 10 $memrd$\storage_4$ls180.v:5600$1535_DATA
+  attribute \src "ls180.v:5612.14-5612.23"
+  wire width 10 $memrd$\storage_5$ls180.v:5612$1543_DATA
+  attribute \src "ls180.v:5617.15-5617.24"
+  wire width 10 $memrd$\storage_5$ls180.v:5617$1545_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5520$5_EN
+  wire width 7 $memwr$\mem$ls180.v:5497$1_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5522$6_ADDR
+  wire width 32 $memwr$\mem$ls180.v:5497$1_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5522$6_DATA
+  wire width 32 $memwr$\mem$ls180.v:5497$1_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5522$6_EN
+  wire width 7 $memwr$\mem$ls180.v:5499$2_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5524$7_ADDR
+  wire width 32 $memwr$\mem$ls180.v:5499$2_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5524$7_DATA
+  wire width 32 $memwr$\mem$ls180.v:5499$2_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5524$7_EN
+  wire width 7 $memwr$\mem$ls180.v:5501$3_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 6 $memwr$\mem$ls180.v:5526$8_ADDR
+  wire width 32 $memwr$\mem$ls180.v:5501$3_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5526$8_DATA
+  wire width 32 $memwr$\mem$ls180.v:5501$3_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem$ls180.v:5526$8_EN
+  wire width 7 $memwr$\mem$ls180.v:5503$4_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5540$9_ADDR
+  wire width 32 $memwr$\mem$ls180.v:5503$4_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5540$9_DATA
+  wire width 32 $memwr$\mem$ls180.v:5503$4_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5540$9_EN
+  wire width 5 $memwr$\mem_1$ls180.v:5517$5_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5542$10_ADDR
+  wire width 32 $memwr$\mem_1$ls180.v:5517$5_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5542$10_DATA
+  wire width 32 $memwr$\mem_1$ls180.v:5517$5_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5542$10_EN
+  wire width 5 $memwr$\mem_1$ls180.v:5519$6_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5544$11_ADDR
+  wire width 32 $memwr$\mem_1$ls180.v:5519$6_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5544$11_DATA
+  wire width 32 $memwr$\mem_1$ls180.v:5519$6_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5544$11_EN
+  wire width 5 $memwr$\mem_1$ls180.v:5521$7_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5546$12_ADDR
+  wire width 32 $memwr$\mem_1$ls180.v:5521$7_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5546$12_DATA
+  wire width 32 $memwr$\mem_1$ls180.v:5521$7_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5546$12_EN
+  wire width 5 $memwr$\mem_1$ls180.v:5523$8_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5548$13_ADDR
+  wire width 32 $memwr$\mem_1$ls180.v:5523$8_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5548$13_DATA
+  wire width 32 $memwr$\mem_1$ls180.v:5523$8_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5548$13_EN
+  wire width 3 $memwr$\storage$ls180.v:5537$9_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5550$14_ADDR
+  wire width 25 $memwr$\storage$ls180.v:5537$9_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5550$14_DATA
+  wire width 25 $memwr$\storage$ls180.v:5537$9_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5550$14_EN
+  wire width 3 $memwr$\storage_1$ls180.v:5551$10_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5552$15_ADDR
+  wire width 25 $memwr$\storage_1$ls180.v:5551$10_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5552$15_DATA
+  wire width 25 $memwr$\storage_1$ls180.v:5551$10_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5552$15_EN
+  wire width 3 $memwr$\storage_2$ls180.v:5565$11_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\mem_1$ls180.v:5554$16_ADDR
+  wire width 25 $memwr$\storage_2$ls180.v:5565$11_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5554$16_DATA
+  wire width 25 $memwr$\storage_2$ls180.v:5565$11_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 64 $memwr$\mem_1$ls180.v:5554$16_EN
+  wire width 3 $memwr$\storage_3$ls180.v:5579$12_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage$ls180.v:5568$17_ADDR
+  wire width 25 $memwr$\storage_3$ls180.v:5579$12_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:5568$17_DATA
+  wire width 25 $memwr$\storage_3$ls180.v:5579$12_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage$ls180.v:5568$17_EN
+  wire width 4 $memwr$\storage_4$ls180.v:5594$13_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_1$ls180.v:5582$18_ADDR
+  wire width 10 $memwr$\storage_4$ls180.v:5594$13_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:5582$18_DATA
+  wire width 10 $memwr$\storage_4$ls180.v:5594$13_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_1$ls180.v:5582$18_EN
+  wire width 4 $memwr$\storage_5$ls180.v:5611$14_ADDR
   attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_2$ls180.v:5596$19_ADDR
+  wire width 10 $memwr$\storage_5$ls180.v:5611$14_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:5596$19_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_2$ls180.v:5596$19_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 3 $memwr$\storage_3$ls180.v:5610$20_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:5610$20_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 25 $memwr$\storage_3$ls180.v:5610$20_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_4$ls180.v:5625$21_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:5625$21_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_4$ls180.v:5625$21_EN
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 4 $memwr$\storage_5$ls180.v:5642$22_ADDR
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:5642$22_DATA
-  attribute \src "ls180.v:0.0-0.0"
-  wire width 10 $memwr$\storage_5$ls180.v:5642$22_EN
-  attribute \src "ls180.v:1722.36-1722.61"
-  wire $ne$ls180.v:1722$83_Y
-  attribute \src "ls180.v:1897.60-1897.89"
-  wire $ne$ls180.v:1897$122_Y
-  attribute \src "ls180.v:1958.8-1958.132"
-  wire $ne$ls180.v:1958$141_Y
-  attribute \src "ls180.v:1990.70-1990.123"
-  wire $ne$ls180.v:1990$148_Y
-  attribute \src "ls180.v:1991.70-1991.123"
-  wire $ne$ls180.v:1991$149_Y
-  attribute \src "ls180.v:2115.8-2115.132"
-  wire $ne$ls180.v:2115$171_Y
-  attribute \src "ls180.v:2147.70-2147.123"
-  wire $ne$ls180.v:2147$178_Y
-  attribute \src "ls180.v:2148.70-2148.123"
-  wire $ne$ls180.v:2148$179_Y
-  attribute \src "ls180.v:2272.8-2272.132"
-  wire $ne$ls180.v:2272$201_Y
-  attribute \src "ls180.v:2304.70-2304.123"
-  wire $ne$ls180.v:2304$208_Y
-  attribute \src "ls180.v:2305.70-2305.123"
-  wire $ne$ls180.v:2305$209_Y
-  attribute \src "ls180.v:2429.8-2429.132"
-  wire $ne$ls180.v:2429$231_Y
-  attribute \src "ls180.v:2461.70-2461.123"
-  wire $ne$ls180.v:2461$238_Y
-  attribute \src "ls180.v:2462.70-2462.123"
-  wire $ne$ls180.v:2462$239_Y
-  attribute \src "ls180.v:2954.37-2954.60"
-  wire $ne$ls180.v:2954$637_Y
-  attribute \src "ls180.v:2955.37-2955.59"
-  wire $ne$ls180.v:2955$638_Y
-  attribute \src "ls180.v:2984.37-2984.60"
-  wire $ne$ls180.v:2984$648_Y
-  attribute \src "ls180.v:2985.37-2985.59"
-  wire $ne$ls180.v:2985$649_Y
-  attribute \src "ls180.v:3080.99-3080.143"
-  wire $ne$ls180.v:3080$656_Y
-  attribute \src "ls180.v:4370.7-4370.47"
-  wire $ne$ls180.v:4370$1287_Y
-  attribute \src "ls180.v:4424.9-4424.38"
-  wire $ne$ls180.v:4424$1304_Y
-  attribute \src "ls180.v:4460.8-4460.39"
-  wire $ne$ls180.v:4460$1311_Y
-  attribute \src "ls180.v:1526.28-1526.63"
-  wire $not$ls180.v:1526$25_Y
-  attribute \src "ls180.v:1565.43-1565.59"
-  wire $not$ls180.v:1565$30_Y
-  attribute \src "ls180.v:1566.43-1566.59"
-  wire $not$ls180.v:1566$31_Y
-  attribute \src "ls180.v:1586.28-1586.63"
-  wire $not$ls180.v:1586$36_Y
-  attribute \src "ls180.v:1625.43-1625.59"
-  wire $not$ls180.v:1625$41_Y
-  attribute \src "ls180.v:1626.43-1626.59"
-  wire $not$ls180.v:1626$42_Y
-  attribute \src "ls180.v:1646.31-1646.69"
-  wire $not$ls180.v:1646$47_Y
-  attribute \src "ls180.v:1685.22-1685.41"
-  wire $not$ls180.v:1685$52_Y
-  attribute \src "ls180.v:1686.22-1686.41"
-  wire $not$ls180.v:1686$53_Y
-  attribute \src "ls180.v:1846.29-1846.54"
-  wire $not$ls180.v:1846$114_Y
-  attribute \src "ls180.v:1847.26-1847.51"
-  wire $not$ls180.v:1847$115_Y
-  attribute \src "ls180.v:1848.27-1848.52"
-  wire $not$ls180.v:1848$116_Y
-  attribute \src "ls180.v:1849.27-1849.52"
-  wire $not$ls180.v:1849$117_Y
-  attribute \src "ls180.v:1891.28-1891.46"
-  wire $not$ls180.v:1891$120_Y
-  attribute \src "ls180.v:1992.53-1992.96"
-  wire $not$ls180.v:1992$150_Y
-  attribute \src "ls180.v:2046.9-2046.40"
-  wire $not$ls180.v:2046$155_Y
-  attribute \src "ls180.v:2149.53-2149.96"
-  wire $not$ls180.v:2149$180_Y
-  attribute \src "ls180.v:2203.9-2203.40"
-  wire $not$ls180.v:2203$185_Y
-  attribute \src "ls180.v:2306.53-2306.96"
-  wire $not$ls180.v:2306$210_Y
-  attribute \src "ls180.v:2360.9-2360.40"
-  wire $not$ls180.v:2360$215_Y
-  attribute \src "ls180.v:2463.53-2463.96"
-  wire $not$ls180.v:2463$240_Y
-  attribute \src "ls180.v:2517.9-2517.40"
-  wire $not$ls180.v:2517$245_Y
-  attribute \src "ls180.v:2559.129-2559.162"
-  wire $not$ls180.v:2559$248_Y
-  attribute \src "ls180.v:2559.168-2559.200"
-  wire $not$ls180.v:2559$250_Y
-  attribute \src "ls180.v:2560.129-2560.162"
-  wire $not$ls180.v:2560$254_Y
-  attribute \src "ls180.v:2560.168-2560.200"
-  wire $not$ls180.v:2560$256_Y
-  attribute \src "ls180.v:2576.38-2576.63"
-  wire width 2 $not$ls180.v:2576$284_Y
-  attribute \src "ls180.v:2579.180-2579.215"
-  wire $not$ls180.v:2579$287_Y
-  attribute \src "ls180.v:2579.221-2579.255"
-  wire $not$ls180.v:2579$289_Y
-  attribute \src "ls180.v:2579.139-2579.257"
-  wire $not$ls180.v:2579$291_Y
-  attribute \src "ls180.v:2580.180-2580.215"
-  wire $not$ls180.v:2580$300_Y
-  attribute \src "ls180.v:2580.221-2580.255"
-  wire $not$ls180.v:2580$302_Y
-  attribute \src "ls180.v:2580.139-2580.257"
-  wire $not$ls180.v:2580$304_Y
-  attribute \src "ls180.v:2581.180-2581.215"
-  wire $not$ls180.v:2581$313_Y
-  attribute \src "ls180.v:2581.221-2581.255"
-  wire $not$ls180.v:2581$315_Y
-  attribute \src "ls180.v:2581.139-2581.257"
-  wire $not$ls180.v:2581$317_Y
-  attribute \src "ls180.v:2582.180-2582.215"
-  wire $not$ls180.v:2582$326_Y
-  attribute \src "ls180.v:2582.221-2582.255"
-  wire $not$ls180.v:2582$328_Y
-  attribute \src "ls180.v:2582.139-2582.257"
-  wire $not$ls180.v:2582$330_Y
-  attribute \src "ls180.v:2609.61-2609.88"
-  wire $not$ls180.v:2609$341_Y
-  attribute \src "ls180.v:2612.180-2612.215"
-  wire $not$ls180.v:2612$345_Y
-  attribute \src "ls180.v:2612.221-2612.255"
-  wire $not$ls180.v:2612$347_Y
-  attribute \src "ls180.v:2612.139-2612.257"
-  wire $not$ls180.v:2612$349_Y
-  attribute \src "ls180.v:2613.180-2613.215"
-  wire $not$ls180.v:2613$358_Y
-  attribute \src "ls180.v:2613.221-2613.255"
-  wire $not$ls180.v:2613$360_Y
-  attribute \src "ls180.v:2613.139-2613.257"
-  wire $not$ls180.v:2613$362_Y
-  attribute \src "ls180.v:2614.180-2614.215"
-  wire $not$ls180.v:2614$371_Y
-  attribute \src "ls180.v:2614.221-2614.255"
-  wire $not$ls180.v:2614$373_Y
-  attribute \src "ls180.v:2614.139-2614.257"
-  wire $not$ls180.v:2614$375_Y
-  attribute \src "ls180.v:2615.180-2615.215"
-  wire $not$ls180.v:2615$384_Y
-  attribute \src "ls180.v:2615.221-2615.255"
-  wire $not$ls180.v:2615$386_Y
-  attribute \src "ls180.v:2615.139-2615.257"
-  wire $not$ls180.v:2615$388_Y
-  attribute \src "ls180.v:2678.61-2678.88"
-  wire $not$ls180.v:2678$427_Y
-  attribute \src "ls180.v:2699.97-2699.130"
-  wire $not$ls180.v:2699$430_Y
-  attribute \src "ls180.v:2699.136-2699.168"
-  wire $not$ls180.v:2699$432_Y
-  attribute \src "ls180.v:2699.58-2699.170"
-  wire $not$ls180.v:2699$434_Y
-  attribute \src "ls180.v:2707.11-2707.33"
-  wire $not$ls180.v:2707$437_Y
-  attribute \src "ls180.v:2737.97-2737.130"
-  wire $not$ls180.v:2737$439_Y
-  attribute \src "ls180.v:2737.136-2737.168"
-  wire $not$ls180.v:2737$441_Y
-  attribute \src "ls180.v:2737.58-2737.170"
-  wire $not$ls180.v:2737$443_Y
-  attribute \src "ls180.v:2745.11-2745.32"
-  wire $not$ls180.v:2745$446_Y
+  wire width 10 $memwr$\storage_5$ls180.v:5611$14_EN
+  attribute \src "ls180.v:1711.36-1711.61"
+  wire $ne$ls180.v:1711$63_Y
+  attribute \src "ls180.v:1882.60-1882.89"
+  wire $ne$ls180.v:1882$90_Y
+  attribute \src "ls180.v:1943.8-1943.132"
+  wire $ne$ls180.v:1943$109_Y
+  attribute \src "ls180.v:1975.70-1975.123"
+  wire $ne$ls180.v:1975$116_Y
+  attribute \src "ls180.v:1976.70-1976.123"
+  wire $ne$ls180.v:1976$117_Y
+  attribute \src "ls180.v:2100.8-2100.132"
+  wire $ne$ls180.v:2100$139_Y
+  attribute \src "ls180.v:2132.70-2132.123"
+  wire $ne$ls180.v:2132$146_Y
+  attribute \src "ls180.v:2133.70-2133.123"
+  wire $ne$ls180.v:2133$147_Y
+  attribute \src "ls180.v:2257.8-2257.132"
+  wire $ne$ls180.v:2257$169_Y
+  attribute \src "ls180.v:2289.70-2289.123"
+  wire $ne$ls180.v:2289$176_Y
+  attribute \src "ls180.v:2290.70-2290.123"
+  wire $ne$ls180.v:2290$177_Y
+  attribute \src "ls180.v:2414.8-2414.132"
+  wire $ne$ls180.v:2414$199_Y
+  attribute \src "ls180.v:2446.70-2446.123"
+  wire $ne$ls180.v:2446$206_Y
+  attribute \src "ls180.v:2447.70-2447.123"
+  wire $ne$ls180.v:2447$207_Y
+  attribute \src "ls180.v:2939.37-2939.60"
+  wire $ne$ls180.v:2939$605_Y
+  attribute \src "ls180.v:2940.37-2940.59"
+  wire $ne$ls180.v:2940$606_Y
+  attribute \src "ls180.v:2969.37-2969.60"
+  wire $ne$ls180.v:2969$616_Y
+  attribute \src "ls180.v:2970.37-2970.59"
+  wire $ne$ls180.v:2970$617_Y
+  attribute \src "ls180.v:3065.99-3065.143"
+  wire $ne$ls180.v:3065$624_Y
+  attribute \src "ls180.v:4355.7-4355.47"
+  wire $ne$ls180.v:4355$1255_Y
+  attribute \src "ls180.v:4409.9-4409.38"
+  wire $ne$ls180.v:4409$1272_Y
+  attribute \src "ls180.v:4445.8-4445.39"
+  wire $ne$ls180.v:4445$1279_Y
+  attribute \src "ls180.v:1519.40-1519.70"
+  wire $not$ls180.v:1519$17_Y
+  attribute \src "ls180.v:1558.56-1558.84"
+  wire $not$ls180.v:1558$22_Y
+  attribute \src "ls180.v:1559.56-1559.84"
+  wire $not$ls180.v:1559$23_Y
+  attribute \src "ls180.v:1579.40-1579.70"
+  wire $not$ls180.v:1579$28_Y
+  attribute \src "ls180.v:1618.56-1618.84"
+  wire $not$ls180.v:1618$33_Y
+  attribute \src "ls180.v:1619.56-1619.84"
+  wire $not$ls180.v:1619$34_Y
+  attribute \src "ls180.v:1639.40-1639.73"
+  wire $not$ls180.v:1639$39_Y
+  attribute \src "ls180.v:1678.56-1678.84"
+  wire $not$ls180.v:1678$44_Y
+  attribute \src "ls180.v:1679.56-1679.84"
+  wire $not$ls180.v:1679$45_Y
+  attribute \src "ls180.v:1831.29-1831.54"
+  wire $not$ls180.v:1831$82_Y
+  attribute \src "ls180.v:1832.26-1832.51"
+  wire $not$ls180.v:1832$83_Y
+  attribute \src "ls180.v:1833.27-1833.52"
+  wire $not$ls180.v:1833$84_Y
+  attribute \src "ls180.v:1834.27-1834.52"
+  wire $not$ls180.v:1834$85_Y
+  attribute \src "ls180.v:1876.28-1876.46"
+  wire $not$ls180.v:1876$88_Y
+  attribute \src "ls180.v:1977.53-1977.96"
+  wire $not$ls180.v:1977$118_Y
+  attribute \src "ls180.v:2031.9-2031.40"
+  wire $not$ls180.v:2031$123_Y
+  attribute \src "ls180.v:2134.53-2134.96"
+  wire $not$ls180.v:2134$148_Y
+  attribute \src "ls180.v:2188.9-2188.40"
+  wire $not$ls180.v:2188$153_Y
+  attribute \src "ls180.v:2291.53-2291.96"
+  wire $not$ls180.v:2291$178_Y
+  attribute \src "ls180.v:2345.9-2345.40"
+  wire $not$ls180.v:2345$183_Y
+  attribute \src "ls180.v:2448.53-2448.96"
+  wire $not$ls180.v:2448$208_Y
+  attribute \src "ls180.v:2502.9-2502.40"
+  wire $not$ls180.v:2502$213_Y
+  attribute \src "ls180.v:2544.129-2544.162"
+  wire $not$ls180.v:2544$216_Y
+  attribute \src "ls180.v:2544.168-2544.200"
+  wire $not$ls180.v:2544$218_Y
+  attribute \src "ls180.v:2545.129-2545.162"
+  wire $not$ls180.v:2545$222_Y
+  attribute \src "ls180.v:2545.168-2545.200"
+  wire $not$ls180.v:2545$224_Y
+  attribute \src "ls180.v:2561.38-2561.63"
+  wire width 2 $not$ls180.v:2561$252_Y
+  attribute \src "ls180.v:2564.180-2564.215"
+  wire $not$ls180.v:2564$255_Y
+  attribute \src "ls180.v:2564.221-2564.255"
+  wire $not$ls180.v:2564$257_Y
+  attribute \src "ls180.v:2564.139-2564.257"
+  wire $not$ls180.v:2564$259_Y
+  attribute \src "ls180.v:2565.180-2565.215"
+  wire $not$ls180.v:2565$268_Y
+  attribute \src "ls180.v:2565.221-2565.255"
+  wire $not$ls180.v:2565$270_Y
+  attribute \src "ls180.v:2565.139-2565.257"
+  wire $not$ls180.v:2565$272_Y
+  attribute \src "ls180.v:2566.180-2566.215"
+  wire $not$ls180.v:2566$281_Y
+  attribute \src "ls180.v:2566.221-2566.255"
+  wire $not$ls180.v:2566$283_Y
+  attribute \src "ls180.v:2566.139-2566.257"
+  wire $not$ls180.v:2566$285_Y
+  attribute \src "ls180.v:2567.180-2567.215"
+  wire $not$ls180.v:2567$294_Y
+  attribute \src "ls180.v:2567.221-2567.255"
+  wire $not$ls180.v:2567$296_Y
+  attribute \src "ls180.v:2567.139-2567.257"
+  wire $not$ls180.v:2567$298_Y
+  attribute \src "ls180.v:2594.61-2594.88"
+  wire $not$ls180.v:2594$309_Y
+  attribute \src "ls180.v:2597.180-2597.215"
+  wire $not$ls180.v:2597$313_Y
+  attribute \src "ls180.v:2597.221-2597.255"
+  wire $not$ls180.v:2597$315_Y
+  attribute \src "ls180.v:2597.139-2597.257"
+  wire $not$ls180.v:2597$317_Y
+  attribute \src "ls180.v:2598.180-2598.215"
+  wire $not$ls180.v:2598$326_Y
+  attribute \src "ls180.v:2598.221-2598.255"
+  wire $not$ls180.v:2598$328_Y
+  attribute \src "ls180.v:2598.139-2598.257"
+  wire $not$ls180.v:2598$330_Y
+  attribute \src "ls180.v:2599.180-2599.215"
+  wire $not$ls180.v:2599$339_Y
+  attribute \src "ls180.v:2599.221-2599.255"
+  wire $not$ls180.v:2599$341_Y
+  attribute \src "ls180.v:2599.139-2599.257"
+  wire $not$ls180.v:2599$343_Y
+  attribute \src "ls180.v:2600.180-2600.215"
+  wire $not$ls180.v:2600$352_Y
+  attribute \src "ls180.v:2600.221-2600.255"
+  wire $not$ls180.v:2600$354_Y
+  attribute \src "ls180.v:2600.139-2600.257"
+  wire $not$ls180.v:2600$356_Y
+  attribute \src "ls180.v:2663.61-2663.88"
+  wire $not$ls180.v:2663$395_Y
+  attribute \src "ls180.v:2684.97-2684.130"
+  wire $not$ls180.v:2684$398_Y
+  attribute \src "ls180.v:2684.136-2684.168"
+  wire $not$ls180.v:2684$400_Y
+  attribute \src "ls180.v:2684.58-2684.170"
+  wire $not$ls180.v:2684$402_Y
+  attribute \src "ls180.v:2692.11-2692.33"
+  wire $not$ls180.v:2692$405_Y
+  attribute \src "ls180.v:2722.97-2722.130"
+  wire $not$ls180.v:2722$407_Y
+  attribute \src "ls180.v:2722.136-2722.168"
+  wire $not$ls180.v:2722$409_Y
+  attribute \src "ls180.v:2722.58-2722.170"
+  wire $not$ls180.v:2722$411_Y
+  attribute \src "ls180.v:2730.11-2730.32"
+  wire $not$ls180.v:2730$414_Y
+  attribute \src "ls180.v:2740.87-2740.336"
+  wire $not$ls180.v:2740$426_Y
+  attribute \src "ls180.v:2741.40-2741.68"
+  wire $not$ls180.v:2741$429_Y
+  attribute \src "ls180.v:2741.73-2741.100"
+  wire $not$ls180.v:2741$430_Y
+  attribute \src "ls180.v:2745.87-2745.336"
+  wire $not$ls180.v:2745$442_Y
+  attribute \src "ls180.v:2746.40-2746.68"
+  wire $not$ls180.v:2746$445_Y
+  attribute \src "ls180.v:2746.73-2746.100"
+  wire $not$ls180.v:2746$446_Y
+  attribute \src "ls180.v:2750.87-2750.336"
+  wire $not$ls180.v:2750$458_Y
+  attribute \src "ls180.v:2751.40-2751.68"
+  wire $not$ls180.v:2751$461_Y
+  attribute \src "ls180.v:2751.73-2751.100"
+  wire $not$ls180.v:2751$462_Y
   attribute \src "ls180.v:2755.87-2755.336"
-  wire $not$ls180.v:2755$458_Y
+  wire $not$ls180.v:2755$474_Y
   attribute \src "ls180.v:2756.40-2756.68"
-  wire $not$ls180.v:2756$461_Y
+  wire $not$ls180.v:2756$477_Y
   attribute \src "ls180.v:2756.73-2756.100"
-  wire $not$ls180.v:2756$462_Y
-  attribute \src "ls180.v:2760.87-2760.336"
-  wire $not$ls180.v:2760$474_Y
-  attribute \src "ls180.v:2761.40-2761.68"
-  wire $not$ls180.v:2761$477_Y
-  attribute \src "ls180.v:2761.73-2761.100"
-  wire $not$ls180.v:2761$478_Y
-  attribute \src "ls180.v:2765.87-2765.336"
-  wire $not$ls180.v:2765$490_Y
-  attribute \src "ls180.v:2766.40-2766.68"
-  wire $not$ls180.v:2766$493_Y
-  attribute \src "ls180.v:2766.73-2766.100"
-  wire $not$ls180.v:2766$494_Y
-  attribute \src "ls180.v:2770.87-2770.336"
-  wire $not$ls180.v:2770$506_Y
-  attribute \src "ls180.v:2771.40-2771.68"
-  wire $not$ls180.v:2771$509_Y
-  attribute \src "ls180.v:2771.73-2771.100"
-  wire $not$ls180.v:2771$510_Y
-  attribute \src "ls180.v:2775.123-2775.372"
-  wire $not$ls180.v:2775$523_Y
-  attribute \src "ls180.v:2775.497-2775.746"
-  wire $not$ls180.v:2775$539_Y
-  attribute \src "ls180.v:2775.871-2775.1120"
-  wire $not$ls180.v:2775$555_Y
-  attribute \src "ls180.v:2775.1245-2775.1494"
-  wire $not$ls180.v:2775$571_Y
-  attribute \src "ls180.v:2797.27-2797.40"
-  wire $not$ls180.v:2797$577_Y
-  attribute \src "ls180.v:2836.25-2836.40"
-  wire $not$ls180.v:2836$582_Y
-  attribute \src "ls180.v:2837.25-2837.40"
-  wire $not$ls180.v:2837$583_Y
-  attribute \src "ls180.v:2862.22-2862.38"
-  wire $not$ls180.v:2862$589_Y
-  attribute \src "ls180.v:2863.25-2863.40"
-  wire $not$ls180.v:2863$590_Y
-  attribute \src "ls180.v:2864.65-2864.78"
-  wire $not$ls180.v:2864$592_Y
-  attribute \src "ls180.v:2865.87-2865.102"
-  wire $not$ls180.v:2865$596_Y
-  attribute \src "ls180.v:2866.63-2866.83"
-  wire $not$ls180.v:2866$599_Y
-  attribute \src "ls180.v:2867.71-2867.86"
-  wire $not$ls180.v:2867$602_Y
-  attribute \src "ls180.v:2883.25-2883.44"
-  wire $not$ls180.v:2883$611_Y
-  attribute \src "ls180.v:2884.26-2884.47"
-  wire $not$ls180.v:2884$612_Y
-  attribute \src "ls180.v:2890.22-2890.41"
-  wire $not$ls180.v:2890$613_Y
-  attribute \src "ls180.v:2896.26-2896.47"
-  wire $not$ls180.v:2896$614_Y
-  attribute \src "ls180.v:2897.25-2897.44"
-  wire $not$ls180.v:2897$615_Y
-  attribute \src "ls180.v:2900.22-2900.43"
-  wire $not$ls180.v:2900$618_Y
-  attribute \src "ls180.v:2938.61-2938.78"
-  wire $not$ls180.v:2938$628_Y
-  attribute \src "ls180.v:2968.61-2968.78"
-  wire $not$ls180.v:2968$639_Y
-  attribute \src "ls180.v:3163.81-3163.104"
-  wire $not$ls180.v:3163$689_Y
-  attribute \src "ls180.v:3180.71-3180.106"
-  wire $not$ls180.v:3180$713_Y
-  attribute \src "ls180.v:3183.73-3183.108"
-  wire $not$ls180.v:3183$720_Y
-  attribute \src "ls180.v:3186.73-3186.108"
-  wire $not$ls180.v:3186$727_Y
-  attribute \src "ls180.v:3189.73-3189.108"
-  wire $not$ls180.v:3189$734_Y
-  attribute \src "ls180.v:3192.73-3192.108"
-  wire $not$ls180.v:3192$741_Y
-  attribute \src "ls180.v:3195.76-3195.111"
-  wire $not$ls180.v:3195$748_Y
-  attribute \src "ls180.v:3198.76-3198.111"
-  wire $not$ls180.v:3198$755_Y
-  attribute \src "ls180.v:3201.76-3201.111"
-  wire $not$ls180.v:3201$762_Y
-  attribute \src "ls180.v:3204.76-3204.111"
-  wire $not$ls180.v:3204$769_Y
-  attribute \src "ls180.v:3218.68-3218.103"
-  wire $not$ls180.v:3218$777_Y
-  attribute \src "ls180.v:3221.67-3221.102"
-  wire $not$ls180.v:3221$784_Y
-  attribute \src "ls180.v:3224.69-3224.104"
-  wire $not$ls180.v:3224$791_Y
-  attribute \src "ls180.v:3232.68-3232.103"
-  wire $not$ls180.v:3232$799_Y
-  attribute \src "ls180.v:3235.67-3235.102"
-  wire $not$ls180.v:3235$806_Y
-  attribute \src "ls180.v:3238.69-3238.104"
-  wire $not$ls180.v:3238$813_Y
-  attribute \src "ls180.v:3246.67-3246.102"
-  wire $not$ls180.v:3246$821_Y
-  attribute \src "ls180.v:3249.66-3249.101"
-  wire $not$ls180.v:3249$828_Y
-  attribute \src "ls180.v:3260.78-3260.113"
-  wire $not$ls180.v:3260$836_Y
-  attribute \src "ls180.v:3263.82-3263.117"
-  wire $not$ls180.v:3263$843_Y
-  attribute \src "ls180.v:3266.63-3266.98"
-  wire $not$ls180.v:3266$850_Y
-  attribute \src "ls180.v:3269.82-3269.117"
-  wire $not$ls180.v:3269$857_Y
-  attribute \src "ls180.v:3272.82-3272.117"
-  wire $not$ls180.v:3272$864_Y
-  attribute \src "ls180.v:3275.83-3275.118"
-  wire $not$ls180.v:3275$871_Y
-  attribute \src "ls180.v:3278.81-3278.116"
-  wire $not$ls180.v:3278$878_Y
-  attribute \src "ls180.v:3281.81-3281.116"
-  wire $not$ls180.v:3281$885_Y
-  attribute \src "ls180.v:3284.81-3284.116"
-  wire $not$ls180.v:3284$892_Y
-  attribute \src "ls180.v:3287.81-3287.116"
-  wire $not$ls180.v:3287$899_Y
-  attribute \src "ls180.v:3305.70-3305.105"
-  wire $not$ls180.v:3305$907_Y
-  attribute \src "ls180.v:3308.70-3308.105"
-  wire $not$ls180.v:3308$914_Y
-  attribute \src "ls180.v:3311.70-3311.105"
-  wire $not$ls180.v:3311$921_Y
-  attribute \src "ls180.v:3314.70-3314.105"
-  wire $not$ls180.v:3314$928_Y
-  attribute \src "ls180.v:3317.72-3317.107"
-  wire $not$ls180.v:3317$935_Y
-  attribute \src "ls180.v:3320.72-3320.107"
-  wire $not$ls180.v:3320$942_Y
-  attribute \src "ls180.v:3323.72-3323.107"
-  wire $not$ls180.v:3323$949_Y
-  attribute \src "ls180.v:3326.72-3326.107"
-  wire $not$ls180.v:3326$956_Y
-  attribute \src "ls180.v:3329.68-3329.103"
-  wire $not$ls180.v:3329$963_Y
-  attribute \src "ls180.v:3332.78-3332.113"
-  wire $not$ls180.v:3332$970_Y
-  attribute \src "ls180.v:3335.71-3335.106"
-  wire $not$ls180.v:3335$977_Y
-  attribute \src "ls180.v:3338.71-3338.106"
-  wire $not$ls180.v:3338$984_Y
-  attribute \src "ls180.v:3341.71-3341.106"
-  wire $not$ls180.v:3341$991_Y
-  attribute \src "ls180.v:3344.71-3344.106"
-  wire $not$ls180.v:3344$998_Y
-  attribute \src "ls180.v:3347.75-3347.110"
-  wire $not$ls180.v:3347$1005_Y
-  attribute \src "ls180.v:3350.76-3350.111"
-  wire $not$ls180.v:3350$1012_Y
-  attribute \src "ls180.v:3353.75-3353.110"
-  wire $not$ls180.v:3353$1019_Y
-  attribute \src "ls180.v:3373.48-3373.83"
-  wire $not$ls180.v:3373$1027_Y
-  attribute \src "ls180.v:3376.71-3376.106"
-  wire $not$ls180.v:3376$1034_Y
-  attribute \src "ls180.v:3379.72-3379.107"
-  wire $not$ls180.v:3379$1041_Y
-  attribute \src "ls180.v:3382.63-3382.98"
-  wire $not$ls180.v:3382$1048_Y
-  attribute \src "ls180.v:3385.64-3385.99"
-  wire $not$ls180.v:3385$1055_Y
-  attribute \src "ls180.v:3388.75-3388.110"
-  wire $not$ls180.v:3388$1062_Y
-  attribute \src "ls180.v:3391.72-3391.107"
-  wire $not$ls180.v:3391$1069_Y
-  attribute \src "ls180.v:3394.71-3394.106"
-  wire $not$ls180.v:3394$1076_Y
-  attribute \src "ls180.v:3407.77-3407.112"
-  wire $not$ls180.v:3407$1084_Y
-  attribute \src "ls180.v:3410.77-3410.112"
-  wire $not$ls180.v:3410$1091_Y
-  attribute \src "ls180.v:3413.77-3413.112"
-  wire $not$ls180.v:3413$1098_Y
-  attribute \src "ls180.v:3416.77-3416.112"
-  wire $not$ls180.v:3416$1105_Y
-  attribute \src "ls180.v:3776.68-3776.317"
-  wire $not$ls180.v:3776$1147_Y
-  attribute \src "ls180.v:3800.68-3800.317"
-  wire $not$ls180.v:3800$1163_Y
-  attribute \src "ls180.v:3824.68-3824.317"
-  wire $not$ls180.v:3824$1179_Y
-  attribute \src "ls180.v:3848.68-3848.317"
-  wire $not$ls180.v:3848$1195_Y
-  attribute \src "ls180.v:4376.62-4376.86"
-  wire $not$ls180.v:4376$1290_Y
-  attribute \src "ls180.v:4395.8-4395.33"
-  wire $not$ls180.v:4395$1294_Y
-  attribute \src "ls180.v:4399.54-4399.74"
-  wire $not$ls180.v:4399$1297_Y
-  attribute \src "ls180.v:4407.27-4407.45"
-  wire $not$ls180.v:4407$1299_Y
-  attribute \src "ls180.v:4477.126-4477.174"
-  wire $not$ls180.v:4477$1314_Y
-  attribute \src "ls180.v:4483.126-4483.174"
-  wire $not$ls180.v:4483$1319_Y
-  attribute \src "ls180.v:4484.8-4484.56"
-  wire $not$ls180.v:4484$1321_Y
-  attribute \src "ls180.v:4492.8-4492.51"
-  wire $not$ls180.v:4492$1324_Y
-  attribute \src "ls180.v:4507.8-4507.41"
-  wire $not$ls180.v:4507$1326_Y
-  attribute \src "ls180.v:4523.126-4523.174"
-  wire $not$ls180.v:4523$1330_Y
-  attribute \src "ls180.v:4529.126-4529.174"
-  wire $not$ls180.v:4529$1335_Y
-  attribute \src "ls180.v:4530.8-4530.56"
-  wire $not$ls180.v:4530$1337_Y
-  attribute \src "ls180.v:4538.8-4538.51"
-  wire $not$ls180.v:4538$1340_Y
-  attribute \src "ls180.v:4553.8-4553.41"
-  wire $not$ls180.v:4553$1342_Y
-  attribute \src "ls180.v:4569.126-4569.174"
-  wire $not$ls180.v:4569$1346_Y
-  attribute \src "ls180.v:4575.126-4575.174"
-  wire $not$ls180.v:4575$1351_Y
-  attribute \src "ls180.v:4576.8-4576.56"
-  wire $not$ls180.v:4576$1353_Y
-  attribute \src "ls180.v:4584.8-4584.51"
-  wire $not$ls180.v:4584$1356_Y
-  attribute \src "ls180.v:4599.8-4599.41"
-  wire $not$ls180.v:4599$1358_Y
-  attribute \src "ls180.v:4615.126-4615.174"
-  wire $not$ls180.v:4615$1362_Y
-  attribute \src "ls180.v:4621.126-4621.174"
-  wire $not$ls180.v:4621$1367_Y
-  attribute \src "ls180.v:4622.8-4622.56"
-  wire $not$ls180.v:4622$1369_Y
-  attribute \src "ls180.v:4630.8-4630.51"
-  wire $not$ls180.v:4630$1372_Y
-  attribute \src "ls180.v:4645.8-4645.41"
-  wire $not$ls180.v:4645$1374_Y
-  attribute \src "ls180.v:4653.7-4653.17"
-  wire $not$ls180.v:4653$1377_Y
-  attribute \src "ls180.v:4656.8-4656.24"
-  wire $not$ls180.v:4656$1378_Y
-  attribute \src "ls180.v:4660.7-4660.17"
-  wire $not$ls180.v:4660$1380_Y
-  attribute \src "ls180.v:4663.8-4663.24"
-  wire $not$ls180.v:4663$1381_Y
-  attribute \src "ls180.v:4782.25-4782.38"
-  wire $not$ls180.v:4782$1383_Y
-  attribute \src "ls180.v:4783.25-4783.38"
-  wire $not$ls180.v:4783$1384_Y
-  attribute \src "ls180.v:4784.24-4784.37"
-  wire $not$ls180.v:4784$1385_Y
+  wire $not$ls180.v:2756$478_Y
+  attribute \src "ls180.v:2760.123-2760.372"
+  wire $not$ls180.v:2760$491_Y
+  attribute \src "ls180.v:2760.497-2760.746"
+  wire $not$ls180.v:2760$507_Y
+  attribute \src "ls180.v:2760.871-2760.1120"
+  wire $not$ls180.v:2760$523_Y
+  attribute \src "ls180.v:2760.1245-2760.1494"
+  wire $not$ls180.v:2760$539_Y
+  attribute \src "ls180.v:2782.27-2782.40"
+  wire $not$ls180.v:2782$545_Y
+  attribute \src "ls180.v:2821.25-2821.40"
+  wire $not$ls180.v:2821$550_Y
+  attribute \src "ls180.v:2822.25-2822.40"
+  wire $not$ls180.v:2822$551_Y
+  attribute \src "ls180.v:2847.22-2847.38"
+  wire $not$ls180.v:2847$557_Y
+  attribute \src "ls180.v:2848.25-2848.40"
+  wire $not$ls180.v:2848$558_Y
+  attribute \src "ls180.v:2849.65-2849.78"
+  wire $not$ls180.v:2849$560_Y
+  attribute \src "ls180.v:2850.87-2850.102"
+  wire $not$ls180.v:2850$564_Y
+  attribute \src "ls180.v:2851.63-2851.83"
+  wire $not$ls180.v:2851$567_Y
+  attribute \src "ls180.v:2852.71-2852.86"
+  wire $not$ls180.v:2852$570_Y
+  attribute \src "ls180.v:2868.25-2868.44"
+  wire $not$ls180.v:2868$579_Y
+  attribute \src "ls180.v:2869.26-2869.47"
+  wire $not$ls180.v:2869$580_Y
+  attribute \src "ls180.v:2875.22-2875.41"
+  wire $not$ls180.v:2875$581_Y
+  attribute \src "ls180.v:2881.26-2881.47"
+  wire $not$ls180.v:2881$582_Y
+  attribute \src "ls180.v:2882.25-2882.44"
+  wire $not$ls180.v:2882$583_Y
+  attribute \src "ls180.v:2885.22-2885.43"
+  wire $not$ls180.v:2885$586_Y
+  attribute \src "ls180.v:2923.61-2923.78"
+  wire $not$ls180.v:2923$596_Y
+  attribute \src "ls180.v:2953.61-2953.78"
+  wire $not$ls180.v:2953$607_Y
+  attribute \src "ls180.v:3148.81-3148.104"
+  wire $not$ls180.v:3148$657_Y
+  attribute \src "ls180.v:3165.71-3165.106"
+  wire $not$ls180.v:3165$681_Y
+  attribute \src "ls180.v:3168.73-3168.108"
+  wire $not$ls180.v:3168$688_Y
+  attribute \src "ls180.v:3171.73-3171.108"
+  wire $not$ls180.v:3171$695_Y
+  attribute \src "ls180.v:3174.73-3174.108"
+  wire $not$ls180.v:3174$702_Y
+  attribute \src "ls180.v:3177.73-3177.108"
+  wire $not$ls180.v:3177$709_Y
+  attribute \src "ls180.v:3180.76-3180.111"
+  wire $not$ls180.v:3180$716_Y
+  attribute \src "ls180.v:3183.76-3183.111"
+  wire $not$ls180.v:3183$723_Y
+  attribute \src "ls180.v:3186.76-3186.111"
+  wire $not$ls180.v:3186$730_Y
+  attribute \src "ls180.v:3189.76-3189.111"
+  wire $not$ls180.v:3189$737_Y
+  attribute \src "ls180.v:3203.68-3203.103"
+  wire $not$ls180.v:3203$745_Y
+  attribute \src "ls180.v:3206.67-3206.102"
+  wire $not$ls180.v:3206$752_Y
+  attribute \src "ls180.v:3209.69-3209.104"
+  wire $not$ls180.v:3209$759_Y
+  attribute \src "ls180.v:3217.68-3217.103"
+  wire $not$ls180.v:3217$767_Y
+  attribute \src "ls180.v:3220.67-3220.102"
+  wire $not$ls180.v:3220$774_Y
+  attribute \src "ls180.v:3223.69-3223.104"
+  wire $not$ls180.v:3223$781_Y
+  attribute \src "ls180.v:3231.67-3231.102"
+  wire $not$ls180.v:3231$789_Y
+  attribute \src "ls180.v:3234.66-3234.101"
+  wire $not$ls180.v:3234$796_Y
+  attribute \src "ls180.v:3245.78-3245.113"
+  wire $not$ls180.v:3245$804_Y
+  attribute \src "ls180.v:3248.82-3248.117"
+  wire $not$ls180.v:3248$811_Y
+  attribute \src "ls180.v:3251.63-3251.98"
+  wire $not$ls180.v:3251$818_Y
+  attribute \src "ls180.v:3254.82-3254.117"
+  wire $not$ls180.v:3254$825_Y
+  attribute \src "ls180.v:3257.82-3257.117"
+  wire $not$ls180.v:3257$832_Y
+  attribute \src "ls180.v:3260.83-3260.118"
+  wire $not$ls180.v:3260$839_Y
+  attribute \src "ls180.v:3263.81-3263.116"
+  wire $not$ls180.v:3263$846_Y
+  attribute \src "ls180.v:3266.81-3266.116"
+  wire $not$ls180.v:3266$853_Y
+  attribute \src "ls180.v:3269.81-3269.116"
+  wire $not$ls180.v:3269$860_Y
+  attribute \src "ls180.v:3272.81-3272.116"
+  wire $not$ls180.v:3272$867_Y
+  attribute \src "ls180.v:3290.70-3290.105"
+  wire $not$ls180.v:3290$875_Y
+  attribute \src "ls180.v:3293.70-3293.105"
+  wire $not$ls180.v:3293$882_Y
+  attribute \src "ls180.v:3296.70-3296.105"
+  wire $not$ls180.v:3296$889_Y
+  attribute \src "ls180.v:3299.70-3299.105"
+  wire $not$ls180.v:3299$896_Y
+  attribute \src "ls180.v:3302.72-3302.107"
+  wire $not$ls180.v:3302$903_Y
+  attribute \src "ls180.v:3305.72-3305.107"
+  wire $not$ls180.v:3305$910_Y
+  attribute \src "ls180.v:3308.72-3308.107"
+  wire $not$ls180.v:3308$917_Y
+  attribute \src "ls180.v:3311.72-3311.107"
+  wire $not$ls180.v:3311$924_Y
+  attribute \src "ls180.v:3314.68-3314.103"
+  wire $not$ls180.v:3314$931_Y
+  attribute \src "ls180.v:3317.78-3317.113"
+  wire $not$ls180.v:3317$938_Y
+  attribute \src "ls180.v:3320.71-3320.106"
+  wire $not$ls180.v:3320$945_Y
+  attribute \src "ls180.v:3323.71-3323.106"
+  wire $not$ls180.v:3323$952_Y
+  attribute \src "ls180.v:3326.71-3326.106"
+  wire $not$ls180.v:3326$959_Y
+  attribute \src "ls180.v:3329.71-3329.106"
+  wire $not$ls180.v:3329$966_Y
+  attribute \src "ls180.v:3332.75-3332.110"
+  wire $not$ls180.v:3332$973_Y
+  attribute \src "ls180.v:3335.76-3335.111"
+  wire $not$ls180.v:3335$980_Y
+  attribute \src "ls180.v:3338.75-3338.110"
+  wire $not$ls180.v:3338$987_Y
+  attribute \src "ls180.v:3358.48-3358.83"
+  wire $not$ls180.v:3358$995_Y
+  attribute \src "ls180.v:3361.71-3361.106"
+  wire $not$ls180.v:3361$1002_Y
+  attribute \src "ls180.v:3364.72-3364.107"
+  wire $not$ls180.v:3364$1009_Y
+  attribute \src "ls180.v:3367.63-3367.98"
+  wire $not$ls180.v:3367$1016_Y
+  attribute \src "ls180.v:3370.64-3370.99"
+  wire $not$ls180.v:3370$1023_Y
+  attribute \src "ls180.v:3373.75-3373.110"
+  wire $not$ls180.v:3373$1030_Y
+  attribute \src "ls180.v:3376.72-3376.107"
+  wire $not$ls180.v:3376$1037_Y
+  attribute \src "ls180.v:3379.71-3379.106"
+  wire $not$ls180.v:3379$1044_Y
+  attribute \src "ls180.v:3392.77-3392.112"
+  wire $not$ls180.v:3392$1052_Y
+  attribute \src "ls180.v:3395.77-3395.112"
+  wire $not$ls180.v:3395$1059_Y
+  attribute \src "ls180.v:3398.77-3398.112"
+  wire $not$ls180.v:3398$1066_Y
+  attribute \src "ls180.v:3401.77-3401.112"
+  wire $not$ls180.v:3401$1073_Y
+  attribute \src "ls180.v:3761.68-3761.317"
+  wire $not$ls180.v:3761$1115_Y
+  attribute \src "ls180.v:3785.68-3785.317"
+  wire $not$ls180.v:3785$1131_Y
+  attribute \src "ls180.v:3809.68-3809.317"
+  wire $not$ls180.v:3809$1147_Y
+  attribute \src "ls180.v:3833.68-3833.317"
+  wire $not$ls180.v:3833$1163_Y
+  attribute \src "ls180.v:4361.62-4361.86"
+  wire $not$ls180.v:4361$1258_Y
+  attribute \src "ls180.v:4380.8-4380.33"
+  wire $not$ls180.v:4380$1262_Y
+  attribute \src "ls180.v:4384.54-4384.74"
+  wire $not$ls180.v:4384$1265_Y
+  attribute \src "ls180.v:4392.27-4392.45"
+  wire $not$ls180.v:4392$1267_Y
+  attribute \src "ls180.v:4462.126-4462.174"
+  wire $not$ls180.v:4462$1282_Y
+  attribute \src "ls180.v:4468.126-4468.174"
+  wire $not$ls180.v:4468$1287_Y
+  attribute \src "ls180.v:4469.8-4469.56"
+  wire $not$ls180.v:4469$1289_Y
+  attribute \src "ls180.v:4477.8-4477.51"
+  wire $not$ls180.v:4477$1292_Y
+  attribute \src "ls180.v:4492.8-4492.41"
+  wire $not$ls180.v:4492$1294_Y
+  attribute \src "ls180.v:4508.126-4508.174"
+  wire $not$ls180.v:4508$1298_Y
+  attribute \src "ls180.v:4514.126-4514.174"
+  wire $not$ls180.v:4514$1303_Y
+  attribute \src "ls180.v:4515.8-4515.56"
+  wire $not$ls180.v:4515$1305_Y
+  attribute \src "ls180.v:4523.8-4523.51"
+  wire $not$ls180.v:4523$1308_Y
+  attribute \src "ls180.v:4538.8-4538.41"
+  wire $not$ls180.v:4538$1310_Y
+  attribute \src "ls180.v:4554.126-4554.174"
+  wire $not$ls180.v:4554$1314_Y
+  attribute \src "ls180.v:4560.126-4560.174"
+  wire $not$ls180.v:4560$1319_Y
+  attribute \src "ls180.v:4561.8-4561.56"
+  wire $not$ls180.v:4561$1321_Y
+  attribute \src "ls180.v:4569.8-4569.51"
+  wire $not$ls180.v:4569$1324_Y
+  attribute \src "ls180.v:4584.8-4584.41"
+  wire $not$ls180.v:4584$1326_Y
+  attribute \src "ls180.v:4600.126-4600.174"
+  wire $not$ls180.v:4600$1330_Y
+  attribute \src "ls180.v:4606.126-4606.174"
+  wire $not$ls180.v:4606$1335_Y
+  attribute \src "ls180.v:4607.8-4607.56"
+  wire $not$ls180.v:4607$1337_Y
+  attribute \src "ls180.v:4615.8-4615.51"
+  wire $not$ls180.v:4615$1340_Y
+  attribute \src "ls180.v:4630.8-4630.41"
+  wire $not$ls180.v:4630$1342_Y
+  attribute \src "ls180.v:4638.7-4638.17"
+  wire $not$ls180.v:4638$1345_Y
+  attribute \src "ls180.v:4641.8-4641.24"
+  wire $not$ls180.v:4641$1346_Y
+  attribute \src "ls180.v:4645.7-4645.17"
+  wire $not$ls180.v:4645$1348_Y
+  attribute \src "ls180.v:4648.8-4648.24"
+  wire $not$ls180.v:4648$1349_Y
+  attribute \src "ls180.v:4767.25-4767.38"
+  wire $not$ls180.v:4767$1351_Y
+  attribute \src "ls180.v:4768.25-4768.38"
+  wire $not$ls180.v:4768$1352_Y
+  attribute \src "ls180.v:4769.24-4769.37"
+  wire $not$ls180.v:4769$1353_Y
+  attribute \src "ls180.v:4780.8-4780.28"
+  wire $not$ls180.v:4780$1354_Y
   attribute \src "ls180.v:4795.8-4795.28"
-  wire $not$ls180.v:4795$1386_Y
-  attribute \src "ls180.v:4810.8-4810.28"
-  wire $not$ls180.v:4810$1389_Y
-  attribute \src "ls180.v:4846.31-4846.48"
-  wire $not$ls180.v:4846$1419_Y
-  attribute \src "ls180.v:4846.54-4846.74"
-  wire $not$ls180.v:4846$1421_Y
-  attribute \src "ls180.v:4875.7-4875.24"
-  wire $not$ls180.v:4875$1428_Y
-  attribute \src "ls180.v:4876.9-4876.21"
-  wire $not$ls180.v:4876$1429_Y
-  attribute \src "ls180.v:4909.8-4909.19"
-  wire $not$ls180.v:4909$1435_Y
-  attribute \src "ls180.v:4916.8-4916.19"
-  wire $not$ls180.v:4916$1437_Y
-  attribute \src "ls180.v:4926.60-4926.76"
-  wire $not$ls180.v:4926$1440_Y
-  attribute \src "ls180.v:4932.60-4932.76"
-  wire $not$ls180.v:4932$1445_Y
-  attribute \src "ls180.v:4933.8-4933.24"
-  wire $not$ls180.v:4933$1447_Y
-  attribute \src "ls180.v:4948.60-4948.76"
-  wire $not$ls180.v:4948$1451_Y
-  attribute \src "ls180.v:4954.60-4954.76"
-  wire $not$ls180.v:4954$1456_Y
-  attribute \src "ls180.v:4955.8-4955.24"
-  wire $not$ls180.v:4955$1458_Y
-  attribute \src "ls180.v:4989.9-4989.32"
-  wire $not$ls180.v:4989$1461_Y
-  attribute \src "ls180.v:5000.9-5000.32"
-  wire $not$ls180.v:5000$1462_Y
-  attribute \src "ls180.v:5011.9-5011.32"
-  wire $not$ls180.v:5011$1463_Y
-  attribute \src "ls180.v:5024.8-5024.25"
-  wire $not$ls180.v:5024$1464_Y
-  attribute \src "ls180.v:1567.10-1567.61"
-  wire $or$ls180.v:1567$32_Y
-  attribute \src "ls180.v:1627.10-1627.61"
-  wire $or$ls180.v:1627$43_Y
-  attribute \src "ls180.v:1687.10-1687.43"
-  wire $or$ls180.v:1687$54_Y
-  attribute \src "ls180.v:1897.34-1897.90"
-  wire $or$ls180.v:1897$123_Y
-  attribute \src "ls180.v:1940.54-1940.125"
-  wire $or$ls180.v:1940$127_Y
-  attribute \src "ls180.v:1941.39-1941.136"
-  wire $or$ls180.v:1941$128_Y
-  attribute \src "ls180.v:1949.40-1949.155"
-  wire width 13 $or$ls180.v:1949$132_Y
-  attribute \src "ls180.v:1986.117-1986.225"
-  wire $or$ls180.v:1986$145_Y
-  attribute \src "ls180.v:1992.52-1992.142"
-  wire $or$ls180.v:1992$151_Y
-  attribute \src "ls180.v:2097.54-2097.125"
-  wire $or$ls180.v:2097$157_Y
-  attribute \src "ls180.v:2098.39-2098.136"
-  wire $or$ls180.v:2098$158_Y
-  attribute \src "ls180.v:2106.40-2106.155"
-  wire width 13 $or$ls180.v:2106$162_Y
-  attribute \src "ls180.v:2143.117-2143.225"
-  wire $or$ls180.v:2143$175_Y
-  attribute \src "ls180.v:2149.52-2149.142"
-  wire $or$ls180.v:2149$181_Y
-  attribute \src "ls180.v:2254.54-2254.125"
-  wire $or$ls180.v:2254$187_Y
-  attribute \src "ls180.v:2255.39-2255.136"
-  wire $or$ls180.v:2255$188_Y
-  attribute \src "ls180.v:2263.40-2263.155"
-  wire width 13 $or$ls180.v:2263$192_Y
-  attribute \src "ls180.v:2300.117-2300.225"
-  wire $or$ls180.v:2300$205_Y
-  attribute \src "ls180.v:2306.52-2306.142"
-  wire $or$ls180.v:2306$211_Y
-  attribute \src "ls180.v:2411.54-2411.125"
-  wire $or$ls180.v:2411$217_Y
-  attribute \src "ls180.v:2412.39-2412.136"
-  wire $or$ls180.v:2412$218_Y
-  attribute \src "ls180.v:2420.40-2420.155"
-  wire width 13 $or$ls180.v:2420$222_Y
-  attribute \src "ls180.v:2457.117-2457.225"
-  wire $or$ls180.v:2457$235_Y
-  attribute \src "ls180.v:2463.52-2463.142"
-  wire $or$ls180.v:2463$241_Y
-  attribute \src "ls180.v:2562.92-2562.168"
-  wire $or$ls180.v:2562$261_Y
-  attribute \src "ls180.v:2565.34-2565.179"
-  wire $or$ls180.v:2565$267_Y
-  attribute \src "ls180.v:2565.33-2565.254"
-  wire $or$ls180.v:2565$269_Y
-  attribute \src "ls180.v:2565.32-2565.329"
-  wire $or$ls180.v:2565$271_Y
-  attribute \src "ls180.v:2566.35-2566.182"
-  wire $or$ls180.v:2566$274_Y
-  attribute \src "ls180.v:2566.34-2566.258"
-  wire $or$ls180.v:2566$276_Y
-  attribute \src "ls180.v:2566.33-2566.334"
-  wire $or$ls180.v:2566$278_Y
-  attribute \src "ls180.v:2579.138-2579.292"
-  wire $or$ls180.v:2579$292_Y
-  attribute \src "ls180.v:2579.65-2579.446"
-  wire $or$ls180.v:2579$297_Y
-  attribute \src "ls180.v:2580.138-2580.292"
-  wire $or$ls180.v:2580$305_Y
-  attribute \src "ls180.v:2580.65-2580.446"
-  wire $or$ls180.v:2580$310_Y
-  attribute \src "ls180.v:2581.138-2581.292"
-  wire $or$ls180.v:2581$318_Y
-  attribute \src "ls180.v:2581.65-2581.446"
-  wire $or$ls180.v:2581$323_Y
-  attribute \src "ls180.v:2582.138-2582.292"
-  wire $or$ls180.v:2582$331_Y
-  attribute \src "ls180.v:2582.65-2582.446"
-  wire $or$ls180.v:2582$336_Y
-  attribute \src "ls180.v:2609.31-2609.89"
-  wire $or$ls180.v:2609$342_Y
-  attribute \src "ls180.v:2612.138-2612.292"
-  wire $or$ls180.v:2612$350_Y
-  attribute \src "ls180.v:2612.65-2612.446"
-  wire $or$ls180.v:2612$355_Y
-  attribute \src "ls180.v:2613.138-2613.292"
-  wire $or$ls180.v:2613$363_Y
-  attribute \src "ls180.v:2613.65-2613.446"
-  wire $or$ls180.v:2613$368_Y
-  attribute \src "ls180.v:2614.138-2614.292"
-  wire $or$ls180.v:2614$376_Y
-  attribute \src "ls180.v:2614.65-2614.446"
-  wire $or$ls180.v:2614$381_Y
-  attribute \src "ls180.v:2615.138-2615.292"
-  wire $or$ls180.v:2615$389_Y
-  attribute \src "ls180.v:2615.65-2615.446"
-  wire $or$ls180.v:2615$394_Y
-  attribute \src "ls180.v:2678.31-2678.89"
-  wire $or$ls180.v:2678$428_Y
-  attribute \src "ls180.v:2699.57-2699.191"
-  wire $or$ls180.v:2699$435_Y
-  attribute \src "ls180.v:2707.10-2707.52"
-  wire $or$ls180.v:2707$438_Y
-  attribute \src "ls180.v:2737.57-2737.191"
-  wire $or$ls180.v:2737$444_Y
-  attribute \src "ls180.v:2745.10-2745.51"
-  wire $or$ls180.v:2745$447_Y
+  wire $not$ls180.v:4795$1357_Y
+  attribute \src "ls180.v:4831.31-4831.48"
+  wire $not$ls180.v:4831$1387_Y
+  attribute \src "ls180.v:4831.54-4831.74"
+  wire $not$ls180.v:4831$1389_Y
+  attribute \src "ls180.v:4860.7-4860.24"
+  wire $not$ls180.v:4860$1396_Y
+  attribute \src "ls180.v:4861.9-4861.21"
+  wire $not$ls180.v:4861$1397_Y
+  attribute \src "ls180.v:4894.8-4894.19"
+  wire $not$ls180.v:4894$1403_Y
+  attribute \src "ls180.v:4901.8-4901.19"
+  wire $not$ls180.v:4901$1405_Y
+  attribute \src "ls180.v:4911.60-4911.76"
+  wire $not$ls180.v:4911$1408_Y
+  attribute \src "ls180.v:4917.60-4917.76"
+  wire $not$ls180.v:4917$1413_Y
+  attribute \src "ls180.v:4918.8-4918.24"
+  wire $not$ls180.v:4918$1415_Y
+  attribute \src "ls180.v:4933.60-4933.76"
+  wire $not$ls180.v:4933$1419_Y
+  attribute \src "ls180.v:4939.60-4939.76"
+  wire $not$ls180.v:4939$1424_Y
+  attribute \src "ls180.v:4940.8-4940.24"
+  wire $not$ls180.v:4940$1426_Y
+  attribute \src "ls180.v:4974.9-4974.32"
+  wire $not$ls180.v:4974$1429_Y
+  attribute \src "ls180.v:4985.9-4985.32"
+  wire $not$ls180.v:4985$1430_Y
+  attribute \src "ls180.v:4996.9-4996.32"
+  wire $not$ls180.v:4996$1431_Y
+  attribute \src "ls180.v:5009.8-5009.25"
+  wire $not$ls180.v:5009$1432_Y
+  attribute \src "ls180.v:1560.10-1560.86"
+  wire $or$ls180.v:1560$24_Y
+  attribute \src "ls180.v:1620.10-1620.86"
+  wire $or$ls180.v:1620$35_Y
+  attribute \src "ls180.v:1680.10-1680.86"
+  wire $or$ls180.v:1680$46_Y
+  attribute \src "ls180.v:1882.34-1882.90"
+  wire $or$ls180.v:1882$91_Y
+  attribute \src "ls180.v:1925.54-1925.125"
+  wire $or$ls180.v:1925$95_Y
+  attribute \src "ls180.v:1926.39-1926.136"
+  wire $or$ls180.v:1926$96_Y
+  attribute \src "ls180.v:1934.40-1934.155"
+  wire width 13 $or$ls180.v:1934$100_Y
+  attribute \src "ls180.v:1971.117-1971.225"
+  wire $or$ls180.v:1971$113_Y
+  attribute \src "ls180.v:1977.52-1977.142"
+  wire $or$ls180.v:1977$119_Y
+  attribute \src "ls180.v:2082.54-2082.125"
+  wire $or$ls180.v:2082$125_Y
+  attribute \src "ls180.v:2083.39-2083.136"
+  wire $or$ls180.v:2083$126_Y
+  attribute \src "ls180.v:2091.40-2091.155"
+  wire width 13 $or$ls180.v:2091$130_Y
+  attribute \src "ls180.v:2128.117-2128.225"
+  wire $or$ls180.v:2128$143_Y
+  attribute \src "ls180.v:2134.52-2134.142"
+  wire $or$ls180.v:2134$149_Y
+  attribute \src "ls180.v:2239.54-2239.125"
+  wire $or$ls180.v:2239$155_Y
+  attribute \src "ls180.v:2240.39-2240.136"
+  wire $or$ls180.v:2240$156_Y
+  attribute \src "ls180.v:2248.40-2248.155"
+  wire width 13 $or$ls180.v:2248$160_Y
+  attribute \src "ls180.v:2285.117-2285.225"
+  wire $or$ls180.v:2285$173_Y
+  attribute \src "ls180.v:2291.52-2291.142"
+  wire $or$ls180.v:2291$179_Y
+  attribute \src "ls180.v:2396.54-2396.125"
+  wire $or$ls180.v:2396$185_Y
+  attribute \src "ls180.v:2397.39-2397.136"
+  wire $or$ls180.v:2397$186_Y
+  attribute \src "ls180.v:2405.40-2405.155"
+  wire width 13 $or$ls180.v:2405$190_Y
+  attribute \src "ls180.v:2442.117-2442.225"
+  wire $or$ls180.v:2442$203_Y
+  attribute \src "ls180.v:2448.52-2448.142"
+  wire $or$ls180.v:2448$209_Y
+  attribute \src "ls180.v:2547.92-2547.168"
+  wire $or$ls180.v:2547$229_Y
+  attribute \src "ls180.v:2550.34-2550.179"
+  wire $or$ls180.v:2550$235_Y
+  attribute \src "ls180.v:2550.33-2550.254"
+  wire $or$ls180.v:2550$237_Y
+  attribute \src "ls180.v:2550.32-2550.329"
+  wire $or$ls180.v:2550$239_Y
+  attribute \src "ls180.v:2551.35-2551.182"
+  wire $or$ls180.v:2551$242_Y
+  attribute \src "ls180.v:2551.34-2551.258"
+  wire $or$ls180.v:2551$244_Y
+  attribute \src "ls180.v:2551.33-2551.334"
+  wire $or$ls180.v:2551$246_Y
+  attribute \src "ls180.v:2564.138-2564.292"
+  wire $or$ls180.v:2564$260_Y
+  attribute \src "ls180.v:2564.65-2564.446"
+  wire $or$ls180.v:2564$265_Y
+  attribute \src "ls180.v:2565.138-2565.292"
+  wire $or$ls180.v:2565$273_Y
+  attribute \src "ls180.v:2565.65-2565.446"
+  wire $or$ls180.v:2565$278_Y
+  attribute \src "ls180.v:2566.138-2566.292"
+  wire $or$ls180.v:2566$286_Y
+  attribute \src "ls180.v:2566.65-2566.446"
+  wire $or$ls180.v:2566$291_Y
+  attribute \src "ls180.v:2567.138-2567.292"
+  wire $or$ls180.v:2567$299_Y
+  attribute \src "ls180.v:2567.65-2567.446"
+  wire $or$ls180.v:2567$304_Y
+  attribute \src "ls180.v:2594.31-2594.89"
+  wire $or$ls180.v:2594$310_Y
+  attribute \src "ls180.v:2597.138-2597.292"
+  wire $or$ls180.v:2597$318_Y
+  attribute \src "ls180.v:2597.65-2597.446"
+  wire $or$ls180.v:2597$323_Y
+  attribute \src "ls180.v:2598.138-2598.292"
+  wire $or$ls180.v:2598$331_Y
+  attribute \src "ls180.v:2598.65-2598.446"
+  wire $or$ls180.v:2598$336_Y
+  attribute \src "ls180.v:2599.138-2599.292"
+  wire $or$ls180.v:2599$344_Y
+  attribute \src "ls180.v:2599.65-2599.446"
+  wire $or$ls180.v:2599$349_Y
+  attribute \src "ls180.v:2600.138-2600.292"
+  wire $or$ls180.v:2600$357_Y
+  attribute \src "ls180.v:2600.65-2600.446"
+  wire $or$ls180.v:2600$362_Y
+  attribute \src "ls180.v:2663.31-2663.89"
+  wire $or$ls180.v:2663$396_Y
+  attribute \src "ls180.v:2684.57-2684.191"
+  wire $or$ls180.v:2684$403_Y
+  attribute \src "ls180.v:2692.10-2692.52"
+  wire $or$ls180.v:2692$406_Y
+  attribute \src "ls180.v:2722.57-2722.191"
+  wire $or$ls180.v:2722$412_Y
+  attribute \src "ls180.v:2730.10-2730.51"
+  wire $or$ls180.v:2730$415_Y
+  attribute \src "ls180.v:2740.91-2740.185"
+  wire $or$ls180.v:2740$419_Y
+  attribute \src "ls180.v:2740.90-2740.260"
+  wire $or$ls180.v:2740$422_Y
+  attribute \src "ls180.v:2740.89-2740.335"
+  wire $or$ls180.v:2740$425_Y
+  attribute \src "ls180.v:2745.91-2745.185"
+  wire $or$ls180.v:2745$435_Y
+  attribute \src "ls180.v:2745.90-2745.260"
+  wire $or$ls180.v:2745$438_Y
+  attribute \src "ls180.v:2745.89-2745.335"
+  wire $or$ls180.v:2745$441_Y
+  attribute \src "ls180.v:2750.91-2750.185"
+  wire $or$ls180.v:2750$451_Y
+  attribute \src "ls180.v:2750.90-2750.260"
+  wire $or$ls180.v:2750$454_Y
+  attribute \src "ls180.v:2750.89-2750.335"
+  wire $or$ls180.v:2750$457_Y
   attribute \src "ls180.v:2755.91-2755.185"
-  wire $or$ls180.v:2755$451_Y
+  wire $or$ls180.v:2755$467_Y
   attribute \src "ls180.v:2755.90-2755.260"
-  wire $or$ls180.v:2755$454_Y
+  wire $or$ls180.v:2755$470_Y
   attribute \src "ls180.v:2755.89-2755.335"
-  wire $or$ls180.v:2755$457_Y
-  attribute \src "ls180.v:2760.91-2760.185"
-  wire $or$ls180.v:2760$467_Y
-  attribute \src "ls180.v:2760.90-2760.260"
-  wire $or$ls180.v:2760$470_Y
-  attribute \src "ls180.v:2760.89-2760.335"
-  wire $or$ls180.v:2760$473_Y
-  attribute \src "ls180.v:2765.91-2765.185"
-  wire $or$ls180.v:2765$483_Y
-  attribute \src "ls180.v:2765.90-2765.260"
-  wire $or$ls180.v:2765$486_Y
-  attribute \src "ls180.v:2765.89-2765.335"
-  wire $or$ls180.v:2765$489_Y
-  attribute \src "ls180.v:2770.91-2770.185"
-  wire $or$ls180.v:2770$499_Y
-  attribute \src "ls180.v:2770.90-2770.260"
-  wire $or$ls180.v:2770$502_Y
-  attribute \src "ls180.v:2770.89-2770.335"
-  wire $or$ls180.v:2770$505_Y
-  attribute \src "ls180.v:2775.127-2775.221"
-  wire $or$ls180.v:2775$516_Y
-  attribute \src "ls180.v:2775.126-2775.296"
-  wire $or$ls180.v:2775$519_Y
-  attribute \src "ls180.v:2775.125-2775.371"
-  wire $or$ls180.v:2775$522_Y
-  attribute \src "ls180.v:2775.29-2775.406"
-  wire $or$ls180.v:2775$527_Y
-  attribute \src "ls180.v:2775.501-2775.595"
-  wire $or$ls180.v:2775$532_Y
-  attribute \src "ls180.v:2775.500-2775.670"
-  wire $or$ls180.v:2775$535_Y
-  attribute \src "ls180.v:2775.499-2775.745"
-  wire $or$ls180.v:2775$538_Y
-  attribute \src "ls180.v:2775.28-2775.780"
-  wire $or$ls180.v:2775$543_Y
-  attribute \src "ls180.v:2775.875-2775.969"
-  wire $or$ls180.v:2775$548_Y
-  attribute \src "ls180.v:2775.874-2775.1044"
-  wire $or$ls180.v:2775$551_Y
-  attribute \src "ls180.v:2775.873-2775.1119"
-  wire $or$ls180.v:2775$554_Y
-  attribute \src "ls180.v:2775.27-2775.1154"
-  wire $or$ls180.v:2775$559_Y
-  attribute \src "ls180.v:2775.1249-2775.1343"
-  wire $or$ls180.v:2775$564_Y
-  attribute \src "ls180.v:2775.1248-2775.1418"
-  wire $or$ls180.v:2775$567_Y
-  attribute \src "ls180.v:2775.1247-2775.1493"
-  wire $or$ls180.v:2775$570_Y
-  attribute \src "ls180.v:2775.26-2775.1528"
-  wire $or$ls180.v:2775$575_Y
-  attribute \src "ls180.v:2838.10-2838.42"
-  wire $or$ls180.v:2838$584_Y
-  attribute \src "ls180.v:2865.30-2865.59"
-  wire $or$ls180.v:2865$594_Y
-  attribute \src "ls180.v:2866.29-2866.58"
-  wire $or$ls180.v:2866$598_Y
-  attribute \src "ls180.v:2867.38-2867.100"
-  wire $or$ls180.v:2867$604_Y
-  attribute \src "ls180.v:2868.19-2868.67"
-  wire $or$ls180.v:2868$607_Y
-  attribute \src "ls180.v:2869.21-2869.75"
-  wire $or$ls180.v:2869$609_Y
-  attribute \src "ls180.v:2899.32-2899.59"
-  wire $or$ls180.v:2899$617_Y
-  attribute \src "ls180.v:2923.15-2923.124"
-  wire $or$ls180.v:2923$627_Y
-  attribute \src "ls180.v:2938.60-2938.92"
-  wire $or$ls180.v:2938$629_Y
-  attribute \src "ls180.v:2949.52-2949.95"
-  wire $or$ls180.v:2949$634_Y
-  attribute \src "ls180.v:2968.60-2968.92"
-  wire $or$ls180.v:2968$640_Y
-  attribute \src "ls180.v:2979.52-2979.95"
-  wire $or$ls180.v:2979$645_Y
-  attribute \src "ls180.v:3162.38-3162.83"
-  wire $or$ls180.v:3162$683_Y
-  attribute \src "ls180.v:3162.37-3162.121"
-  wire $or$ls180.v:3162$684_Y
-  attribute \src "ls180.v:3162.36-3162.159"
-  wire $or$ls180.v:3162$685_Y
-  attribute \src "ls180.v:3162.35-3162.200"
-  wire $or$ls180.v:3162$686_Y
-  attribute \src "ls180.v:3162.34-3162.251"
-  wire $or$ls180.v:3162$687_Y
-  attribute \src "ls180.v:3168.33-3168.78"
-  wire $or$ls180.v:3168$692_Y
-  attribute \src "ls180.v:3168.32-3168.116"
-  wire $or$ls180.v:3168$693_Y
-  attribute \src "ls180.v:3168.31-3168.154"
-  wire $or$ls180.v:3168$694_Y
-  attribute \src "ls180.v:3168.30-3168.195"
-  wire $or$ls180.v:3168$695_Y
-  attribute \src "ls180.v:3168.29-3168.246"
-  wire $or$ls180.v:3168$696_Y
-  attribute \src "ls180.v:3169.35-3169.158"
-  wire width 64 $or$ls180.v:3169$699_Y
-  attribute \src "ls180.v:3169.34-3169.235"
-  wire width 64 $or$ls180.v:3169$701_Y
-  attribute \src "ls180.v:3169.33-3169.312"
-  wire width 64 $or$ls180.v:3169$703_Y
-  attribute \src "ls180.v:3169.32-3169.392"
-  wire width 64 $or$ls180.v:3169$705_Y
-  attribute \src "ls180.v:3169.31-3169.482"
-  wire width 64 $or$ls180.v:3169$707_Y
-  attribute \src "ls180.v:3449.52-3449.129"
-  wire width 8 $or$ls180.v:3449$1109_Y
-  attribute \src "ls180.v:3449.51-3449.170"
-  wire width 8 $or$ls180.v:3449$1110_Y
-  attribute \src "ls180.v:3449.50-3449.211"
-  wire width 8 $or$ls180.v:3449$1111_Y
-  attribute \src "ls180.v:3449.49-3449.252"
-  wire width 8 $or$ls180.v:3449$1112_Y
-  attribute \src "ls180.v:3449.48-3449.293"
-  wire width 8 $or$ls180.v:3449$1113_Y
-  attribute \src "ls180.v:3449.47-3449.334"
-  wire width 8 $or$ls180.v:3449$1114_Y
-  attribute \src "ls180.v:3449.46-3449.375"
-  wire width 8 $or$ls180.v:3449$1115_Y
-  attribute \src "ls180.v:3776.72-3776.166"
-  wire $or$ls180.v:3776$1140_Y
-  attribute \src "ls180.v:3776.71-3776.241"
-  wire $or$ls180.v:3776$1143_Y
-  attribute \src "ls180.v:3776.70-3776.316"
-  wire $or$ls180.v:3776$1146_Y
-  attribute \src "ls180.v:3800.72-3800.166"
-  wire $or$ls180.v:3800$1156_Y
-  attribute \src "ls180.v:3800.71-3800.241"
-  wire $or$ls180.v:3800$1159_Y
-  attribute \src "ls180.v:3800.70-3800.316"
-  wire $or$ls180.v:3800$1162_Y
-  attribute \src "ls180.v:3824.72-3824.166"
-  wire $or$ls180.v:3824$1172_Y
-  attribute \src "ls180.v:3824.71-3824.241"
-  wire $or$ls180.v:3824$1175_Y
-  attribute \src "ls180.v:3824.70-3824.316"
-  wire $or$ls180.v:3824$1178_Y
-  attribute \src "ls180.v:3848.72-3848.166"
-  wire $or$ls180.v:3848$1188_Y
-  attribute \src "ls180.v:3848.71-3848.241"
-  wire $or$ls180.v:3848$1191_Y
-  attribute \src "ls180.v:3848.70-3848.316"
-  wire $or$ls180.v:3848$1194_Y
-  attribute \src "ls180.v:4301.15-4301.58"
-  wire $or$ls180.v:4301$1248_Y
-  attribute \src "ls180.v:4302.15-4302.58"
-  wire $or$ls180.v:4302$1249_Y
-  attribute \src "ls180.v:4303.15-4303.58"
-  wire $or$ls180.v:4303$1250_Y
-  attribute \src "ls180.v:4304.15-4304.58"
-  wire $or$ls180.v:4304$1251_Y
-  attribute \src "ls180.v:4305.15-4305.58"
-  wire $or$ls180.v:4305$1252_Y
-  attribute \src "ls180.v:4306.15-4306.58"
-  wire $or$ls180.v:4306$1253_Y
-  attribute \src "ls180.v:4307.15-4307.58"
-  wire $or$ls180.v:4307$1254_Y
-  attribute \src "ls180.v:4308.15-4308.58"
-  wire $or$ls180.v:4308$1255_Y
-  attribute \src "ls180.v:4309.15-4309.58"
-  wire $or$ls180.v:4309$1256_Y
-  attribute \src "ls180.v:4310.15-4310.58"
-  wire $or$ls180.v:4310$1257_Y
+  wire $or$ls180.v:2755$473_Y
+  attribute \src "ls180.v:2760.127-2760.221"
+  wire $or$ls180.v:2760$484_Y
+  attribute \src "ls180.v:2760.126-2760.296"
+  wire $or$ls180.v:2760$487_Y
+  attribute \src "ls180.v:2760.125-2760.371"
+  wire $or$ls180.v:2760$490_Y
+  attribute \src "ls180.v:2760.29-2760.406"
+  wire $or$ls180.v:2760$495_Y
+  attribute \src "ls180.v:2760.501-2760.595"
+  wire $or$ls180.v:2760$500_Y
+  attribute \src "ls180.v:2760.500-2760.670"
+  wire $or$ls180.v:2760$503_Y
+  attribute \src "ls180.v:2760.499-2760.745"
+  wire $or$ls180.v:2760$506_Y
+  attribute \src "ls180.v:2760.28-2760.780"
+  wire $or$ls180.v:2760$511_Y
+  attribute \src "ls180.v:2760.875-2760.969"
+  wire $or$ls180.v:2760$516_Y
+  attribute \src "ls180.v:2760.874-2760.1044"
+  wire $or$ls180.v:2760$519_Y
+  attribute \src "ls180.v:2760.873-2760.1119"
+  wire $or$ls180.v:2760$522_Y
+  attribute \src "ls180.v:2760.27-2760.1154"
+  wire $or$ls180.v:2760$527_Y
+  attribute \src "ls180.v:2760.1249-2760.1343"
+  wire $or$ls180.v:2760$532_Y
+  attribute \src "ls180.v:2760.1248-2760.1418"
+  wire $or$ls180.v:2760$535_Y
+  attribute \src "ls180.v:2760.1247-2760.1493"
+  wire $or$ls180.v:2760$538_Y
+  attribute \src "ls180.v:2760.26-2760.1528"
+  wire $or$ls180.v:2760$543_Y
+  attribute \src "ls180.v:2823.10-2823.42"
+  wire $or$ls180.v:2823$552_Y
+  attribute \src "ls180.v:2850.30-2850.59"
+  wire $or$ls180.v:2850$562_Y
+  attribute \src "ls180.v:2851.29-2851.58"
+  wire $or$ls180.v:2851$566_Y
+  attribute \src "ls180.v:2852.38-2852.100"
+  wire $or$ls180.v:2852$572_Y
+  attribute \src "ls180.v:2853.19-2853.67"
+  wire $or$ls180.v:2853$575_Y
+  attribute \src "ls180.v:2854.21-2854.75"
+  wire $or$ls180.v:2854$577_Y
+  attribute \src "ls180.v:2884.32-2884.59"
+  wire $or$ls180.v:2884$585_Y
+  attribute \src "ls180.v:2908.15-2908.124"
+  wire $or$ls180.v:2908$595_Y
+  attribute \src "ls180.v:2923.60-2923.92"
+  wire $or$ls180.v:2923$597_Y
+  attribute \src "ls180.v:2934.52-2934.95"
+  wire $or$ls180.v:2934$602_Y
+  attribute \src "ls180.v:2953.60-2953.92"
+  wire $or$ls180.v:2953$608_Y
+  attribute \src "ls180.v:2964.52-2964.95"
+  wire $or$ls180.v:2964$613_Y
+  attribute \src "ls180.v:3147.38-3147.83"
+  wire $or$ls180.v:3147$651_Y
+  attribute \src "ls180.v:3147.37-3147.120"
+  wire $or$ls180.v:3147$652_Y
+  attribute \src "ls180.v:3147.36-3147.157"
+  wire $or$ls180.v:3147$653_Y
+  attribute \src "ls180.v:3147.35-3147.173"
+  wire $or$ls180.v:3147$654_Y
+  attribute \src "ls180.v:3147.34-3147.213"
+  wire $or$ls180.v:3147$655_Y
+  attribute \src "ls180.v:3153.33-3153.78"
+  wire $or$ls180.v:3153$660_Y
+  attribute \src "ls180.v:3153.32-3153.115"
+  wire $or$ls180.v:3153$661_Y
+  attribute \src "ls180.v:3153.31-3153.152"
+  wire $or$ls180.v:3153$662_Y
+  attribute \src "ls180.v:3153.30-3153.168"
+  wire $or$ls180.v:3153$663_Y
+  attribute \src "ls180.v:3153.29-3153.208"
+  wire $or$ls180.v:3153$664_Y
+  attribute \src "ls180.v:3154.35-3154.158"
+  wire width 32 $or$ls180.v:3154$667_Y
+  attribute \src "ls180.v:3154.34-3154.234"
+  wire width 32 $or$ls180.v:3154$669_Y
+  attribute \src "ls180.v:3154.33-3154.310"
+  wire width 32 $or$ls180.v:3154$671_Y
+  attribute \src "ls180.v:3154.32-3154.365"
+  wire width 32 $or$ls180.v:3154$673_Y
+  attribute \src "ls180.v:3154.31-3154.444"
+  wire width 32 $or$ls180.v:3154$675_Y
+  attribute \src "ls180.v:3434.52-3434.129"
+  wire width 8 $or$ls180.v:3434$1077_Y
+  attribute \src "ls180.v:3434.51-3434.170"
+  wire width 8 $or$ls180.v:3434$1078_Y
+  attribute \src "ls180.v:3434.50-3434.211"
+  wire width 8 $or$ls180.v:3434$1079_Y
+  attribute \src "ls180.v:3434.49-3434.252"
+  wire width 8 $or$ls180.v:3434$1080_Y
+  attribute \src "ls180.v:3434.48-3434.293"
+  wire width 8 $or$ls180.v:3434$1081_Y
+  attribute \src "ls180.v:3434.47-3434.334"
+  wire width 8 $or$ls180.v:3434$1082_Y
+  attribute \src "ls180.v:3434.46-3434.375"
+  wire width 8 $or$ls180.v:3434$1083_Y
+  attribute \src "ls180.v:3761.72-3761.166"
+  wire $or$ls180.v:3761$1108_Y
+  attribute \src "ls180.v:3761.71-3761.241"
+  wire $or$ls180.v:3761$1111_Y
+  attribute \src "ls180.v:3761.70-3761.316"
+  wire $or$ls180.v:3761$1114_Y
+  attribute \src "ls180.v:3785.72-3785.166"
+  wire $or$ls180.v:3785$1124_Y
+  attribute \src "ls180.v:3785.71-3785.241"
+  wire $or$ls180.v:3785$1127_Y
+  attribute \src "ls180.v:3785.70-3785.316"
+  wire $or$ls180.v:3785$1130_Y
+  attribute \src "ls180.v:3809.72-3809.166"
+  wire $or$ls180.v:3809$1140_Y
+  attribute \src "ls180.v:3809.71-3809.241"
+  wire $or$ls180.v:3809$1143_Y
+  attribute \src "ls180.v:3809.70-3809.316"
+  wire $or$ls180.v:3809$1146_Y
+  attribute \src "ls180.v:3833.72-3833.166"
+  wire $or$ls180.v:3833$1156_Y
+  attribute \src "ls180.v:3833.71-3833.241"
+  wire $or$ls180.v:3833$1159_Y
+  attribute \src "ls180.v:3833.70-3833.316"
+  wire $or$ls180.v:3833$1162_Y
+  attribute \src "ls180.v:4286.15-4286.58"
+  wire $or$ls180.v:4286$1216_Y
+  attribute \src "ls180.v:4287.15-4287.58"
+  wire $or$ls180.v:4287$1217_Y
+  attribute \src "ls180.v:4288.15-4288.58"
+  wire $or$ls180.v:4288$1218_Y
+  attribute \src "ls180.v:4289.15-4289.58"
+  wire $or$ls180.v:4289$1219_Y
+  attribute \src "ls180.v:4290.15-4290.58"
+  wire $or$ls180.v:4290$1220_Y
+  attribute \src "ls180.v:4291.15-4291.58"
+  wire $or$ls180.v:4291$1221_Y
+  attribute \src "ls180.v:4292.15-4292.58"
+  wire $or$ls180.v:4292$1222_Y
+  attribute \src "ls180.v:4293.15-4293.58"
+  wire $or$ls180.v:4293$1223_Y
+  attribute \src "ls180.v:4294.15-4294.58"
+  wire $or$ls180.v:4294$1224_Y
+  attribute \src "ls180.v:4295.15-4295.58"
+  wire $or$ls180.v:4295$1225_Y
+  attribute \src "ls180.v:4296.16-4296.60"
+  wire $or$ls180.v:4296$1226_Y
+  attribute \src "ls180.v:4297.16-4297.60"
+  wire $or$ls180.v:4297$1227_Y
+  attribute \src "ls180.v:4298.16-4298.60"
+  wire $or$ls180.v:4298$1228_Y
+  attribute \src "ls180.v:4299.16-4299.60"
+  wire $or$ls180.v:4299$1229_Y
+  attribute \src "ls180.v:4300.16-4300.60"
+  wire $or$ls180.v:4300$1230_Y
+  attribute \src "ls180.v:4301.16-4301.60"
+  wire $or$ls180.v:4301$1231_Y
+  attribute \src "ls180.v:4302.16-4302.60"
+  wire $or$ls180.v:4302$1232_Y
+  attribute \src "ls180.v:4303.16-4303.60"
+  wire $or$ls180.v:4303$1233_Y
+  attribute \src "ls180.v:4304.16-4304.60"
+  wire $or$ls180.v:4304$1234_Y
+  attribute \src "ls180.v:4305.16-4305.60"
+  wire $or$ls180.v:4305$1235_Y
+  attribute \src "ls180.v:4306.16-4306.60"
+  wire $or$ls180.v:4306$1236_Y
+  attribute \src "ls180.v:4307.16-4307.60"
+  wire $or$ls180.v:4307$1237_Y
+  attribute \src "ls180.v:4308.16-4308.60"
+  wire $or$ls180.v:4308$1238_Y
+  attribute \src "ls180.v:4309.16-4309.60"
+  wire $or$ls180.v:4309$1239_Y
+  attribute \src "ls180.v:4310.16-4310.60"
+  wire $or$ls180.v:4310$1240_Y
   attribute \src "ls180.v:4311.16-4311.60"
-  wire $or$ls180.v:4311$1258_Y
+  wire $or$ls180.v:4311$1241_Y
   attribute \src "ls180.v:4312.16-4312.60"
-  wire $or$ls180.v:4312$1259_Y
+  wire $or$ls180.v:4312$1242_Y
   attribute \src "ls180.v:4313.16-4313.60"
-  wire $or$ls180.v:4313$1260_Y
+  wire $or$ls180.v:4313$1243_Y
   attribute \src "ls180.v:4314.16-4314.60"
-  wire $or$ls180.v:4314$1261_Y
+  wire $or$ls180.v:4314$1244_Y
   attribute \src "ls180.v:4315.16-4315.60"
-  wire $or$ls180.v:4315$1262_Y
+  wire $or$ls180.v:4315$1245_Y
   attribute \src "ls180.v:4316.16-4316.60"
-  wire $or$ls180.v:4316$1263_Y
+  wire $or$ls180.v:4316$1246_Y
   attribute \src "ls180.v:4317.16-4317.60"
-  wire $or$ls180.v:4317$1264_Y
+  wire $or$ls180.v:4317$1247_Y
   attribute \src "ls180.v:4318.16-4318.60"
-  wire $or$ls180.v:4318$1265_Y
+  wire $or$ls180.v:4318$1248_Y
   attribute \src "ls180.v:4319.16-4319.60"
-  wire $or$ls180.v:4319$1266_Y
+  wire $or$ls180.v:4319$1249_Y
   attribute \src "ls180.v:4320.16-4320.60"
-  wire $or$ls180.v:4320$1267_Y
+  wire $or$ls180.v:4320$1250_Y
   attribute \src "ls180.v:4321.16-4321.60"
-  wire $or$ls180.v:4321$1268_Y
-  attribute \src "ls180.v:4322.16-4322.60"
-  wire $or$ls180.v:4322$1269_Y
-  attribute \src "ls180.v:4323.16-4323.60"
-  wire $or$ls180.v:4323$1270_Y
-  attribute \src "ls180.v:4324.16-4324.60"
-  wire $or$ls180.v:4324$1271_Y
-  attribute \src "ls180.v:4325.16-4325.60"
-  wire $or$ls180.v:4325$1272_Y
-  attribute \src "ls180.v:4326.16-4326.60"
-  wire $or$ls180.v:4326$1273_Y
-  attribute \src "ls180.v:4327.16-4327.60"
-  wire $or$ls180.v:4327$1274_Y
-  attribute \src "ls180.v:4328.16-4328.60"
-  wire $or$ls180.v:4328$1275_Y
-  attribute \src "ls180.v:4329.16-4329.60"
-  wire $or$ls180.v:4329$1276_Y
-  attribute \src "ls180.v:4330.16-4330.60"
-  wire $or$ls180.v:4330$1277_Y
-  attribute \src "ls180.v:4331.16-4331.60"
-  wire $or$ls180.v:4331$1278_Y
-  attribute \src "ls180.v:4332.16-4332.60"
-  wire $or$ls180.v:4332$1279_Y
-  attribute \src "ls180.v:4333.16-4333.60"
-  wire $or$ls180.v:4333$1280_Y
-  attribute \src "ls180.v:4334.16-4334.60"
-  wire $or$ls180.v:4334$1281_Y
-  attribute \src "ls180.v:4335.16-4335.60"
-  wire $or$ls180.v:4335$1282_Y
-  attribute \src "ls180.v:4336.16-4336.60"
-  wire $or$ls180.v:4336$1283_Y
-  attribute \src "ls180.v:4337.7-4337.58"
-  wire $or$ls180.v:4337$1284_Y
-  attribute \src "ls180.v:4348.7-4348.58"
-  wire $or$ls180.v:4348$1285_Y
-  attribute \src "ls180.v:4359.7-4359.40"
-  wire $or$ls180.v:4359$1286_Y
-  attribute \src "ls180.v:4492.7-4492.97"
-  wire $or$ls180.v:4492$1325_Y
-  attribute \src "ls180.v:4538.7-4538.97"
-  wire $or$ls180.v:4538$1341_Y
-  attribute \src "ls180.v:4584.7-4584.97"
-  wire $or$ls180.v:4584$1357_Y
-  attribute \src "ls180.v:4630.7-4630.97"
-  wire $or$ls180.v:4630$1373_Y
-  attribute \src "ls180.v:4818.45-4818.130"
-  wire $or$ls180.v:4818$1394_Y
-  attribute \src "ls180.v:4818.44-4818.212"
-  wire $or$ls180.v:4818$1397_Y
-  attribute \src "ls180.v:4818.43-4818.294"
-  wire $or$ls180.v:4818$1400_Y
-  attribute \src "ls180.v:4818.42-4818.376"
-  wire $or$ls180.v:4818$1403_Y
-  attribute \src "ls180.v:4819.46-4819.131"
-  wire $or$ls180.v:4819$1406_Y
-  attribute \src "ls180.v:4819.45-4819.213"
-  wire $or$ls180.v:4819$1409_Y
-  attribute \src "ls180.v:4819.44-4819.295"
-  wire $or$ls180.v:4819$1412_Y
-  attribute \src "ls180.v:4819.43-4819.377"
-  wire $or$ls180.v:4819$1415_Y
-  attribute \src "ls180.v:4823.7-4823.39"
-  wire $or$ls180.v:4823$1416_Y
-  attribute \src "ls180.v:5748.8-5748.46"
-  wire $or$ls180.v:5748$1626_Y
-  attribute \src "ls180.v:1949.41-1949.84"
-  wire width 13 $sshl$ls180.v:1949$131_Y
-  attribute \src "ls180.v:2106.41-2106.84"
-  wire width 13 $sshl$ls180.v:2106$161_Y
-  attribute \src "ls180.v:2263.41-2263.84"
-  wire width 13 $sshl$ls180.v:2263$191_Y
-  attribute \src "ls180.v:2420.41-2420.84"
-  wire width 13 $sshl$ls180.v:2420$221_Y
-  attribute \src "ls180.v:1980.58-1980.112"
-  wire width 3 $sub$ls180.v:1980$144_Y
-  attribute \src "ls180.v:2137.58-2137.112"
-  wire width 3 $sub$ls180.v:2137$174_Y
-  attribute \src "ls180.v:2294.58-2294.112"
-  wire width 3 $sub$ls180.v:2294$204_Y
-  attribute \src "ls180.v:2451.58-2451.112"
-  wire width 3 $sub$ls180.v:2451$234_Y
-  attribute \src "ls180.v:2857.33-2857.65"
-  wire width 31 $sub$ls180.v:2857$588_Y
-  attribute \src "ls180.v:2943.26-2943.48"
-  wire width 4 $sub$ls180.v:2943$633_Y
-  attribute \src "ls180.v:2973.26-2973.48"
-  wire width 4 $sub$ls180.v:2973$644_Y
-  attribute \src "ls180.v:4383.26-4383.50"
-  wire width 32 $sub$ls180.v:4383$1293_Y
-  attribute \src "ls180.v:4408.26-4408.51"
-  wire width 10 $sub$ls180.v:4408$1301_Y
-  attribute \src "ls180.v:4414.29-4414.57"
-  wire $sub$ls180.v:4414$1302_Y
-  attribute \src "ls180.v:4425.31-4425.59"
-  wire $sub$ls180.v:4425$1305_Y
-  attribute \src "ls180.v:4489.54-4489.106"
-  wire width 4 $sub$ls180.v:4489$1323_Y
-  attribute \src "ls180.v:4508.41-4508.80"
-  wire width 3 $sub$ls180.v:4508$1327_Y
-  attribute \src "ls180.v:4535.54-4535.106"
-  wire width 4 $sub$ls180.v:4535$1339_Y
-  attribute \src "ls180.v:4554.41-4554.80"
-  wire width 3 $sub$ls180.v:4554$1343_Y
-  attribute \src "ls180.v:4581.54-4581.106"
-  wire width 4 $sub$ls180.v:4581$1355_Y
-  attribute \src "ls180.v:4600.41-4600.80"
-  wire width 3 $sub$ls180.v:4600$1359_Y
-  attribute \src "ls180.v:4627.54-4627.106"
-  wire width 4 $sub$ls180.v:4627$1371_Y
-  attribute \src "ls180.v:4646.41-4646.80"
-  wire width 3 $sub$ls180.v:4646$1375_Y
-  attribute \src "ls180.v:4657.20-4657.38"
-  wire width 5 $sub$ls180.v:4657$1379_Y
-  attribute \src "ls180.v:4664.20-4664.38"
-  wire width 4 $sub$ls180.v:4664$1382_Y
+  wire $or$ls180.v:4321$1251_Y
+  attribute \src "ls180.v:4322.7-4322.83"
+  wire $or$ls180.v:4322$1252_Y
+  attribute \src "ls180.v:4333.7-4333.83"
+  wire $or$ls180.v:4333$1253_Y
+  attribute \src "ls180.v:4344.7-4344.83"
+  wire $or$ls180.v:4344$1254_Y
+  attribute \src "ls180.v:4477.7-4477.97"
+  wire $or$ls180.v:4477$1293_Y
+  attribute \src "ls180.v:4523.7-4523.97"
+  wire $or$ls180.v:4523$1309_Y
+  attribute \src "ls180.v:4569.7-4569.97"
+  wire $or$ls180.v:4569$1325_Y
+  attribute \src "ls180.v:4615.7-4615.97"
+  wire $or$ls180.v:4615$1341_Y
+  attribute \src "ls180.v:4803.45-4803.130"
+  wire $or$ls180.v:4803$1362_Y
+  attribute \src "ls180.v:4803.44-4803.212"
+  wire $or$ls180.v:4803$1365_Y
+  attribute \src "ls180.v:4803.43-4803.294"
+  wire $or$ls180.v:4803$1368_Y
+  attribute \src "ls180.v:4803.42-4803.376"
+  wire $or$ls180.v:4803$1371_Y
+  attribute \src "ls180.v:4804.46-4804.131"
+  wire $or$ls180.v:4804$1374_Y
+  attribute \src "ls180.v:4804.45-4804.213"
+  wire $or$ls180.v:4804$1377_Y
+  attribute \src "ls180.v:4804.44-4804.295"
+  wire $or$ls180.v:4804$1380_Y
+  attribute \src "ls180.v:4804.43-4804.377"
+  wire $or$ls180.v:4804$1383_Y
+  attribute \src "ls180.v:4808.7-4808.39"
+  wire $or$ls180.v:4808$1384_Y
+  attribute \src "ls180.v:5717.8-5717.46"
+  wire $or$ls180.v:5717$1546_Y
+  attribute \src "ls180.v:1934.41-1934.84"
+  wire width 13 $sshl$ls180.v:1934$99_Y
+  attribute \src "ls180.v:2091.41-2091.84"
+  wire width 13 $sshl$ls180.v:2091$129_Y
+  attribute \src "ls180.v:2248.41-2248.84"
+  wire width 13 $sshl$ls180.v:2248$159_Y
+  attribute \src "ls180.v:2405.41-2405.84"
+  wire width 13 $sshl$ls180.v:2405$189_Y
+  attribute \src "ls180.v:1965.58-1965.112"
+  wire width 3 $sub$ls180.v:1965$112_Y
+  attribute \src "ls180.v:2122.58-2122.112"
+  wire width 3 $sub$ls180.v:2122$142_Y
+  attribute \src "ls180.v:2279.58-2279.112"
+  wire width 3 $sub$ls180.v:2279$172_Y
+  attribute \src "ls180.v:2436.58-2436.112"
+  wire width 3 $sub$ls180.v:2436$202_Y
+  attribute \src "ls180.v:2842.33-2842.65"
+  wire width 31 $sub$ls180.v:2842$556_Y
+  attribute \src "ls180.v:2928.26-2928.48"
+  wire width 4 $sub$ls180.v:2928$601_Y
+  attribute \src "ls180.v:2958.26-2958.48"
+  wire width 4 $sub$ls180.v:2958$612_Y
+  attribute \src "ls180.v:4368.26-4368.50"
+  wire width 32 $sub$ls180.v:4368$1261_Y
+  attribute \src "ls180.v:4393.26-4393.51"
+  wire width 10 $sub$ls180.v:4393$1269_Y
+  attribute \src "ls180.v:4399.29-4399.57"
+  wire $sub$ls180.v:4399$1270_Y
+  attribute \src "ls180.v:4410.31-4410.59"
+  wire $sub$ls180.v:4410$1273_Y
+  attribute \src "ls180.v:4474.54-4474.106"
+  wire width 4 $sub$ls180.v:4474$1291_Y
+  attribute \src "ls180.v:4493.41-4493.80"
+  wire width 3 $sub$ls180.v:4493$1295_Y
+  attribute \src "ls180.v:4520.54-4520.106"
+  wire width 4 $sub$ls180.v:4520$1307_Y
+  attribute \src "ls180.v:4539.41-4539.80"
+  wire width 3 $sub$ls180.v:4539$1311_Y
+  attribute \src "ls180.v:4566.54-4566.106"
+  wire width 4 $sub$ls180.v:4566$1323_Y
+  attribute \src "ls180.v:4585.41-4585.80"
+  wire width 3 $sub$ls180.v:4585$1327_Y
+  attribute \src "ls180.v:4612.54-4612.106"
+  wire width 4 $sub$ls180.v:4612$1339_Y
+  attribute \src "ls180.v:4631.41-4631.80"
+  wire width 3 $sub$ls180.v:4631$1343_Y
+  attribute \src "ls180.v:4642.20-4642.38"
+  wire width 5 $sub$ls180.v:4642$1347_Y
+  attribute \src "ls180.v:4649.20-4649.38"
+  wire width 4 $sub$ls180.v:4649$1350_Y
+  attribute \src "ls180.v:4781.28-4781.54"
+  wire $sub$ls180.v:4781$1355_Y
   attribute \src "ls180.v:4796.28-4796.54"
-  wire $sub$ls180.v:4796$1387_Y
-  attribute \src "ls180.v:4811.28-4811.54"
-  wire width 3 $sub$ls180.v:4811$1390_Y
-  attribute \src "ls180.v:4938.23-4938.44"
-  wire width 5 $sub$ls180.v:4938$1449_Y
-  attribute \src "ls180.v:4960.23-4960.44"
-  wire width 5 $sub$ls180.v:4960$1460_Y
-  attribute \src "ls180.v:5025.26-5025.50"
-  wire width 20 $sub$ls180.v:5025$1465_Y
-  attribute \src "ls180.v:833.6-833.13"
+  wire width 3 $sub$ls180.v:4796$1358_Y
+  attribute \src "ls180.v:4923.23-4923.44"
+  wire width 5 $sub$ls180.v:4923$1417_Y
+  attribute \src "ls180.v:4945.23-4945.44"
+  wire width 5 $sub$ls180.v:4945$1428_Y
+  attribute \src "ls180.v:5010.26-5010.50"
+  wire width 20 $sub$ls180.v:5010$1433_Y
+  attribute \src "ls180.v:834.6-834.13"
   wire \ack_cmd
-  attribute \src "ls180.v:835.6-835.15"
+  attribute \src "ls180.v:836.6-836.15"
   wire \ack_rdata
-  attribute \src "ls180.v:834.6-834.15"
+  attribute \src "ls180.v:835.6-835.15"
   wire \ack_wdata
-  attribute \src "ls180.v:1388.11-1388.23"
+  attribute \src "ls180.v:1381.11-1381.23"
   wire width 2 \array_muxed0
-  attribute \src "ls180.v:1389.12-1389.24"
+  attribute \src "ls180.v:1382.12-1382.24"
   wire width 13 \array_muxed1
-  attribute \src "ls180.v:1390.5-1390.17"
+  attribute \src "ls180.v:1383.5-1383.17"
   wire \array_muxed2
-  attribute \src "ls180.v:1391.5-1391.17"
+  attribute \src "ls180.v:1384.5-1384.17"
   wire \array_muxed3
-  attribute \src "ls180.v:1392.5-1392.17"
+  attribute \src "ls180.v:1385.5-1385.17"
   wire \array_muxed4
-  attribute \src "ls180.v:1393.5-1393.17"
+  attribute \src "ls180.v:1386.5-1386.17"
   wire \array_muxed5
-  attribute \src "ls180.v:1394.5-1394.17"
+  attribute \src "ls180.v:1387.5-1387.17"
   wire \array_muxed6
-  attribute \src "ls180.v:831.5-831.17"
+  attribute \src "ls180.v:832.5-832.17"
   wire \cmd_consumed
-  attribute \src "ls180.v:214.5-214.23"
-  wire \converter0_counter
-  attribute \src "ls180.v:1009.5-1009.58"
-  wire \converter0_counter_subfragments_converter0_next_value
-  attribute \src "ls180.v:1010.5-1010.61"
-  wire \converter0_counter_subfragments_converter0_next_value_ce
-  attribute \src "ls180.v:216.12-216.28"
-  wire width 64 \converter0_dat_r
-  attribute \src "ls180.v:215.6-215.22"
-  wire \converter0_reset
-  attribute \src "ls180.v:213.5-213.20"
-  wire \converter0_skip
-  attribute \src "ls180.v:229.5-229.23"
-  wire \converter1_counter
-  attribute \src "ls180.v:1013.5-1013.58"
-  wire \converter1_counter_subfragments_converter1_next_value
-  attribute \src "ls180.v:1014.5-1014.61"
-  wire \converter1_counter_subfragments_converter1_next_value_ce
-  attribute \src "ls180.v:231.12-231.28"
-  wire width 64 \converter1_dat_r
-  attribute \src "ls180.v:230.6-230.22"
-  wire \converter1_reset
-  attribute \src "ls180.v:228.5-228.20"
-  wire \converter1_skip
-  attribute \src "ls180.v:828.5-828.22"
+  attribute \src "ls180.v:829.5-829.22"
   wire \converter_counter
-  attribute \src "ls180.v:1054.5-1054.46"
+  attribute \src "ls180.v:1055.5-1055.46"
   wire \converter_counter_subfragments_next_value
-  attribute \src "ls180.v:1055.5-1055.49"
+  attribute \src "ls180.v:1056.5-1056.49"
   wire \converter_counter_subfragments_next_value_ce
-  attribute \src "ls180.v:830.12-830.27"
+  attribute \src "ls180.v:831.12-831.27"
   wire width 32 \converter_dat_r
-  attribute \src "ls180.v:829.6-829.21"
+  attribute \src "ls180.v:830.6-830.21"
   wire \converter_reset
-  attribute \src "ls180.v:827.5-827.19"
+  attribute \src "ls180.v:828.5-828.19"
   wire \converter_skip
-  attribute \src "ls180.v:245.6-245.18"
+  attribute \src "ls180.v:258.6-258.18"
   wire \dfi_p0_act_n
-  attribute \src "ls180.v:236.13-236.27"
+  attribute \src "ls180.v:249.13-249.27"
   wire width 13 \dfi_p0_address
-  attribute \src "ls180.v:237.12-237.23"
+  attribute \src "ls180.v:250.12-250.23"
   wire width 2 \dfi_p0_bank
-  attribute \src "ls180.v:238.6-238.18"
+  attribute \src "ls180.v:251.6-251.18"
   wire \dfi_p0_cas_n
-  attribute \src "ls180.v:242.6-242.16"
+  attribute \src "ls180.v:255.6-255.16"
   wire \dfi_p0_cke
-  attribute \src "ls180.v:239.6-239.17"
+  attribute \src "ls180.v:252.6-252.17"
   wire \dfi_p0_cs_n
-  attribute \src "ls180.v:243.6-243.16"
+  attribute \src "ls180.v:256.6-256.16"
   wire \dfi_p0_odt
-  attribute \src "ls180.v:240.6-240.18"
+  attribute \src "ls180.v:253.6-253.18"
   wire \dfi_p0_ras_n
-  attribute \src "ls180.v:250.12-250.25"
+  attribute \src "ls180.v:263.12-263.25"
   wire width 16 \dfi_p0_rddata
-  attribute \src "ls180.v:249.6-249.22"
+  attribute \src "ls180.v:262.6-262.22"
   wire \dfi_p0_rddata_en
-  attribute \src "ls180.v:251.5-251.24"
+  attribute \src "ls180.v:264.5-264.24"
   wire \dfi_p0_rddata_valid
-  attribute \src "ls180.v:244.6-244.20"
+  attribute \src "ls180.v:257.6-257.20"
   wire \dfi_p0_reset_n
-  attribute \src "ls180.v:241.6-241.17"
+  attribute \src "ls180.v:254.6-254.17"
   wire \dfi_p0_we_n
-  attribute \src "ls180.v:246.13-246.26"
+  attribute \src "ls180.v:259.13-259.26"
   wire width 16 \dfi_p0_wrdata
-  attribute \src "ls180.v:247.6-247.22"
+  attribute \src "ls180.v:260.6-260.22"
   wire \dfi_p0_wrdata_en
-  attribute \src "ls180.v:248.12-248.30"
+  attribute \src "ls180.v:261.12-261.30"
   wire width 2 \dfi_p0_wrdata_mask
-  attribute \src "ls180.v:998.12-998.17"
+  attribute \src "ls180.v:999.12-999.17"
   wire width 36 \dummy
-  attribute \src "ls180.v:26.13-26.19"
-  wire input 22 \eint_0
-  attribute \src "ls180.v:27.13-27.19"
-  wire input 23 \eint_1
-  attribute \src "ls180.v:28.13-28.19"
-  wire input 24 \eint_2
-  attribute \src "ls180.v:996.11-996.19"
+  attribute \src "ls180.v:7.13-7.19"
+  wire input 3 \eint_0
+  attribute \src "ls180.v:8.13-8.19"
+  wire input 4 \eint_1
+  attribute \src "ls180.v:9.13-9.19"
+  wire input 5 \eint_2
+  attribute \src "ls180.v:997.11-997.19"
   wire width 3 \eint_tmp
-  attribute \src "ls180.v:884.12-884.34"
+  attribute \src "ls180.v:885.12-885.34"
   wire width 2 \eventmanager_pending_r
-  attribute \src "ls180.v:883.6-883.29"
+  attribute \src "ls180.v:884.6-884.29"
   wire \eventmanager_pending_re
-  attribute \src "ls180.v:886.11-886.33"
+  attribute \src "ls180.v:887.11-887.33"
   wire width 2 \eventmanager_pending_w
-  attribute \src "ls180.v:885.6-885.29"
+  attribute \src "ls180.v:886.6-886.29"
   wire \eventmanager_pending_we
-  attribute \src "ls180.v:888.5-888.20"
+  attribute \src "ls180.v:889.5-889.20"
   wire \eventmanager_re
-  attribute \src "ls180.v:880.12-880.33"
+  attribute \src "ls180.v:881.12-881.33"
   wire width 2 \eventmanager_status_r
-  attribute \src "ls180.v:879.6-879.28"
+  attribute \src "ls180.v:880.6-880.28"
   wire \eventmanager_status_re
-  attribute \src "ls180.v:882.11-882.32"
+  attribute \src "ls180.v:883.11-883.32"
   wire width 2 \eventmanager_status_w
-  attribute \src "ls180.v:881.6-881.28"
+  attribute \src "ls180.v:882.6-882.28"
   wire \eventmanager_status_we
-  attribute \src "ls180.v:887.11-887.31"
+  attribute \src "ls180.v:888.11-888.31"
   wire width 2 \eventmanager_storage
-  attribute \src "ls180.v:979.5-979.16"
+  attribute \src "ls180.v:980.5-980.16"
   wire \gpio0_oe_re
-  attribute \src "ls180.v:978.11-978.27"
+  attribute \src "ls180.v:979.11-979.27"
   wire width 8 \gpio0_oe_storage
-  attribute \src "ls180.v:983.5-983.17"
+  attribute \src "ls180.v:984.5-984.17"
   wire \gpio0_out_re
-  attribute \src "ls180.v:982.11-982.28"
+  attribute \src "ls180.v:983.11-983.28"
   wire width 8 \gpio0_out_storage
-  attribute \src "ls180.v:984.11-984.28"
-  wire width 8 \gpio0_pads_gpio0i
   attribute \src "ls180.v:985.11-985.28"
+  wire width 8 \gpio0_pads_gpio0i
+  attribute \src "ls180.v:986.11-986.28"
   wire width 8 \gpio0_pads_gpio0o
-  attribute \src "ls180.v:986.11-986.29"
+  attribute \src "ls180.v:987.11-987.29"
   wire width 8 \gpio0_pads_gpio0oe
-  attribute \src "ls180.v:980.11-980.23"
+  attribute \src "ls180.v:981.11-981.23"
   wire width 8 \gpio0_status
-  attribute \src "ls180.v:981.6-981.14"
+  attribute \src "ls180.v:982.6-982.14"
   wire \gpio0_we
-  attribute \src "ls180.v:988.5-988.16"
+  attribute \src "ls180.v:989.5-989.16"
   wire \gpio1_oe_re
-  attribute \src "ls180.v:987.11-987.27"
+  attribute \src "ls180.v:988.11-988.27"
   wire width 8 \gpio1_oe_storage
-  attribute \src "ls180.v:992.5-992.17"
+  attribute \src "ls180.v:993.5-993.17"
   wire \gpio1_out_re
-  attribute \src "ls180.v:991.11-991.28"
+  attribute \src "ls180.v:992.11-992.28"
   wire width 8 \gpio1_out_storage
-  attribute \src "ls180.v:993.11-993.28"
-  wire width 8 \gpio1_pads_gpio1i
   attribute \src "ls180.v:994.11-994.28"
+  wire width 8 \gpio1_pads_gpio1i
+  attribute \src "ls180.v:995.11-995.28"
   wire width 8 \gpio1_pads_gpio1o
-  attribute \src "ls180.v:995.11-995.29"
+  attribute \src "ls180.v:996.11-996.29"
   wire width 8 \gpio1_pads_gpio1oe
-  attribute \src "ls180.v:989.11-989.23"
+  attribute \src "ls180.v:990.11-990.23"
   wire width 8 \gpio1_status
-  attribute \src "ls180.v:990.6-990.14"
+  attribute \src "ls180.v:991.6-991.14"
   wire \gpio1_we
-  attribute \src "ls180.v:5.20-5.26"
-  wire width 16 input 1 \gpio_i
-  attribute \src "ls180.v:6.21-6.27"
-  wire width 16 output 2 \gpio_o
-  attribute \src "ls180.v:7.21-7.28"
-  wire width 16 output 3 \gpio_oe
-  attribute \src "ls180.v:1000.6-1000.12"
+  attribute \src "ls180.v:30.20-30.26"
+  wire width 16 input 26 \gpio_i
+  attribute \src "ls180.v:31.21-31.27"
+  wire width 16 output 27 \gpio_o
+  attribute \src "ls180.v:32.21-32.28"
+  wire width 16 output 28 \gpio_oe
+  attribute \src "ls180.v:1001.6-1001.12"
   wire \i2c_oe
-  attribute \src "ls180.v:1003.5-1003.11"
+  attribute \src "ls180.v:1004.5-1004.11"
   wire \i2c_re
-  attribute \src "ls180.v:29.14-29.21"
-  wire output 25 \i2c_scl
-  attribute \src "ls180.v:999.6-999.15"
+  attribute \src "ls180.v:22.14-22.21"
+  wire output 18 \i2c_scl
+  attribute \src "ls180.v:1000.6-1000.15"
   wire \i2c_scl_1
-  attribute \src "ls180.v:1001.6-1001.14"
+  attribute \src "ls180.v:1002.6-1002.14"
   wire \i2c_sda0
-  attribute \src "ls180.v:1004.6-1004.14"
+  attribute \src "ls180.v:1005.6-1005.14"
   wire \i2c_sda1
-  attribute \src "ls180.v:30.13-30.22"
-  wire input 26 \i2c_sda_i
-  attribute \src "ls180.v:31.14-31.23"
-  wire output 27 \i2c_sda_o
-  attribute \src "ls180.v:32.14-32.24"
-  wire output 28 \i2c_sda_oe
-  attribute \src "ls180.v:1005.6-1005.16"
+  attribute \src "ls180.v:23.13-23.22"
+  wire input 19 \i2c_sda_i
+  attribute \src "ls180.v:24.14-24.23"
+  wire output 20 \i2c_sda_o
+  attribute \src "ls180.v:25.14-25.24"
+  wire output 21 \i2c_sda_oe
+  attribute \src "ls180.v:1006.6-1006.16"
   wire \i2c_status
-  attribute \src "ls180.v:1002.11-1002.22"
+  attribute \src "ls180.v:1003.11-1003.22"
   wire width 3 \i2c_storage
-  attribute \src "ls180.v:1006.6-1006.12"
+  attribute \src "ls180.v:1007.6-1007.12"
   wire \i2c_we
-  attribute \src "ls180.v:235.5-235.12"
+  attribute \src "ls180.v:248.5-248.12"
   wire \int_rst
-  attribute \src "ls180.v:208.5-208.39"
-  wire \interface0_converted_interface_ack
-  attribute \src "ls180.v:202.13-202.47"
-  wire width 30 \interface0_converted_interface_adr
-  attribute \src "ls180.v:211.12-211.46"
-  wire width 2 \interface0_converted_interface_bte
-  attribute \src "ls180.v:210.12-210.46"
-  wire width 3 \interface0_converted_interface_cti
-  attribute \src "ls180.v:206.6-206.40"
-  wire \interface0_converted_interface_cyc
-  attribute \src "ls180.v:204.13-204.49"
-  wire width 64 \interface0_converted_interface_dat_r
-  attribute \src "ls180.v:203.13-203.49"
-  wire width 64 \interface0_converted_interface_dat_w
-  attribute \src "ls180.v:212.5-212.39"
-  wire \interface0_converted_interface_err
-  attribute \src "ls180.v:205.12-205.46"
-  wire width 8 \interface0_converted_interface_sel
-  attribute \src "ls180.v:207.6-207.40"
-  wire \interface0_converted_interface_stb
-  attribute \src "ls180.v:209.6-209.39"
-  wire \interface0_converted_interface_we
-  attribute \src "ls180.v:223.5-223.39"
-  wire \interface1_converted_interface_ack
-  attribute \src "ls180.v:217.13-217.47"
-  wire width 30 \interface1_converted_interface_adr
-  attribute \src "ls180.v:226.12-226.46"
-  wire width 2 \interface1_converted_interface_bte
-  attribute \src "ls180.v:225.12-225.46"
-  wire width 3 \interface1_converted_interface_cti
-  attribute \src "ls180.v:221.6-221.40"
-  wire \interface1_converted_interface_cyc
-  attribute \src "ls180.v:219.13-219.49"
-  wire width 64 \interface1_converted_interface_dat_r
-  attribute \src "ls180.v:218.13-218.49"
-  wire width 64 \interface1_converted_interface_dat_w
-  attribute \src "ls180.v:227.5-227.39"
-  wire \interface1_converted_interface_err
-  attribute \src "ls180.v:220.12-220.46"
-  wire width 8 \interface1_converted_interface_sel
-  attribute \src "ls180.v:222.6-222.40"
-  wire \interface1_converted_interface_stb
-  attribute \src "ls180.v:224.6-224.39"
-  wire \interface1_converted_interface_we
-  attribute \src "ls180.v:868.6-868.9"
+  attribute \src "ls180.v:869.6-869.9"
   wire \irq
   attribute \src "ls180.v:39.13-39.21"
   wire input 35 \jtag_tck
@@ -244000,8 +243726,8 @@ module \ls180
   wire output 37 \jtag_tdo
   attribute \src "ls180.v:38.13-38.21"
   wire input 34 \jtag_tms
-  attribute \src "ls180.v:156.12-156.27"
-  wire width 6 \libresocsim_adr
+  attribute \src "ls180.v:199.12-199.27"
+  wire width 7 \libresocsim_adr
   attribute \src "ls180.v:52.6-52.27"
   wire \libresocsim_bus_error
   attribute \src "ls180.v:53.12-53.34"
@@ -244010,611 +243736,709 @@ module \ls180
   wire width 32 \libresocsim_bus_errors_status
   attribute \src "ls180.v:50.6-50.31"
   wire \libresocsim_bus_errors_we
-  attribute \src "ls180.v:1097.12-1097.29"
+  attribute \src "ls180.v:155.5-155.35"
+  wire \libresocsim_converter0_counter
+  attribute \src "ls180.v:1010.5-1010.70"
+  wire \libresocsim_converter0_counter_subfragments_converter0_next_value
+  attribute \src "ls180.v:1011.5-1011.73"
+  wire \libresocsim_converter0_counter_subfragments_converter0_next_value_ce
+  attribute \src "ls180.v:157.12-157.40"
+  wire width 64 \libresocsim_converter0_dat_r
+  attribute \src "ls180.v:156.6-156.34"
+  wire \libresocsim_converter0_reset
+  attribute \src "ls180.v:154.5-154.32"
+  wire \libresocsim_converter0_skip
+  attribute \src "ls180.v:170.5-170.35"
+  wire \libresocsim_converter1_counter
+  attribute \src "ls180.v:1014.5-1014.70"
+  wire \libresocsim_converter1_counter_subfragments_converter1_next_value
+  attribute \src "ls180.v:1015.5-1015.73"
+  wire \libresocsim_converter1_counter_subfragments_converter1_next_value_ce
+  attribute \src "ls180.v:172.12-172.40"
+  wire width 64 \libresocsim_converter1_dat_r
+  attribute \src "ls180.v:171.6-171.34"
+  wire \libresocsim_converter1_reset
+  attribute \src "ls180.v:169.5-169.32"
+  wire \libresocsim_converter1_skip
+  attribute \src "ls180.v:185.5-185.35"
+  wire \libresocsim_converter2_counter
+  attribute \src "ls180.v:1018.5-1018.70"
+  wire \libresocsim_converter2_counter_subfragments_converter2_next_value
+  attribute \src "ls180.v:1019.5-1019.73"
+  wire \libresocsim_converter2_counter_subfragments_converter2_next_value_ce
+  attribute \src "ls180.v:187.12-187.40"
+  wire width 64 \libresocsim_converter2_dat_r
+  attribute \src "ls180.v:186.6-186.34"
+  wire \libresocsim_converter2_reset
+  attribute \src "ls180.v:184.5-184.32"
+  wire \libresocsim_converter2_skip
+  attribute \src "ls180.v:1090.12-1090.29"
   wire width 20 \libresocsim_count
-  attribute \src "ls180.v:1338.13-1338.45"
+  attribute \src "ls180.v:1331.13-1331.45"
   wire width 14 \libresocsim_csr_interconnect_adr
-  attribute \src "ls180.v:1341.12-1341.46"
+  attribute \src "ls180.v:1334.12-1334.46"
   wire width 8 \libresocsim_csr_interconnect_dat_r
-  attribute \src "ls180.v:1340.12-1340.46"
+  attribute \src "ls180.v:1333.12-1333.46"
   wire width 8 \libresocsim_csr_interconnect_dat_w
-  attribute \src "ls180.v:1339.6-1339.37"
+  attribute \src "ls180.v:1332.6-1332.37"
   wire \libresocsim_csr_interconnect_we
-  attribute \src "ls180.v:1135.12-1135.46"
+  attribute \src "ls180.v:1128.12-1128.46"
   wire width 8 \libresocsim_csrbank0_bus_errors0_r
-  attribute \src "ls180.v:1134.6-1134.41"
+  attribute \src "ls180.v:1127.6-1127.41"
   wire \libresocsim_csrbank0_bus_errors0_re
-  attribute \src "ls180.v:1137.12-1137.46"
+  attribute \src "ls180.v:1130.12-1130.46"
   wire width 8 \libresocsim_csrbank0_bus_errors0_w
-  attribute \src "ls180.v:1136.6-1136.41"
+  attribute \src "ls180.v:1129.6-1129.41"
   wire \libresocsim_csrbank0_bus_errors0_we
-  attribute \src "ls180.v:1131.12-1131.46"
+  attribute \src "ls180.v:1124.12-1124.46"
   wire width 8 \libresocsim_csrbank0_bus_errors1_r
-  attribute \src "ls180.v:1130.6-1130.41"
+  attribute \src "ls180.v:1123.6-1123.41"
   wire \libresocsim_csrbank0_bus_errors1_re
-  attribute \src "ls180.v:1133.12-1133.46"
+  attribute \src "ls180.v:1126.12-1126.46"
   wire width 8 \libresocsim_csrbank0_bus_errors1_w
-  attribute \src "ls180.v:1132.6-1132.41"
+  attribute \src "ls180.v:1125.6-1125.41"
   wire \libresocsim_csrbank0_bus_errors1_we
-  attribute \src "ls180.v:1127.12-1127.46"
+  attribute \src "ls180.v:1120.12-1120.46"
   wire width 8 \libresocsim_csrbank0_bus_errors2_r
-  attribute \src "ls180.v:1126.6-1126.41"
+  attribute \src "ls180.v:1119.6-1119.41"
   wire \libresocsim_csrbank0_bus_errors2_re
-  attribute \src "ls180.v:1129.12-1129.46"
+  attribute \src "ls180.v:1122.12-1122.46"
   wire width 8 \libresocsim_csrbank0_bus_errors2_w
-  attribute \src "ls180.v:1128.6-1128.41"
+  attribute \src "ls180.v:1121.6-1121.41"
   wire \libresocsim_csrbank0_bus_errors2_we
-  attribute \src "ls180.v:1123.12-1123.46"
+  attribute \src "ls180.v:1116.12-1116.46"
   wire width 8 \libresocsim_csrbank0_bus_errors3_r
-  attribute \src "ls180.v:1122.6-1122.41"
+  attribute \src "ls180.v:1115.6-1115.41"
   wire \libresocsim_csrbank0_bus_errors3_re
-  attribute \src "ls180.v:1125.12-1125.46"
+  attribute \src "ls180.v:1118.12-1118.46"
   wire width 8 \libresocsim_csrbank0_bus_errors3_w
-  attribute \src "ls180.v:1124.6-1124.41"
+  attribute \src "ls180.v:1117.6-1117.41"
   wire \libresocsim_csrbank0_bus_errors3_we
-  attribute \src "ls180.v:1103.6-1103.35"
+  attribute \src "ls180.v:1096.6-1096.35"
   wire \libresocsim_csrbank0_reset0_r
-  attribute \src "ls180.v:1102.6-1102.36"
+  attribute \src "ls180.v:1095.6-1095.36"
   wire \libresocsim_csrbank0_reset0_re
-  attribute \src "ls180.v:1105.6-1105.35"
+  attribute \src "ls180.v:1098.6-1098.35"
   wire \libresocsim_csrbank0_reset0_w
-  attribute \src "ls180.v:1104.6-1104.36"
+  attribute \src "ls180.v:1097.6-1097.36"
   wire \libresocsim_csrbank0_reset0_we
-  attribute \src "ls180.v:1119.12-1119.43"
+  attribute \src "ls180.v:1112.12-1112.43"
   wire width 8 \libresocsim_csrbank0_scratch0_r
-  attribute \src "ls180.v:1118.6-1118.38"
+  attribute \src "ls180.v:1111.6-1111.38"
   wire \libresocsim_csrbank0_scratch0_re
-  attribute \src "ls180.v:1121.12-1121.43"
+  attribute \src "ls180.v:1114.12-1114.43"
   wire width 8 \libresocsim_csrbank0_scratch0_w
-  attribute \src "ls180.v:1120.6-1120.38"
+  attribute \src "ls180.v:1113.6-1113.38"
   wire \libresocsim_csrbank0_scratch0_we
-  attribute \src "ls180.v:1115.12-1115.43"
+  attribute \src "ls180.v:1108.12-1108.43"
   wire width 8 \libresocsim_csrbank0_scratch1_r
-  attribute \src "ls180.v:1114.6-1114.38"
+  attribute \src "ls180.v:1107.6-1107.38"
   wire \libresocsim_csrbank0_scratch1_re
-  attribute \src "ls180.v:1117.12-1117.43"
+  attribute \src "ls180.v:1110.12-1110.43"
   wire width 8 \libresocsim_csrbank0_scratch1_w
-  attribute \src "ls180.v:1116.6-1116.38"
+  attribute \src "ls180.v:1109.6-1109.38"
   wire \libresocsim_csrbank0_scratch1_we
-  attribute \src "ls180.v:1111.12-1111.43"
+  attribute \src "ls180.v:1104.12-1104.43"
   wire width 8 \libresocsim_csrbank0_scratch2_r
-  attribute \src "ls180.v:1110.6-1110.38"
+  attribute \src "ls180.v:1103.6-1103.38"
   wire \libresocsim_csrbank0_scratch2_re
-  attribute \src "ls180.v:1113.12-1113.43"
+  attribute \src "ls180.v:1106.12-1106.43"
   wire width 8 \libresocsim_csrbank0_scratch2_w
-  attribute \src "ls180.v:1112.6-1112.38"
+  attribute \src "ls180.v:1105.6-1105.38"
   wire \libresocsim_csrbank0_scratch2_we
-  attribute \src "ls180.v:1107.12-1107.43"
+  attribute \src "ls180.v:1100.12-1100.43"
   wire width 8 \libresocsim_csrbank0_scratch3_r
-  attribute \src "ls180.v:1106.6-1106.38"
+  attribute \src "ls180.v:1099.6-1099.38"
   wire \libresocsim_csrbank0_scratch3_re
-  attribute \src "ls180.v:1109.12-1109.43"
+  attribute \src "ls180.v:1102.12-1102.43"
   wire width 8 \libresocsim_csrbank0_scratch3_w
-  attribute \src "ls180.v:1108.6-1108.38"
+  attribute \src "ls180.v:1101.6-1101.38"
   wire \libresocsim_csrbank0_scratch3_we
-  attribute \src "ls180.v:1138.6-1138.30"
+  attribute \src "ls180.v:1131.6-1131.30"
   wire \libresocsim_csrbank0_sel
-  attribute \src "ls180.v:1148.12-1148.37"
+  attribute \src "ls180.v:1141.12-1141.37"
   wire width 8 \libresocsim_csrbank1_in_r
-  attribute \src "ls180.v:1147.6-1147.32"
+  attribute \src "ls180.v:1140.6-1140.32"
   wire \libresocsim_csrbank1_in_re
-  attribute \src "ls180.v:1150.12-1150.37"
+  attribute \src "ls180.v:1143.12-1143.37"
   wire width 8 \libresocsim_csrbank1_in_w
-  attribute \src "ls180.v:1149.6-1149.32"
+  attribute \src "ls180.v:1142.6-1142.32"
   wire \libresocsim_csrbank1_in_we
-  attribute \src "ls180.v:1144.12-1144.38"
+  attribute \src "ls180.v:1137.12-1137.38"
   wire width 8 \libresocsim_csrbank1_oe0_r
-  attribute \src "ls180.v:1143.6-1143.33"
+  attribute \src "ls180.v:1136.6-1136.33"
   wire \libresocsim_csrbank1_oe0_re
-  attribute \src "ls180.v:1146.12-1146.38"
+  attribute \src "ls180.v:1139.12-1139.38"
   wire width 8 \libresocsim_csrbank1_oe0_w
-  attribute \src "ls180.v:1145.6-1145.33"
+  attribute \src "ls180.v:1138.6-1138.33"
   wire \libresocsim_csrbank1_oe0_we
-  attribute \src "ls180.v:1152.12-1152.39"
+  attribute \src "ls180.v:1145.12-1145.39"
   wire width 8 \libresocsim_csrbank1_out0_r
-  attribute \src "ls180.v:1151.6-1151.34"
+  attribute \src "ls180.v:1144.6-1144.34"
   wire \libresocsim_csrbank1_out0_re
-  attribute \src "ls180.v:1154.12-1154.39"
+  attribute \src "ls180.v:1147.12-1147.39"
   wire width 8 \libresocsim_csrbank1_out0_w
-  attribute \src "ls180.v:1153.6-1153.34"
+  attribute \src "ls180.v:1146.6-1146.34"
   wire \libresocsim_csrbank1_out0_we
-  attribute \src "ls180.v:1155.6-1155.30"
+  attribute \src "ls180.v:1148.6-1148.30"
   wire \libresocsim_csrbank1_sel
-  attribute \src "ls180.v:1165.12-1165.37"
+  attribute \src "ls180.v:1158.12-1158.37"
   wire width 8 \libresocsim_csrbank2_in_r
-  attribute \src "ls180.v:1164.6-1164.32"
+  attribute \src "ls180.v:1157.6-1157.32"
   wire \libresocsim_csrbank2_in_re
-  attribute \src "ls180.v:1167.12-1167.37"
+  attribute \src "ls180.v:1160.12-1160.37"
   wire width 8 \libresocsim_csrbank2_in_w
-  attribute \src "ls180.v:1166.6-1166.32"
+  attribute \src "ls180.v:1159.6-1159.32"
   wire \libresocsim_csrbank2_in_we
-  attribute \src "ls180.v:1161.12-1161.38"
+  attribute \src "ls180.v:1154.12-1154.38"
   wire width 8 \libresocsim_csrbank2_oe0_r
-  attribute \src "ls180.v:1160.6-1160.33"
+  attribute \src "ls180.v:1153.6-1153.33"
   wire \libresocsim_csrbank2_oe0_re
-  attribute \src "ls180.v:1163.12-1163.38"
+  attribute \src "ls180.v:1156.12-1156.38"
   wire width 8 \libresocsim_csrbank2_oe0_w
-  attribute \src "ls180.v:1162.6-1162.33"
+  attribute \src "ls180.v:1155.6-1155.33"
   wire \libresocsim_csrbank2_oe0_we
-  attribute \src "ls180.v:1169.12-1169.39"
+  attribute \src "ls180.v:1162.12-1162.39"
   wire width 8 \libresocsim_csrbank2_out0_r
-  attribute \src "ls180.v:1168.6-1168.34"
+  attribute \src "ls180.v:1161.6-1161.34"
   wire \libresocsim_csrbank2_out0_re
-  attribute \src "ls180.v:1171.12-1171.39"
+  attribute \src "ls180.v:1164.12-1164.39"
   wire width 8 \libresocsim_csrbank2_out0_w
-  attribute \src "ls180.v:1170.6-1170.34"
+  attribute \src "ls180.v:1163.6-1163.34"
   wire \libresocsim_csrbank2_out0_we
-  attribute \src "ls180.v:1172.6-1172.30"
+  attribute \src "ls180.v:1165.6-1165.30"
   wire \libresocsim_csrbank2_sel
-  attribute \src "ls180.v:1182.6-1182.30"
+  attribute \src "ls180.v:1175.6-1175.30"
   wire \libresocsim_csrbank3_r_r
-  attribute \src "ls180.v:1181.6-1181.31"
+  attribute \src "ls180.v:1174.6-1174.31"
   wire \libresocsim_csrbank3_r_re
-  attribute \src "ls180.v:1184.6-1184.30"
+  attribute \src "ls180.v:1177.6-1177.30"
   wire \libresocsim_csrbank3_r_w
-  attribute \src "ls180.v:1183.6-1183.31"
+  attribute \src "ls180.v:1176.6-1176.31"
   wire \libresocsim_csrbank3_r_we
-  attribute \src "ls180.v:1185.6-1185.30"
+  attribute \src "ls180.v:1178.6-1178.30"
   wire \libresocsim_csrbank3_sel
-  attribute \src "ls180.v:1178.12-1178.37"
+  attribute \src "ls180.v:1171.12-1171.37"
   wire width 3 \libresocsim_csrbank3_w0_r
-  attribute \src "ls180.v:1177.6-1177.32"
+  attribute \src "ls180.v:1170.6-1170.32"
   wire \libresocsim_csrbank3_w0_re
-  attribute \src "ls180.v:1180.12-1180.37"
+  attribute \src "ls180.v:1173.12-1173.37"
   wire width 3 \libresocsim_csrbank3_w0_w
-  attribute \src "ls180.v:1179.6-1179.32"
+  attribute \src "ls180.v:1172.6-1172.32"
   wire \libresocsim_csrbank3_w0_we
-  attribute \src "ls180.v:1191.12-1191.48"
+  attribute \src "ls180.v:1184.12-1184.48"
   wire width 4 \libresocsim_csrbank4_dfii_control0_r
-  attribute \src "ls180.v:1190.6-1190.43"
+  attribute \src "ls180.v:1183.6-1183.43"
   wire \libresocsim_csrbank4_dfii_control0_re
-  attribute \src "ls180.v:1193.12-1193.48"
+  attribute \src "ls180.v:1186.12-1186.48"
   wire width 4 \libresocsim_csrbank4_dfii_control0_w
-  attribute \src "ls180.v:1192.6-1192.43"
+  attribute \src "ls180.v:1185.6-1185.43"
   wire \libresocsim_csrbank4_dfii_control0_we
-  attribute \src "ls180.v:1203.12-1203.52"
+  attribute \src "ls180.v:1196.12-1196.52"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r
-  attribute \src "ls180.v:1202.6-1202.47"
+  attribute \src "ls180.v:1195.6-1195.47"
   wire \libresocsim_csrbank4_dfii_pi0_address0_re
-  attribute \src "ls180.v:1205.12-1205.52"
+  attribute \src "ls180.v:1198.12-1198.52"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w
-  attribute \src "ls180.v:1204.6-1204.47"
+  attribute \src "ls180.v:1197.6-1197.47"
   wire \libresocsim_csrbank4_dfii_pi0_address0_we
-  attribute \src "ls180.v:1199.12-1199.52"
+  attribute \src "ls180.v:1192.12-1192.52"
   wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r
-  attribute \src "ls180.v:1198.6-1198.47"
+  attribute \src "ls180.v:1191.6-1191.47"
   wire \libresocsim_csrbank4_dfii_pi0_address1_re
-  attribute \src "ls180.v:1201.12-1201.52"
+  attribute \src "ls180.v:1194.12-1194.52"
   wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w
-  attribute \src "ls180.v:1200.6-1200.47"
+  attribute \src "ls180.v:1193.6-1193.47"
   wire \libresocsim_csrbank4_dfii_pi0_address1_we
-  attribute \src "ls180.v:1207.12-1207.53"
+  attribute \src "ls180.v:1200.12-1200.53"
   wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r
-  attribute \src "ls180.v:1206.6-1206.48"
+  attribute \src "ls180.v:1199.6-1199.48"
   wire \libresocsim_csrbank4_dfii_pi0_baddress0_re
-  attribute \src "ls180.v:1209.12-1209.53"
+  attribute \src "ls180.v:1202.12-1202.53"
   wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w
-  attribute \src "ls180.v:1208.6-1208.48"
+  attribute \src "ls180.v:1201.6-1201.48"
   wire \libresocsim_csrbank4_dfii_pi0_baddress0_we
-  attribute \src "ls180.v:1195.12-1195.52"
+  attribute \src "ls180.v:1188.12-1188.52"
   wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r
-  attribute \src "ls180.v:1194.6-1194.47"
+  attribute \src "ls180.v:1187.6-1187.47"
   wire \libresocsim_csrbank4_dfii_pi0_command0_re
-  attribute \src "ls180.v:1197.12-1197.52"
+  attribute \src "ls180.v:1190.12-1190.52"
   wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w
-  attribute \src "ls180.v:1196.6-1196.47"
+  attribute \src "ls180.v:1189.6-1189.47"
   wire \libresocsim_csrbank4_dfii_pi0_command0_we
-  attribute \src "ls180.v:1223.12-1223.51"
+  attribute \src "ls180.v:1216.12-1216.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r
-  attribute \src "ls180.v:1222.6-1222.46"
+  attribute \src "ls180.v:1215.6-1215.46"
   wire \libresocsim_csrbank4_dfii_pi0_rddata0_re
-  attribute \src "ls180.v:1225.12-1225.51"
+  attribute \src "ls180.v:1218.12-1218.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w
-  attribute \src "ls180.v:1224.6-1224.46"
+  attribute \src "ls180.v:1217.6-1217.46"
   wire \libresocsim_csrbank4_dfii_pi0_rddata0_we
-  attribute \src "ls180.v:1219.12-1219.51"
+  attribute \src "ls180.v:1212.12-1212.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r
-  attribute \src "ls180.v:1218.6-1218.46"
+  attribute \src "ls180.v:1211.6-1211.46"
   wire \libresocsim_csrbank4_dfii_pi0_rddata1_re
-  attribute \src "ls180.v:1221.12-1221.51"
+  attribute \src "ls180.v:1214.12-1214.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w
-  attribute \src "ls180.v:1220.6-1220.46"
+  attribute \src "ls180.v:1213.6-1213.46"
   wire \libresocsim_csrbank4_dfii_pi0_rddata1_we
-  attribute \src "ls180.v:1215.12-1215.51"
+  attribute \src "ls180.v:1208.12-1208.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r
-  attribute \src "ls180.v:1214.6-1214.46"
+  attribute \src "ls180.v:1207.6-1207.46"
   wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re
-  attribute \src "ls180.v:1217.12-1217.51"
+  attribute \src "ls180.v:1210.12-1210.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w
-  attribute \src "ls180.v:1216.6-1216.46"
+  attribute \src "ls180.v:1209.6-1209.46"
   wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we
-  attribute \src "ls180.v:1211.12-1211.51"
+  attribute \src "ls180.v:1204.12-1204.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r
-  attribute \src "ls180.v:1210.6-1210.46"
+  attribute \src "ls180.v:1203.6-1203.46"
   wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re
-  attribute \src "ls180.v:1213.12-1213.51"
+  attribute \src "ls180.v:1206.12-1206.51"
   wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w
-  attribute \src "ls180.v:1212.6-1212.46"
+  attribute \src "ls180.v:1205.6-1205.46"
   wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we
-  attribute \src "ls180.v:1226.6-1226.30"
+  attribute \src "ls180.v:1219.6-1219.30"
   wire \libresocsim_csrbank4_sel
-  attribute \src "ls180.v:1264.6-1264.32"
+  attribute \src "ls180.v:1257.6-1257.32"
   wire \libresocsim_csrbank5_en0_r
-  attribute \src "ls180.v:1263.6-1263.33"
+  attribute \src "ls180.v:1256.6-1256.33"
   wire \libresocsim_csrbank5_en0_re
-  attribute \src "ls180.v:1266.6-1266.32"
+  attribute \src "ls180.v:1259.6-1259.32"
   wire \libresocsim_csrbank5_en0_w
-  attribute \src "ls180.v:1265.6-1265.33"
+  attribute \src "ls180.v:1258.6-1258.33"
   wire \libresocsim_csrbank5_en0_we
-  attribute \src "ls180.v:1288.6-1288.39"
+  attribute \src "ls180.v:1281.6-1281.39"
   wire \libresocsim_csrbank5_ev_enable0_r
-  attribute \src "ls180.v:1287.6-1287.40"
+  attribute \src "ls180.v:1280.6-1280.40"
   wire \libresocsim_csrbank5_ev_enable0_re
-  attribute \src "ls180.v:1290.6-1290.39"
+  attribute \src "ls180.v:1283.6-1283.39"
   wire \libresocsim_csrbank5_ev_enable0_w
-  attribute \src "ls180.v:1289.6-1289.40"
+  attribute \src "ls180.v:1282.6-1282.40"
   wire \libresocsim_csrbank5_ev_enable0_we
-  attribute \src "ls180.v:1244.12-1244.40"
+  attribute \src "ls180.v:1237.12-1237.40"
   wire width 8 \libresocsim_csrbank5_load0_r
-  attribute \src "ls180.v:1243.6-1243.35"
+  attribute \src "ls180.v:1236.6-1236.35"
   wire \libresocsim_csrbank5_load0_re
-  attribute \src "ls180.v:1246.12-1246.40"
+  attribute \src "ls180.v:1239.12-1239.40"
   wire width 8 \libresocsim_csrbank5_load0_w
-  attribute \src "ls180.v:1245.6-1245.35"
+  attribute \src "ls180.v:1238.6-1238.35"
   wire \libresocsim_csrbank5_load0_we
-  attribute \src "ls180.v:1240.12-1240.40"
+  attribute \src "ls180.v:1233.12-1233.40"
   wire width 8 \libresocsim_csrbank5_load1_r
-  attribute \src "ls180.v:1239.6-1239.35"
+  attribute \src "ls180.v:1232.6-1232.35"
   wire \libresocsim_csrbank5_load1_re
-  attribute \src "ls180.v:1242.12-1242.40"
+  attribute \src "ls180.v:1235.12-1235.40"
   wire width 8 \libresocsim_csrbank5_load1_w
-  attribute \src "ls180.v:1241.6-1241.35"
+  attribute \src "ls180.v:1234.6-1234.35"
   wire \libresocsim_csrbank5_load1_we
-  attribute \src "ls180.v:1236.12-1236.40"
+  attribute \src "ls180.v:1229.12-1229.40"
   wire width 8 \libresocsim_csrbank5_load2_r
-  attribute \src "ls180.v:1235.6-1235.35"
+  attribute \src "ls180.v:1228.6-1228.35"
   wire \libresocsim_csrbank5_load2_re
-  attribute \src "ls180.v:1238.12-1238.40"
+  attribute \src "ls180.v:1231.12-1231.40"
   wire width 8 \libresocsim_csrbank5_load2_w
-  attribute \src "ls180.v:1237.6-1237.35"
+  attribute \src "ls180.v:1230.6-1230.35"
   wire \libresocsim_csrbank5_load2_we
-  attribute \src "ls180.v:1232.12-1232.40"
+  attribute \src "ls180.v:1225.12-1225.40"
   wire width 8 \libresocsim_csrbank5_load3_r
-  attribute \src "ls180.v:1231.6-1231.35"
+  attribute \src "ls180.v:1224.6-1224.35"
   wire \libresocsim_csrbank5_load3_re
-  attribute \src "ls180.v:1234.12-1234.40"
+  attribute \src "ls180.v:1227.12-1227.40"
   wire width 8 \libresocsim_csrbank5_load3_w
-  attribute \src "ls180.v:1233.6-1233.35"
+  attribute \src "ls180.v:1226.6-1226.35"
   wire \libresocsim_csrbank5_load3_we
-  attribute \src "ls180.v:1260.12-1260.42"
+  attribute \src "ls180.v:1253.12-1253.42"
   wire width 8 \libresocsim_csrbank5_reload0_r
-  attribute \src "ls180.v:1259.6-1259.37"
+  attribute \src "ls180.v:1252.6-1252.37"
   wire \libresocsim_csrbank5_reload0_re
-  attribute \src "ls180.v:1262.12-1262.42"
+  attribute \src "ls180.v:1255.12-1255.42"
   wire width 8 \libresocsim_csrbank5_reload0_w
-  attribute \src "ls180.v:1261.6-1261.37"
+  attribute \src "ls180.v:1254.6-1254.37"
   wire \libresocsim_csrbank5_reload0_we
-  attribute \src "ls180.v:1256.12-1256.42"
+  attribute \src "ls180.v:1249.12-1249.42"
   wire width 8 \libresocsim_csrbank5_reload1_r
-  attribute \src "ls180.v:1255.6-1255.37"
+  attribute \src "ls180.v:1248.6-1248.37"
   wire \libresocsim_csrbank5_reload1_re
-  attribute \src "ls180.v:1258.12-1258.42"
+  attribute \src "ls180.v:1251.12-1251.42"
   wire width 8 \libresocsim_csrbank5_reload1_w
-  attribute \src "ls180.v:1257.6-1257.37"
+  attribute \src "ls180.v:1250.6-1250.37"
   wire \libresocsim_csrbank5_reload1_we
-  attribute \src "ls180.v:1252.12-1252.42"
+  attribute \src "ls180.v:1245.12-1245.42"
   wire width 8 \libresocsim_csrbank5_reload2_r
-  attribute \src "ls180.v:1251.6-1251.37"
+  attribute \src "ls180.v:1244.6-1244.37"
   wire \libresocsim_csrbank5_reload2_re
-  attribute \src "ls180.v:1254.12-1254.42"
+  attribute \src "ls180.v:1247.12-1247.42"
   wire width 8 \libresocsim_csrbank5_reload2_w
-  attribute \src "ls180.v:1253.6-1253.37"
+  attribute \src "ls180.v:1246.6-1246.37"
   wire \libresocsim_csrbank5_reload2_we
-  attribute \src "ls180.v:1248.12-1248.42"
+  attribute \src "ls180.v:1241.12-1241.42"
   wire width 8 \libresocsim_csrbank5_reload3_r
-  attribute \src "ls180.v:1247.6-1247.37"
+  attribute \src "ls180.v:1240.6-1240.37"
   wire \libresocsim_csrbank5_reload3_re
-  attribute \src "ls180.v:1250.12-1250.42"
+  attribute \src "ls180.v:1243.12-1243.42"
   wire width 8 \libresocsim_csrbank5_reload3_w
-  attribute \src "ls180.v:1249.6-1249.37"
+  attribute \src "ls180.v:1242.6-1242.37"
   wire \libresocsim_csrbank5_reload3_we
-  attribute \src "ls180.v:1291.6-1291.30"
+  attribute \src "ls180.v:1284.6-1284.30"
   wire \libresocsim_csrbank5_sel
-  attribute \src "ls180.v:1268.6-1268.42"
+  attribute \src "ls180.v:1261.6-1261.42"
   wire \libresocsim_csrbank5_update_value0_r
-  attribute \src "ls180.v:1267.6-1267.43"
+  attribute \src "ls180.v:1260.6-1260.43"
   wire \libresocsim_csrbank5_update_value0_re
-  attribute \src "ls180.v:1270.6-1270.42"
+  attribute \src "ls180.v:1263.6-1263.42"
   wire \libresocsim_csrbank5_update_value0_w
-  attribute \src "ls180.v:1269.6-1269.43"
+  attribute \src "ls180.v:1262.6-1262.43"
   wire \libresocsim_csrbank5_update_value0_we
-  attribute \src "ls180.v:1284.12-1284.41"
+  attribute \src "ls180.v:1277.12-1277.41"
   wire width 8 \libresocsim_csrbank5_value0_r
-  attribute \src "ls180.v:1283.6-1283.36"
+  attribute \src "ls180.v:1276.6-1276.36"
   wire \libresocsim_csrbank5_value0_re
-  attribute \src "ls180.v:1286.12-1286.41"
+  attribute \src "ls180.v:1279.12-1279.41"
   wire width 8 \libresocsim_csrbank5_value0_w
-  attribute \src "ls180.v:1285.6-1285.36"
+  attribute \src "ls180.v:1278.6-1278.36"
   wire \libresocsim_csrbank5_value0_we
-  attribute \src "ls180.v:1280.12-1280.41"
+  attribute \src "ls180.v:1273.12-1273.41"
   wire width 8 \libresocsim_csrbank5_value1_r
-  attribute \src "ls180.v:1279.6-1279.36"
+  attribute \src "ls180.v:1272.6-1272.36"
   wire \libresocsim_csrbank5_value1_re
-  attribute \src "ls180.v:1282.12-1282.41"
+  attribute \src "ls180.v:1275.12-1275.41"
   wire width 8 \libresocsim_csrbank5_value1_w
-  attribute \src "ls180.v:1281.6-1281.36"
+  attribute \src "ls180.v:1274.6-1274.36"
   wire \libresocsim_csrbank5_value1_we
-  attribute \src "ls180.v:1276.12-1276.41"
+  attribute \src "ls180.v:1269.12-1269.41"
   wire width 8 \libresocsim_csrbank5_value2_r
-  attribute \src "ls180.v:1275.6-1275.36"
+  attribute \src "ls180.v:1268.6-1268.36"
   wire \libresocsim_csrbank5_value2_re
-  attribute \src "ls180.v:1278.12-1278.41"
+  attribute \src "ls180.v:1271.12-1271.41"
   wire width 8 \libresocsim_csrbank5_value2_w
-  attribute \src "ls180.v:1277.6-1277.36"
+  attribute \src "ls180.v:1270.6-1270.36"
   wire \libresocsim_csrbank5_value2_we
-  attribute \src "ls180.v:1272.12-1272.41"
+  attribute \src "ls180.v:1265.12-1265.41"
   wire width 8 \libresocsim_csrbank5_value3_r
-  attribute \src "ls180.v:1271.6-1271.36"
+  attribute \src "ls180.v:1264.6-1264.36"
   wire \libresocsim_csrbank5_value3_re
-  attribute \src "ls180.v:1274.12-1274.41"
+  attribute \src "ls180.v:1267.12-1267.41"
   wire width 8 \libresocsim_csrbank5_value3_w
-  attribute \src "ls180.v:1273.6-1273.36"
+  attribute \src "ls180.v:1266.6-1266.36"
   wire \libresocsim_csrbank5_value3_we
-  attribute \src "ls180.v:1305.12-1305.45"
+  attribute \src "ls180.v:1298.12-1298.45"
   wire width 2 \libresocsim_csrbank6_ev_enable0_r
-  attribute \src "ls180.v:1304.6-1304.40"
+  attribute \src "ls180.v:1297.6-1297.40"
   wire \libresocsim_csrbank6_ev_enable0_re
-  attribute \src "ls180.v:1307.12-1307.45"
+  attribute \src "ls180.v:1300.12-1300.45"
   wire width 2 \libresocsim_csrbank6_ev_enable0_w
-  attribute \src "ls180.v:1306.6-1306.40"
+  attribute \src "ls180.v:1299.6-1299.40"
   wire \libresocsim_csrbank6_ev_enable0_we
-  attribute \src "ls180.v:1301.6-1301.36"
+  attribute \src "ls180.v:1294.6-1294.36"
   wire \libresocsim_csrbank6_rxempty_r
-  attribute \src "ls180.v:1300.6-1300.37"
+  attribute \src "ls180.v:1293.6-1293.37"
   wire \libresocsim_csrbank6_rxempty_re
-  attribute \src "ls180.v:1303.6-1303.36"
+  attribute \src "ls180.v:1296.6-1296.36"
   wire \libresocsim_csrbank6_rxempty_w
-  attribute \src "ls180.v:1302.6-1302.37"
+  attribute \src "ls180.v:1295.6-1295.37"
   wire \libresocsim_csrbank6_rxempty_we
-  attribute \src "ls180.v:1313.6-1313.35"
+  attribute \src "ls180.v:1306.6-1306.35"
   wire \libresocsim_csrbank6_rxfull_r
-  attribute \src "ls180.v:1312.6-1312.36"
+  attribute \src "ls180.v:1305.6-1305.36"
   wire \libresocsim_csrbank6_rxfull_re
-  attribute \src "ls180.v:1315.6-1315.35"
+  attribute \src "ls180.v:1308.6-1308.35"
   wire \libresocsim_csrbank6_rxfull_w
-  attribute \src "ls180.v:1314.6-1314.36"
+  attribute \src "ls180.v:1307.6-1307.36"
   wire \libresocsim_csrbank6_rxfull_we
-  attribute \src "ls180.v:1316.6-1316.30"
+  attribute \src "ls180.v:1309.6-1309.30"
   wire \libresocsim_csrbank6_sel
-  attribute \src "ls180.v:1309.6-1309.36"
+  attribute \src "ls180.v:1302.6-1302.36"
   wire \libresocsim_csrbank6_txempty_r
-  attribute \src "ls180.v:1308.6-1308.37"
+  attribute \src "ls180.v:1301.6-1301.37"
   wire \libresocsim_csrbank6_txempty_re
-  attribute \src "ls180.v:1311.6-1311.36"
+  attribute \src "ls180.v:1304.6-1304.36"
   wire \libresocsim_csrbank6_txempty_w
-  attribute \src "ls180.v:1310.6-1310.37"
+  attribute \src "ls180.v:1303.6-1303.37"
   wire \libresocsim_csrbank6_txempty_we
-  attribute \src "ls180.v:1297.6-1297.35"
+  attribute \src "ls180.v:1290.6-1290.35"
   wire \libresocsim_csrbank6_txfull_r
-  attribute \src "ls180.v:1296.6-1296.36"
+  attribute \src "ls180.v:1289.6-1289.36"
   wire \libresocsim_csrbank6_txfull_re
-  attribute \src "ls180.v:1299.6-1299.35"
+  attribute \src "ls180.v:1292.6-1292.35"
   wire \libresocsim_csrbank6_txfull_w
-  attribute \src "ls180.v:1298.6-1298.36"
+  attribute \src "ls180.v:1291.6-1291.36"
   wire \libresocsim_csrbank6_txfull_we
-  attribute \src "ls180.v:1337.6-1337.30"
+  attribute \src "ls180.v:1330.6-1330.30"
   wire \libresocsim_csrbank7_sel
-  attribute \src "ls180.v:1334.12-1334.47"
+  attribute \src "ls180.v:1327.12-1327.47"
   wire width 8 \libresocsim_csrbank7_tuning_word0_r
-  attribute \src "ls180.v:1333.6-1333.42"
+  attribute \src "ls180.v:1326.6-1326.42"
   wire \libresocsim_csrbank7_tuning_word0_re
-  attribute \src "ls180.v:1336.12-1336.47"
+  attribute \src "ls180.v:1329.12-1329.47"
   wire width 8 \libresocsim_csrbank7_tuning_word0_w
-  attribute \src "ls180.v:1335.6-1335.42"
+  attribute \src "ls180.v:1328.6-1328.42"
   wire \libresocsim_csrbank7_tuning_word0_we
-  attribute \src "ls180.v:1330.12-1330.47"
+  attribute \src "ls180.v:1323.12-1323.47"
   wire width 8 \libresocsim_csrbank7_tuning_word1_r
-  attribute \src "ls180.v:1329.6-1329.42"
+  attribute \src "ls180.v:1322.6-1322.42"
   wire \libresocsim_csrbank7_tuning_word1_re
-  attribute \src "ls180.v:1332.12-1332.47"
+  attribute \src "ls180.v:1325.12-1325.47"
   wire width 8 \libresocsim_csrbank7_tuning_word1_w
-  attribute \src "ls180.v:1331.6-1331.42"
+  attribute \src "ls180.v:1324.6-1324.42"
   wire \libresocsim_csrbank7_tuning_word1_we
-  attribute \src "ls180.v:1326.12-1326.47"
+  attribute \src "ls180.v:1319.12-1319.47"
   wire width 8 \libresocsim_csrbank7_tuning_word2_r
-  attribute \src "ls180.v:1325.6-1325.42"
+  attribute \src "ls180.v:1318.6-1318.42"
   wire \libresocsim_csrbank7_tuning_word2_re
-  attribute \src "ls180.v:1328.12-1328.47"
+  attribute \src "ls180.v:1321.12-1321.47"
   wire width 8 \libresocsim_csrbank7_tuning_word2_w
-  attribute \src "ls180.v:1327.6-1327.42"
+  attribute \src "ls180.v:1320.6-1320.42"
   wire \libresocsim_csrbank7_tuning_word2_we
-  attribute \src "ls180.v:1322.12-1322.47"
+  attribute \src "ls180.v:1315.12-1315.47"
   wire width 8 \libresocsim_csrbank7_tuning_word3_r
-  attribute \src "ls180.v:1321.6-1321.42"
+  attribute \src "ls180.v:1314.6-1314.42"
   wire \libresocsim_csrbank7_tuning_word3_re
-  attribute \src "ls180.v:1324.12-1324.47"
+  attribute \src "ls180.v:1317.12-1317.47"
   wire width 8 \libresocsim_csrbank7_tuning_word3_w
-  attribute \src "ls180.v:1323.6-1323.42"
+  attribute \src "ls180.v:1316.6-1316.42"
   wire \libresocsim_csrbank7_tuning_word3_we
-  attribute \src "ls180.v:157.13-157.30"
-  wire width 64 \libresocsim_dat_r
-  attribute \src "ls180.v:159.13-159.30"
-  wire width 64 \libresocsim_dat_w
-  attribute \src "ls180.v:1096.6-1096.22"
+  attribute \src "ls180.v:200.13-200.30"
+  wire width 32 \libresocsim_dat_r
+  attribute \src "ls180.v:202.13-202.30"
+  wire width 32 \libresocsim_dat_w
+  attribute \src "ls180.v:1089.6-1089.22"
   wire \libresocsim_done
-  attribute \src "ls180.v:165.5-165.22"
+  attribute \src "ls180.v:208.5-208.22"
   wire \libresocsim_en_re
-  attribute \src "ls180.v:164.5-164.27"
+  attribute \src "ls180.v:207.5-207.27"
   wire \libresocsim_en_storage
-  attribute \src "ls180.v:1094.5-1094.22"
+  attribute \src "ls180.v:1087.5-1087.22"
   wire \libresocsim_error
-  attribute \src "ls180.v:181.6-181.40"
+  attribute \src "ls180.v:224.6-224.40"
   wire \libresocsim_eventmanager_pending_r
-  attribute \src "ls180.v:180.6-180.41"
+  attribute \src "ls180.v:223.6-223.41"
   wire \libresocsim_eventmanager_pending_re
-  attribute \src "ls180.v:183.6-183.40"
+  attribute \src "ls180.v:226.6-226.40"
   wire \libresocsim_eventmanager_pending_w
-  attribute \src "ls180.v:182.6-182.41"
+  attribute \src "ls180.v:225.6-225.41"
   wire \libresocsim_eventmanager_pending_we
-  attribute \src "ls180.v:185.5-185.32"
+  attribute \src "ls180.v:228.5-228.32"
   wire \libresocsim_eventmanager_re
-  attribute \src "ls180.v:177.6-177.39"
+  attribute \src "ls180.v:220.6-220.39"
   wire \libresocsim_eventmanager_status_r
-  attribute \src "ls180.v:176.6-176.40"
+  attribute \src "ls180.v:219.6-219.40"
   wire \libresocsim_eventmanager_status_re
-  attribute \src "ls180.v:179.6-179.39"
+  attribute \src "ls180.v:222.6-222.39"
   wire \libresocsim_eventmanager_status_w
-  attribute \src "ls180.v:178.6-178.40"
+  attribute \src "ls180.v:221.6-221.40"
   wire \libresocsim_eventmanager_status_we
-  attribute \src "ls180.v:184.5-184.37"
+  attribute \src "ls180.v:227.5-227.37"
   wire \libresocsim_eventmanager_storage
-  attribute \src "ls180.v:1091.11-1091.28"
+  attribute \src "ls180.v:1084.11-1084.28"
   wire width 2 \libresocsim_grant
-  attribute \src "ls180.v:1098.13-1098.48"
+  attribute \src "ls180.v:1091.13-1091.48"
   wire width 14 \libresocsim_interface0_bank_bus_adr
-  attribute \src "ls180.v:1101.11-1101.48"
+  attribute \src "ls180.v:1094.11-1094.48"
   wire width 8 \libresocsim_interface0_bank_bus_dat_r
-  attribute \src "ls180.v:1100.12-1100.49"
+  attribute \src "ls180.v:1093.12-1093.49"
   wire width 8 \libresocsim_interface0_bank_bus_dat_w
-  attribute \src "ls180.v:1099.6-1099.40"
+  attribute \src "ls180.v:1092.6-1092.40"
   wire \libresocsim_interface0_bank_bus_we
-  attribute \src "ls180.v:1139.13-1139.48"
+  attribute \src "ls180.v:149.6-149.52"
+  wire \libresocsim_interface0_converted_interface_ack
+  attribute \src "ls180.v:143.12-143.58"
+  wire width 30 \libresocsim_interface0_converted_interface_adr
+  attribute \src "ls180.v:152.11-152.57"
+  wire width 2 \libresocsim_interface0_converted_interface_bte
+  attribute \src "ls180.v:151.11-151.57"
+  wire width 3 \libresocsim_interface0_converted_interface_cti
+  attribute \src "ls180.v:147.5-147.51"
+  wire \libresocsim_interface0_converted_interface_cyc
+  attribute \src "ls180.v:145.13-145.61"
+  wire width 32 \libresocsim_interface0_converted_interface_dat_r
+  attribute \src "ls180.v:144.12-144.60"
+  wire width 32 \libresocsim_interface0_converted_interface_dat_w
+  attribute \src "ls180.v:153.6-153.52"
+  wire \libresocsim_interface0_converted_interface_err
+  attribute \src "ls180.v:146.11-146.57"
+  wire width 4 \libresocsim_interface0_converted_interface_sel
+  attribute \src "ls180.v:148.5-148.51"
+  wire \libresocsim_interface0_converted_interface_stb
+  attribute \src "ls180.v:150.5-150.50"
+  wire \libresocsim_interface0_converted_interface_we
+  attribute \src "ls180.v:1132.13-1132.48"
   wire width 14 \libresocsim_interface1_bank_bus_adr
-  attribute \src "ls180.v:1142.11-1142.48"
+  attribute \src "ls180.v:1135.11-1135.48"
   wire width 8 \libresocsim_interface1_bank_bus_dat_r
-  attribute \src "ls180.v:1141.12-1141.49"
+  attribute \src "ls180.v:1134.12-1134.49"
   wire width 8 \libresocsim_interface1_bank_bus_dat_w
-  attribute \src "ls180.v:1140.6-1140.40"
+  attribute \src "ls180.v:1133.6-1133.40"
   wire \libresocsim_interface1_bank_bus_we
-  attribute \src "ls180.v:1156.13-1156.48"
+  attribute \src "ls180.v:164.6-164.52"
+  wire \libresocsim_interface1_converted_interface_ack
+  attribute \src "ls180.v:158.12-158.58"
+  wire width 30 \libresocsim_interface1_converted_interface_adr
+  attribute \src "ls180.v:167.11-167.57"
+  wire width 2 \libresocsim_interface1_converted_interface_bte
+  attribute \src "ls180.v:166.11-166.57"
+  wire width 3 \libresocsim_interface1_converted_interface_cti
+  attribute \src "ls180.v:162.5-162.51"
+  wire \libresocsim_interface1_converted_interface_cyc
+  attribute \src "ls180.v:160.13-160.61"
+  wire width 32 \libresocsim_interface1_converted_interface_dat_r
+  attribute \src "ls180.v:159.12-159.60"
+  wire width 32 \libresocsim_interface1_converted_interface_dat_w
+  attribute \src "ls180.v:168.6-168.52"
+  wire \libresocsim_interface1_converted_interface_err
+  attribute \src "ls180.v:161.11-161.57"
+  wire width 4 \libresocsim_interface1_converted_interface_sel
+  attribute \src "ls180.v:163.5-163.51"
+  wire \libresocsim_interface1_converted_interface_stb
+  attribute \src "ls180.v:165.5-165.50"
+  wire \libresocsim_interface1_converted_interface_we
+  attribute \src "ls180.v:1149.13-1149.48"
   wire width 14 \libresocsim_interface2_bank_bus_adr
-  attribute \src "ls180.v:1159.11-1159.48"
+  attribute \src "ls180.v:1152.11-1152.48"
   wire width 8 \libresocsim_interface2_bank_bus_dat_r
-  attribute \src "ls180.v:1158.12-1158.49"
+  attribute \src "ls180.v:1151.12-1151.49"
   wire width 8 \libresocsim_interface2_bank_bus_dat_w
-  attribute \src "ls180.v:1157.6-1157.40"
+  attribute \src "ls180.v:1150.6-1150.40"
   wire \libresocsim_interface2_bank_bus_we
-  attribute \src "ls180.v:1173.13-1173.48"
+  attribute \src "ls180.v:179.6-179.52"
+  wire \libresocsim_interface2_converted_interface_ack
+  attribute \src "ls180.v:173.12-173.58"
+  wire width 30 \libresocsim_interface2_converted_interface_adr
+  attribute \src "ls180.v:182.11-182.57"
+  wire width 2 \libresocsim_interface2_converted_interface_bte
+  attribute \src "ls180.v:181.11-181.57"
+  wire width 3 \libresocsim_interface2_converted_interface_cti
+  attribute \src "ls180.v:177.5-177.51"
+  wire \libresocsim_interface2_converted_interface_cyc
+  attribute \src "ls180.v:175.13-175.61"
+  wire width 32 \libresocsim_interface2_converted_interface_dat_r
+  attribute \src "ls180.v:174.12-174.60"
+  wire width 32 \libresocsim_interface2_converted_interface_dat_w
+  attribute \src "ls180.v:183.6-183.52"
+  wire \libresocsim_interface2_converted_interface_err
+  attribute \src "ls180.v:176.11-176.57"
+  wire width 4 \libresocsim_interface2_converted_interface_sel
+  attribute \src "ls180.v:178.5-178.51"
+  wire \libresocsim_interface2_converted_interface_stb
+  attribute \src "ls180.v:180.5-180.50"
+  wire \libresocsim_interface2_converted_interface_we
+  attribute \src "ls180.v:1166.13-1166.48"
   wire width 14 \libresocsim_interface3_bank_bus_adr
-  attribute \src "ls180.v:1176.11-1176.48"
+  attribute \src "ls180.v:1169.11-1169.48"
   wire width 8 \libresocsim_interface3_bank_bus_dat_r
-  attribute \src "ls180.v:1175.12-1175.49"
+  attribute \src "ls180.v:1168.12-1168.49"
   wire width 8 \libresocsim_interface3_bank_bus_dat_w
-  attribute \src "ls180.v:1174.6-1174.40"
+  attribute \src "ls180.v:1167.6-1167.40"
   wire \libresocsim_interface3_bank_bus_we
-  attribute \src "ls180.v:1186.13-1186.48"
+  attribute \src "ls180.v:1179.13-1179.48"
   wire width 14 \libresocsim_interface4_bank_bus_adr
-  attribute \src "ls180.v:1189.11-1189.48"
+  attribute \src "ls180.v:1182.11-1182.48"
   wire width 8 \libresocsim_interface4_bank_bus_dat_r
-  attribute \src "ls180.v:1188.12-1188.49"
+  attribute \src "ls180.v:1181.12-1181.49"
   wire width 8 \libresocsim_interface4_bank_bus_dat_w
-  attribute \src "ls180.v:1187.6-1187.40"
+  attribute \src "ls180.v:1180.6-1180.40"
   wire \libresocsim_interface4_bank_bus_we
-  attribute \src "ls180.v:1227.13-1227.48"
+  attribute \src "ls180.v:1220.13-1220.48"
   wire width 14 \libresocsim_interface5_bank_bus_adr
-  attribute \src "ls180.v:1230.11-1230.48"
+  attribute \src "ls180.v:1223.11-1223.48"
   wire width 8 \libresocsim_interface5_bank_bus_dat_r
-  attribute \src "ls180.v:1229.12-1229.49"
+  attribute \src "ls180.v:1222.12-1222.49"
   wire width 8 \libresocsim_interface5_bank_bus_dat_w
-  attribute \src "ls180.v:1228.6-1228.40"
+  attribute \src "ls180.v:1221.6-1221.40"
   wire \libresocsim_interface5_bank_bus_we
-  attribute \src "ls180.v:1292.13-1292.48"
+  attribute \src "ls180.v:1285.13-1285.48"
   wire width 14 \libresocsim_interface6_bank_bus_adr
-  attribute \src "ls180.v:1295.11-1295.48"
+  attribute \src "ls180.v:1288.11-1288.48"
   wire width 8 \libresocsim_interface6_bank_bus_dat_r
-  attribute \src "ls180.v:1294.12-1294.49"
+  attribute \src "ls180.v:1287.12-1287.49"
   wire width 8 \libresocsim_interface6_bank_bus_dat_w
-  attribute \src "ls180.v:1293.6-1293.40"
+  attribute \src "ls180.v:1286.6-1286.40"
   wire \libresocsim_interface6_bank_bus_we
-  attribute \src "ls180.v:1317.13-1317.48"
+  attribute \src "ls180.v:1310.13-1310.48"
   wire width 14 \libresocsim_interface7_bank_bus_adr
-  attribute \src "ls180.v:1320.11-1320.48"
+  attribute \src "ls180.v:1313.11-1313.48"
   wire width 8 \libresocsim_interface7_bank_bus_dat_r
-  attribute \src "ls180.v:1319.12-1319.49"
+  attribute \src "ls180.v:1312.12-1312.49"
   wire width 8 \libresocsim_interface7_bank_bus_dat_w
-  attribute \src "ls180.v:1318.6-1318.40"
+  attribute \src "ls180.v:1311.6-1311.40"
   wire \libresocsim_interface7_bank_bus_we
-  attribute \src "ls180.v:170.6-170.21"
+  attribute \src "ls180.v:213.6-213.21"
   wire \libresocsim_irq
-  attribute \src "ls180.v:111.6-111.27"
+  attribute \src "ls180.v:109.6-109.27"
   wire \libresocsim_libresoc0
-  attribute \src "ls180.v:112.6-112.27"
+  attribute \src "ls180.v:110.6-110.27"
   wire \libresocsim_libresoc1
-  attribute \src "ls180.v:113.13-113.34"
+  attribute \src "ls180.v:111.13-111.34"
   wire width 64 \libresocsim_libresoc2
-  attribute \src "ls180.v:115.12-115.40"
+  attribute \src "ls180.v:113.12-113.40"
   wire width 2 \libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:138.6-138.51"
+  attribute \src "ls180.v:117.6-117.51"
   wire \libresocsim_libresoc_constraintmanager_eint_0
-  attribute \src "ls180.v:139.6-139.51"
+  attribute \src "ls180.v:118.6-118.51"
   wire \libresocsim_libresoc_constraintmanager_eint_1
-  attribute \src "ls180.v:140.6-140.51"
+  attribute \src "ls180.v:119.6-119.51"
   wire \libresocsim_libresoc_constraintmanager_eint_2
-  attribute \src "ls180.v:117.13-117.58"
+  attribute \src "ls180.v:140.13-140.58"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i
-  attribute \src "ls180.v:118.12-118.57"
+  attribute \src "ls180.v:141.12-141.57"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o
-  attribute \src "ls180.v:119.12-119.58"
+  attribute \src "ls180.v:142.12-142.58"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe
-  attribute \src "ls180.v:141.6-141.52"
+  attribute \src "ls180.v:132.6-132.52"
   wire \libresocsim_libresoc_constraintmanager_i2c_scl
-  attribute \src "ls180.v:142.6-142.54"
+  attribute \src "ls180.v:133.6-133.54"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_i
-  attribute \src "ls180.v:143.6-143.54"
+  attribute \src "ls180.v:134.6-134.54"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_o
-  attribute \src "ls180.v:144.6-144.55"
+  attribute \src "ls180.v:135.6-135.55"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe
-  attribute \src "ls180.v:122.12-122.58"
+  attribute \src "ls180.v:120.12-120.58"
   wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a
-  attribute \src "ls180.v:131.11-131.58"
+  attribute \src "ls180.v:129.11-129.58"
   wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba
-  attribute \src "ls180.v:128.5-128.55"
+  attribute \src "ls180.v:126.5-126.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_cas_n
-  attribute \src "ls180.v:130.5-130.53"
+  attribute \src "ls180.v:128.5-128.53"
   wire \libresocsim_libresoc_constraintmanager_sdram_cke
-  attribute \src "ls180.v:133.5-133.55"
+  attribute \src "ls180.v:131.5-131.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_clock
-  attribute \src "ls180.v:129.5-129.54"
+  attribute \src "ls180.v:127.5-127.54"
   wire \libresocsim_libresoc_constraintmanager_sdram_cs_n
-  attribute \src "ls180.v:132.11-132.58"
+  attribute \src "ls180.v:130.11-130.58"
   wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm
-  attribute \src "ls180.v:123.13-123.62"
+  attribute \src "ls180.v:121.13-121.62"
   wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i
-  attribute \src "ls180.v:124.12-124.61"
+  attribute \src "ls180.v:122.12-122.61"
   wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o
-  attribute \src "ls180.v:125.5-125.55"
+  attribute \src "ls180.v:123.5-123.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe
-  attribute \src "ls180.v:127.5-127.55"
+  attribute \src "ls180.v:125.5-125.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_ras_n
-  attribute \src "ls180.v:126.5-126.54"
+  attribute \src "ls180.v:124.5-124.54"
   wire \libresocsim_libresoc_constraintmanager_sdram_we_n
-  attribute \src "ls180.v:134.5-134.57"
+  attribute \src "ls180.v:136.5-136.57"
   wire \libresocsim_libresoc_constraintmanager_spimaster_clk
-  attribute \src "ls180.v:136.5-136.58"
+  attribute \src "ls180.v:138.5-138.58"
   wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n
-  attribute \src "ls180.v:137.6-137.59"
+  attribute \src "ls180.v:139.6-139.59"
   wire \libresocsim_libresoc_constraintmanager_spimaster_miso
-  attribute \src "ls180.v:135.5-135.58"
+  attribute \src "ls180.v:137.5-137.58"
   wire \libresocsim_libresoc_constraintmanager_spimaster_mosi
-  attribute \src "ls180.v:121.5-121.51"
+  attribute \src "ls180.v:116.5-116.51"
   wire \libresocsim_libresoc_constraintmanager_uart_rx
-  attribute \src "ls180.v:120.5-120.51"
+  attribute \src "ls180.v:115.5-115.51"
   wire \libresocsim_libresoc_constraintmanager_uart_tx
-  attribute \src "ls180.v:62.6-62.35"
+  attribute \src "ls180.v:62.5-62.34"
   wire \libresocsim_libresoc_dbus_ack
   attribute \src "ls180.v:56.13-56.42"
   wire width 29 \libresocsim_libresoc_dbus_adr
-  attribute \src "ls180.v:65.11-65.40"
-  wire width 2 \libresocsim_libresoc_dbus_bte
-  attribute \src "ls180.v:64.11-64.40"
-  wire width 3 \libresocsim_libresoc_dbus_cti
   attribute \src "ls180.v:60.6-60.35"
   wire \libresocsim_libresoc_dbus_cyc
   attribute \src "ls180.v:58.13-58.44"
   wire width 64 \libresocsim_libresoc_dbus_dat_r
   attribute \src "ls180.v:57.13-57.44"
   wire width 64 \libresocsim_libresoc_dbus_dat_w
-  attribute \src "ls180.v:66.6-66.35"
+  attribute \src "ls180.v:64.5-64.34"
   wire \libresocsim_libresoc_dbus_err
   attribute \src "ls180.v:59.12-59.41"
   wire width 8 \libresocsim_libresoc_dbus_sel
@@ -244622,53 +244446,45 @@ module \ls180
   wire \libresocsim_libresoc_dbus_stb
   attribute \src "ls180.v:63.6-63.34"
   wire \libresocsim_libresoc_dbus_we
-  attribute \src "ls180.v:73.6-73.35"
+  attribute \src "ls180.v:71.5-71.34"
   wire \libresocsim_libresoc_ibus_ack
-  attribute \src "ls180.v:67.13-67.42"
+  attribute \src "ls180.v:65.13-65.42"
   wire width 29 \libresocsim_libresoc_ibus_adr
-  attribute \src "ls180.v:76.11-76.40"
-  wire width 2 \libresocsim_libresoc_ibus_bte
-  attribute \src "ls180.v:75.11-75.40"
-  wire width 3 \libresocsim_libresoc_ibus_cti
-  attribute \src "ls180.v:71.6-71.35"
+  attribute \src "ls180.v:69.6-69.35"
   wire \libresocsim_libresoc_ibus_cyc
-  attribute \src "ls180.v:69.13-69.44"
+  attribute \src "ls180.v:67.13-67.44"
   wire width 64 \libresocsim_libresoc_ibus_dat_r
-  attribute \src "ls180.v:68.13-68.44"
+  attribute \src "ls180.v:66.13-66.44"
   wire width 64 \libresocsim_libresoc_ibus_dat_w
-  attribute \src "ls180.v:77.6-77.35"
+  attribute \src "ls180.v:73.5-73.34"
   wire \libresocsim_libresoc_ibus_err
-  attribute \src "ls180.v:70.12-70.41"
+  attribute \src "ls180.v:68.12-68.41"
   wire width 8 \libresocsim_libresoc_ibus_sel
-  attribute \src "ls180.v:72.6-72.35"
+  attribute \src "ls180.v:70.6-70.35"
   wire \libresocsim_libresoc_ibus_stb
-  attribute \src "ls180.v:74.6-74.34"
+  attribute \src "ls180.v:72.6-72.34"
   wire \libresocsim_libresoc_ibus_we
   attribute \src "ls180.v:55.12-55.42"
   wire width 16 \libresocsim_libresoc_interrupt
-  attribute \src "ls180.v:107.6-107.35"
+  attribute \src "ls180.v:105.6-105.35"
   wire \libresocsim_libresoc_jtag_tck
-  attribute \src "ls180.v:109.6-109.35"
+  attribute \src "ls180.v:107.6-107.35"
   wire \libresocsim_libresoc_jtag_tdi
-  attribute \src "ls180.v:110.6-110.35"
-  wire \libresocsim_libresoc_jtag_tdo
   attribute \src "ls180.v:108.6-108.35"
+  wire \libresocsim_libresoc_jtag_tdo
+  attribute \src "ls180.v:106.6-106.35"
   wire \libresocsim_libresoc_jtag_tms
-  attribute \src "ls180.v:102.6-102.38"
+  attribute \src "ls180.v:102.5-102.37"
   wire \libresocsim_libresoc_jtag_wb_ack
   attribute \src "ls180.v:96.13-96.45"
   wire width 29 \libresocsim_libresoc_jtag_wb_adr
-  attribute \src "ls180.v:105.11-105.43"
-  wire width 2 \libresocsim_libresoc_jtag_wb_bte
-  attribute \src "ls180.v:104.11-104.43"
-  wire width 3 \libresocsim_libresoc_jtag_wb_cti
   attribute \src "ls180.v:100.6-100.38"
   wire \libresocsim_libresoc_jtag_wb_cyc
   attribute \src "ls180.v:98.13-98.47"
   wire width 64 \libresocsim_libresoc_jtag_wb_dat_r
   attribute \src "ls180.v:97.13-97.47"
   wire width 64 \libresocsim_libresoc_jtag_wb_dat_w
-  attribute \src "ls180.v:106.6-106.38"
+  attribute \src "ls180.v:104.5-104.37"
   wire \libresocsim_libresoc_jtag_wb_err
   attribute \src "ls180.v:99.12-99.44"
   wire width 8 \libresocsim_libresoc_jtag_wb_sel
@@ -244676,139 +244492,131 @@ module \ls180
   wire \libresocsim_libresoc_jtag_wb_stb
   attribute \src "ls180.v:103.6-103.37"
   wire \libresocsim_libresoc_jtag_wb_we
-  attribute \src "ls180.v:114.6-114.35"
+  attribute \src "ls180.v:112.6-112.35"
   wire \libresocsim_libresoc_pll_18_o
-  attribute \src "ls180.v:116.6-116.36"
+  attribute \src "ls180.v:114.6-114.36"
   wire \libresocsim_libresoc_pll_lck_o
   attribute \src "ls180.v:54.6-54.32"
   wire \libresocsim_libresoc_reset
-  attribute \src "ls180.v:84.6-84.39"
+  attribute \src "ls180.v:80.6-80.39"
   wire \libresocsim_libresoc_xics_icp_ack
-  attribute \src "ls180.v:78.12-78.45"
+  attribute \src "ls180.v:74.13-74.46"
   wire width 30 \libresocsim_libresoc_xics_icp_adr
-  attribute \src "ls180.v:82.5-82.38"
+  attribute \src "ls180.v:83.12-83.45"
+  wire width 2 \libresocsim_libresoc_xics_icp_bte
+  attribute \src "ls180.v:82.12-82.45"
+  wire width 3 \libresocsim_libresoc_xics_icp_cti
+  attribute \src "ls180.v:78.6-78.39"
   wire \libresocsim_libresoc_xics_icp_cyc
-  attribute \src "ls180.v:80.13-80.48"
+  attribute \src "ls180.v:76.13-76.48"
   wire width 32 \libresocsim_libresoc_xics_icp_dat_r
-  attribute \src "ls180.v:79.12-79.47"
+  attribute \src "ls180.v:75.13-75.48"
   wire width 32 \libresocsim_libresoc_xics_icp_dat_w
-  attribute \src "ls180.v:86.6-86.39"
+  attribute \src "ls180.v:84.6-84.39"
   wire \libresocsim_libresoc_xics_icp_err
-  attribute \src "ls180.v:81.11-81.44"
+  attribute \src "ls180.v:77.12-77.45"
   wire width 4 \libresocsim_libresoc_xics_icp_sel
-  attribute \src "ls180.v:83.5-83.38"
+  attribute \src "ls180.v:79.6-79.39"
   wire \libresocsim_libresoc_xics_icp_stb
-  attribute \src "ls180.v:85.5-85.37"
+  attribute \src "ls180.v:81.6-81.38"
   wire \libresocsim_libresoc_xics_icp_we
-  attribute \src "ls180.v:93.6-93.39"
+  attribute \src "ls180.v:91.6-91.39"
   wire \libresocsim_libresoc_xics_ics_ack
-  attribute \src "ls180.v:87.12-87.45"
+  attribute \src "ls180.v:85.13-85.46"
   wire width 30 \libresocsim_libresoc_xics_ics_adr
-  attribute \src "ls180.v:91.5-91.38"
+  attribute \src "ls180.v:94.12-94.45"
+  wire width 2 \libresocsim_libresoc_xics_ics_bte
+  attribute \src "ls180.v:93.12-93.45"
+  wire width 3 \libresocsim_libresoc_xics_ics_cti
+  attribute \src "ls180.v:89.6-89.39"
   wire \libresocsim_libresoc_xics_ics_cyc
-  attribute \src "ls180.v:89.13-89.48"
+  attribute \src "ls180.v:87.13-87.48"
   wire width 32 \libresocsim_libresoc_xics_ics_dat_r
-  attribute \src "ls180.v:88.12-88.47"
+  attribute \src "ls180.v:86.13-86.48"
   wire width 32 \libresocsim_libresoc_xics_ics_dat_w
   attribute \src "ls180.v:95.6-95.39"
   wire \libresocsim_libresoc_xics_ics_err
-  attribute \src "ls180.v:90.11-90.44"
+  attribute \src "ls180.v:88.12-88.45"
   wire width 4 \libresocsim_libresoc_xics_ics_sel
-  attribute \src "ls180.v:92.5-92.38"
+  attribute \src "ls180.v:90.6-90.39"
   wire \libresocsim_libresoc_xics_ics_stb
-  attribute \src "ls180.v:94.5-94.37"
+  attribute \src "ls180.v:92.6-92.38"
   wire \libresocsim_libresoc_xics_ics_we
-  attribute \src "ls180.v:1056.12-1056.39"
+  attribute \src "ls180.v:1057.12-1057.39"
   wire width 14 \libresocsim_libresocsim_adr
-  attribute \src "ls180.v:1346.12-1346.63"
+  attribute \src "ls180.v:1339.12-1339.63"
   wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1
-  attribute \src "ls180.v:1347.5-1347.59"
+  attribute \src "ls180.v:1340.5-1340.59"
   wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1
-  attribute \src "ls180.v:1074.5-1074.52"
-  wire \libresocsim_libresocsim_converted_interface_ack
-  attribute \src "ls180.v:1068.13-1068.60"
-  wire width 30 \libresocsim_libresocsim_converted_interface_adr
-  attribute \src "ls180.v:1077.12-1077.59"
-  wire width 2 \libresocsim_libresocsim_converted_interface_bte
-  attribute \src "ls180.v:1076.12-1076.59"
-  wire width 3 \libresocsim_libresocsim_converted_interface_cti
-  attribute \src "ls180.v:1072.6-1072.53"
-  wire \libresocsim_libresocsim_converted_interface_cyc
-  attribute \src "ls180.v:1070.12-1070.61"
-  wire width 64 \libresocsim_libresocsim_converted_interface_dat_r
-  attribute \src "ls180.v:1069.13-1069.62"
-  wire width 64 \libresocsim_libresocsim_converted_interface_dat_w
-  attribute \src "ls180.v:1078.5-1078.52"
-  wire \libresocsim_libresocsim_converted_interface_err
-  attribute \src "ls180.v:1071.12-1071.59"
-  wire width 8 \libresocsim_libresocsim_converted_interface_sel
-  attribute \src "ls180.v:1073.6-1073.53"
-  wire \libresocsim_libresocsim_converted_interface_stb
-  attribute \src "ls180.v:1075.6-1075.52"
-  wire \libresocsim_libresocsim_converted_interface_we
-  attribute \src "ls180.v:1059.12-1059.41"
+  attribute \src "ls180.v:1060.12-1060.41"
   wire width 8 \libresocsim_libresocsim_dat_r
-  attribute \src "ls180.v:1058.11-1058.40"
+  attribute \src "ls180.v:1059.11-1059.40"
   wire width 8 \libresocsim_libresocsim_dat_w
-  attribute \src "ls180.v:1344.11-1344.64"
+  attribute \src "ls180.v:1337.11-1337.64"
   wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0
-  attribute \src "ls180.v:1345.5-1345.61"
+  attribute \src "ls180.v:1338.5-1338.61"
   wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0
-  attribute \src "ls180.v:1057.5-1057.31"
+  attribute \src "ls180.v:1058.5-1058.31"
   wire \libresocsim_libresocsim_we
-  attribute \src "ls180.v:1348.5-1348.55"
+  attribute \src "ls180.v:1341.5-1341.55"
   wire \libresocsim_libresocsim_we_libresocsim_next_value2
-  attribute \src "ls180.v:1349.5-1349.58"
+  attribute \src "ls180.v:1342.5-1342.58"
   wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2
-  attribute \src "ls180.v:1066.5-1066.41"
+  attribute \src "ls180.v:1067.5-1067.41"
   wire \libresocsim_libresocsim_wishbone_ack
-  attribute \src "ls180.v:1060.12-1060.48"
+  attribute \src "ls180.v:1061.13-1061.49"
   wire width 30 \libresocsim_libresocsim_wishbone_adr
-  attribute \src "ls180.v:1064.5-1064.41"
+  attribute \src "ls180.v:1070.12-1070.48"
+  wire width 2 \libresocsim_libresocsim_wishbone_bte
+  attribute \src "ls180.v:1069.12-1069.48"
+  wire width 3 \libresocsim_libresocsim_wishbone_cti
+  attribute \src "ls180.v:1065.6-1065.42"
   wire \libresocsim_libresocsim_wishbone_cyc
-  attribute \src "ls180.v:1062.12-1062.50"
+  attribute \src "ls180.v:1063.12-1063.50"
   wire width 32 \libresocsim_libresocsim_wishbone_dat_r
-  attribute \src "ls180.v:1061.12-1061.50"
+  attribute \src "ls180.v:1062.13-1062.51"
   wire width 32 \libresocsim_libresocsim_wishbone_dat_w
-  attribute \src "ls180.v:1063.11-1063.47"
+  attribute \src "ls180.v:1071.5-1071.41"
+  wire \libresocsim_libresocsim_wishbone_err
+  attribute \src "ls180.v:1064.12-1064.48"
   wire width 4 \libresocsim_libresocsim_wishbone_sel
-  attribute \src "ls180.v:1065.5-1065.41"
+  attribute \src "ls180.v:1066.6-1066.42"
   wire \libresocsim_libresocsim_wishbone_stb
-  attribute \src "ls180.v:1067.5-1067.40"
+  attribute \src "ls180.v:1068.6-1068.41"
   wire \libresocsim_libresocsim_wishbone_we
-  attribute \src "ls180.v:161.5-161.24"
+  attribute \src "ls180.v:204.5-204.24"
   wire \libresocsim_load_re
-  attribute \src "ls180.v:160.12-160.36"
+  attribute \src "ls180.v:203.12-203.36"
   wire width 32 \libresocsim_load_storage
-  attribute \src "ls180.v:1343.11-1343.33"
+  attribute \src "ls180.v:1336.11-1336.33"
   wire width 2 \libresocsim_next_state
-  attribute \src "ls180.v:151.5-151.28"
+  attribute \src "ls180.v:194.5-194.28"
   wire \libresocsim_ram_bus_ack
-  attribute \src "ls180.v:145.13-145.36"
+  attribute \src "ls180.v:188.13-188.36"
   wire width 30 \libresocsim_ram_bus_adr
-  attribute \src "ls180.v:154.12-154.35"
+  attribute \src "ls180.v:197.12-197.35"
   wire width 2 \libresocsim_ram_bus_bte
-  attribute \src "ls180.v:153.12-153.35"
+  attribute \src "ls180.v:196.12-196.35"
   wire width 3 \libresocsim_ram_bus_cti
-  attribute \src "ls180.v:149.6-149.29"
+  attribute \src "ls180.v:192.6-192.29"
   wire \libresocsim_ram_bus_cyc
-  attribute \src "ls180.v:147.13-147.38"
-  wire width 64 \libresocsim_ram_bus_dat_r
-  attribute \src "ls180.v:146.13-146.38"
-  wire width 64 \libresocsim_ram_bus_dat_w
-  attribute \src "ls180.v:155.5-155.28"
+  attribute \src "ls180.v:190.13-190.38"
+  wire width 32 \libresocsim_ram_bus_dat_r
+  attribute \src "ls180.v:189.13-189.38"
+  wire width 32 \libresocsim_ram_bus_dat_w
+  attribute \src "ls180.v:198.5-198.28"
   wire \libresocsim_ram_bus_err
-  attribute \src "ls180.v:148.12-148.35"
-  wire width 8 \libresocsim_ram_bus_sel
-  attribute \src "ls180.v:150.6-150.29"
+  attribute \src "ls180.v:191.12-191.35"
+  wire width 4 \libresocsim_ram_bus_sel
+  attribute \src "ls180.v:193.6-193.29"
   wire \libresocsim_ram_bus_stb
-  attribute \src "ls180.v:152.6-152.28"
+  attribute \src "ls180.v:195.6-195.28"
   wire \libresocsim_ram_bus_we
-  attribute \src "ls180.v:163.5-163.26"
+  attribute \src "ls180.v:206.5-206.26"
   wire \libresocsim_reload_re
-  attribute \src "ls180.v:162.12-162.38"
+  attribute \src "ls180.v:205.12-205.38"
   wire width 32 \libresocsim_reload_storage
-  attribute \src "ls180.v:1090.12-1090.31"
+  attribute \src "ls180.v:1083.12-1083.31"
   wire width 3 \libresocsim_request
   attribute \src "ls180.v:51.6-51.23"
   wire \libresocsim_reset
@@ -244820,1157 +244628,1157 @@ module \ls180
   wire \libresocsim_scratch_re
   attribute \src "ls180.v:47.12-47.39"
   wire width 32 \libresocsim_scratch_storage
-  attribute \src "ls180.v:1085.5-1085.27"
+  attribute \src "ls180.v:1078.5-1078.27"
   wire \libresocsim_shared_ack
-  attribute \src "ls180.v:1079.13-1079.35"
+  attribute \src "ls180.v:1072.13-1072.35"
   wire width 30 \libresocsim_shared_adr
-  attribute \src "ls180.v:1088.12-1088.34"
+  attribute \src "ls180.v:1081.12-1081.34"
   wire width 2 \libresocsim_shared_bte
-  attribute \src "ls180.v:1087.12-1087.34"
+  attribute \src "ls180.v:1080.12-1080.34"
   wire width 3 \libresocsim_shared_cti
-  attribute \src "ls180.v:1083.6-1083.28"
+  attribute \src "ls180.v:1076.6-1076.28"
   wire \libresocsim_shared_cyc
-  attribute \src "ls180.v:1081.12-1081.36"
+  attribute \src "ls180.v:1074.12-1074.36"
   wire width 32 \libresocsim_shared_dat_r
-  attribute \src "ls180.v:1080.13-1080.37"
+  attribute \src "ls180.v:1073.13-1073.37"
   wire width 32 \libresocsim_shared_dat_w
-  attribute \src "ls180.v:1089.6-1089.28"
+  attribute \src "ls180.v:1082.6-1082.28"
   wire \libresocsim_shared_err
-  attribute \src "ls180.v:1082.12-1082.34"
+  attribute \src "ls180.v:1075.12-1075.34"
   wire width 4 \libresocsim_shared_sel
-  attribute \src "ls180.v:1084.6-1084.28"
+  attribute \src "ls180.v:1077.6-1077.28"
   wire \libresocsim_shared_stb
-  attribute \src "ls180.v:1086.6-1086.27"
+  attribute \src "ls180.v:1079.6-1079.27"
   wire \libresocsim_shared_we
-  attribute \src "ls180.v:1092.11-1092.32"
+  attribute \src "ls180.v:1085.11-1085.32"
   wire width 6 \libresocsim_slave_sel
-  attribute \src "ls180.v:1093.11-1093.34"
+  attribute \src "ls180.v:1086.11-1086.34"
   wire width 6 \libresocsim_slave_sel_r
-  attribute \src "ls180.v:1342.11-1342.28"
+  attribute \src "ls180.v:1335.11-1335.28"
   wire width 2 \libresocsim_state
-  attribute \src "ls180.v:167.5-167.32"
+  attribute \src "ls180.v:210.5-210.32"
   wire \libresocsim_update_value_re
-  attribute \src "ls180.v:166.5-166.37"
+  attribute \src "ls180.v:209.5-209.37"
   wire \libresocsim_update_value_storage
-  attribute \src "ls180.v:186.12-186.29"
+  attribute \src "ls180.v:229.12-229.29"
   wire width 32 \libresocsim_value
-  attribute \src "ls180.v:168.12-168.36"
+  attribute \src "ls180.v:211.12-211.36"
   wire width 32 \libresocsim_value_status
-  attribute \src "ls180.v:169.6-169.26"
+  attribute \src "ls180.v:212.6-212.26"
   wire \libresocsim_value_we
-  attribute \src "ls180.v:1095.6-1095.22"
+  attribute \src "ls180.v:1088.6-1088.22"
   wire \libresocsim_wait
-  attribute \src "ls180.v:158.11-158.25"
-  wire width 8 \libresocsim_we
-  attribute \src "ls180.v:174.5-174.27"
+  attribute \src "ls180.v:201.11-201.25"
+  wire width 4 \libresocsim_we
+  attribute \src "ls180.v:217.5-217.27"
   wire \libresocsim_zero_clear
-  attribute \src "ls180.v:175.5-175.33"
+  attribute \src "ls180.v:218.5-218.33"
   wire \libresocsim_zero_old_trigger
-  attribute \src "ls180.v:172.5-172.29"
+  attribute \src "ls180.v:215.5-215.29"
   wire \libresocsim_zero_pending
-  attribute \src "ls180.v:171.6-171.29"
+  attribute \src "ls180.v:214.6-214.29"
   wire \libresocsim_zero_status
-  attribute \src "ls180.v:173.6-173.30"
+  attribute \src "ls180.v:216.6-216.30"
   wire \libresocsim_zero_trigger
-  attribute \src "ls180.v:825.6-825.21"
+  attribute \src "ls180.v:826.6-826.21"
   wire \litedram_wb_ack
-  attribute \src "ls180.v:819.12-819.27"
+  attribute \src "ls180.v:820.12-820.27"
   wire width 30 \litedram_wb_adr
-  attribute \src "ls180.v:823.5-823.20"
+  attribute \src "ls180.v:824.5-824.20"
   wire \litedram_wb_cyc
-  attribute \src "ls180.v:821.13-821.30"
+  attribute \src "ls180.v:822.13-822.30"
   wire width 16 \litedram_wb_dat_r
-  attribute \src "ls180.v:820.12-820.29"
+  attribute \src "ls180.v:821.12-821.29"
   wire width 16 \litedram_wb_dat_w
-  attribute \src "ls180.v:822.11-822.26"
+  attribute \src "ls180.v:823.11-823.26"
   wire width 2 \litedram_wb_sel
-  attribute \src "ls180.v:824.5-824.20"
+  attribute \src "ls180.v:825.5-825.20"
   wire \litedram_wb_stb
-  attribute \src "ls180.v:826.5-826.19"
+  attribute \src "ls180.v:827.5-827.19"
   wire \litedram_wb_we
-  attribute \src "ls180.v:5509.11-5509.17"
-  wire width 6 \memadr
-  attribute \src "ls180.v:5537.11-5537.19"
-  wire width 4 \memadr_1
-  attribute \src "ls180.v:5565.12-5565.18"
+  attribute \src "ls180.v:5494.11-5494.17"
+  wire width 7 \memadr
+  attribute \src "ls180.v:5514.11-5514.19"
+  wire width 5 \memadr_1
+  attribute \src "ls180.v:5534.12-5534.18"
   wire width 25 \memdat
-  attribute \src "ls180.v:5579.12-5579.20"
+  attribute \src "ls180.v:5548.12-5548.20"
   wire width 25 \memdat_1
-  attribute \src "ls180.v:5593.12-5593.20"
+  attribute \src "ls180.v:5562.12-5562.20"
   wire width 25 \memdat_2
-  attribute \src "ls180.v:5607.12-5607.20"
+  attribute \src "ls180.v:5576.12-5576.20"
   wire width 25 \memdat_3
-  attribute \src "ls180.v:5621.11-5621.19"
+  attribute \src "ls180.v:5590.11-5590.19"
   wire width 10 \memdat_4
-  attribute \src "ls180.v:5622.11-5622.19"
+  attribute \src "ls180.v:5591.11-5591.19"
   wire width 10 \memdat_5
-  attribute \src "ls180.v:5638.11-5638.19"
+  attribute \src "ls180.v:5607.11-5607.19"
   wire width 10 \memdat_6
-  attribute \src "ls180.v:5639.11-5639.19"
+  attribute \src "ls180.v:5608.11-5608.19"
   wire width 10 \memdat_7
   attribute \src "ls180.v:42.20-42.22"
   wire width 36 input 38 \nc
-  attribute \src "ls180.v:997.13-997.17"
+  attribute \src "ls180.v:998.13-998.17"
   wire width 36 \nc_1
-  attribute \src "ls180.v:234.6-234.13"
+  attribute \src "ls180.v:247.6-247.13"
   wire \por_clk
-  attribute \src "ls180.v:786.6-786.19"
+  attribute \src "ls180.v:799.6-799.19"
   wire \port_cmd_last
-  attribute \src "ls180.v:788.13-788.34"
+  attribute \src "ls180.v:801.13-801.34"
   wire width 24 \port_cmd_payload_addr
-  attribute \src "ls180.v:787.6-787.25"
+  attribute \src "ls180.v:800.6-800.25"
   wire \port_cmd_payload_we
-  attribute \src "ls180.v:785.6-785.20"
+  attribute \src "ls180.v:798.6-798.20"
   wire \port_cmd_ready
-  attribute \src "ls180.v:784.6-784.20"
+  attribute \src "ls180.v:797.6-797.20"
   wire \port_cmd_valid
-  attribute \src "ls180.v:783.6-783.16"
+  attribute \src "ls180.v:796.6-796.16"
   wire \port_flush
-  attribute \src "ls180.v:795.13-795.36"
+  attribute \src "ls180.v:808.13-808.36"
   wire width 16 \port_rdata_payload_data
-  attribute \src "ls180.v:794.6-794.22"
+  attribute \src "ls180.v:807.6-807.22"
   wire \port_rdata_ready
-  attribute \src "ls180.v:793.6-793.22"
+  attribute \src "ls180.v:806.6-806.22"
   wire \port_rdata_valid
-  attribute \src "ls180.v:791.13-791.36"
+  attribute \src "ls180.v:804.13-804.36"
   wire width 16 \port_wdata_payload_data
-  attribute \src "ls180.v:792.12-792.33"
+  attribute \src "ls180.v:805.12-805.33"
   wire width 2 \port_wdata_payload_we
-  attribute \src "ls180.v:790.6-790.22"
+  attribute \src "ls180.v:803.6-803.22"
   wire \port_wdata_ready
-  attribute \src "ls180.v:789.6-789.22"
+  attribute \src "ls180.v:802.6-802.22"
   wire \port_wdata_valid
-  attribute \src "ls180.v:198.12-198.19"
-  wire width 4 \ram_adr
-  attribute \src "ls180.v:193.5-193.24"
+  attribute \src "ls180.v:241.12-241.19"
+  wire width 5 \ram_adr
+  attribute \src "ls180.v:236.5-236.24"
   wire \ram_bus_ram_bus_ack
-  attribute \src "ls180.v:187.13-187.32"
+  attribute \src "ls180.v:230.13-230.32"
   wire width 30 \ram_bus_ram_bus_adr
-  attribute \src "ls180.v:196.12-196.31"
+  attribute \src "ls180.v:239.12-239.31"
   wire width 2 \ram_bus_ram_bus_bte
-  attribute \src "ls180.v:195.12-195.31"
+  attribute \src "ls180.v:238.12-238.31"
   wire width 3 \ram_bus_ram_bus_cti
-  attribute \src "ls180.v:191.6-191.25"
+  attribute \src "ls180.v:234.6-234.25"
   wire \ram_bus_ram_bus_cyc
-  attribute \src "ls180.v:189.13-189.34"
-  wire width 64 \ram_bus_ram_bus_dat_r
-  attribute \src "ls180.v:188.13-188.34"
-  wire width 64 \ram_bus_ram_bus_dat_w
-  attribute \src "ls180.v:197.5-197.24"
+  attribute \src "ls180.v:232.13-232.34"
+  wire width 32 \ram_bus_ram_bus_dat_r
+  attribute \src "ls180.v:231.13-231.34"
+  wire width 32 \ram_bus_ram_bus_dat_w
+  attribute \src "ls180.v:240.5-240.24"
   wire \ram_bus_ram_bus_err
-  attribute \src "ls180.v:190.12-190.31"
-  wire width 8 \ram_bus_ram_bus_sel
-  attribute \src "ls180.v:192.6-192.25"
+  attribute \src "ls180.v:233.12-233.31"
+  wire width 4 \ram_bus_ram_bus_sel
+  attribute \src "ls180.v:235.6-235.25"
   wire \ram_bus_ram_bus_stb
-  attribute \src "ls180.v:194.6-194.24"
+  attribute \src "ls180.v:237.6-237.24"
   wire \ram_bus_ram_bus_we
-  attribute \src "ls180.v:199.13-199.22"
-  wire width 64 \ram_dat_r
-  attribute \src "ls180.v:201.13-201.22"
-  wire width 64 \ram_dat_w
-  attribute \src "ls180.v:200.11-200.17"
-  wire width 8 \ram_we
-  attribute \src "ls180.v:252.11-252.20"
+  attribute \src "ls180.v:242.13-242.22"
+  wire width 32 \ram_dat_r
+  attribute \src "ls180.v:244.13-244.22"
+  wire width 32 \ram_dat_w
+  attribute \src "ls180.v:243.11-243.17"
+  wire width 4 \ram_we
+  attribute \src "ls180.v:265.11-265.20"
   wire width 3 \rddata_en
   attribute \no_retiming "true"
-  attribute \src "ls180.v:1451.32-1451.37"
+  attribute \src "ls180.v:1444.32-1444.37"
   wire \regs0
   attribute \no_retiming "true"
-  attribute \src "ls180.v:1452.32-1452.37"
+  attribute \src "ls180.v:1445.32-1445.37"
   wire \regs1
-  attribute \src "ls180.v:977.5-977.10"
+  attribute \src "ls180.v:978.5-978.10"
   wire \reset
-  attribute \src "ls180.v:1350.5-1350.21"
+  attribute \src "ls180.v:1343.5-1343.21"
   wire \rhs_array_muxed0
-  attribute \src "ls180.v:1351.12-1351.28"
+  attribute \src "ls180.v:1344.12-1344.28"
   wire width 13 \rhs_array_muxed1
-  attribute \src "ls180.v:1363.5-1363.22"
+  attribute \src "ls180.v:1356.5-1356.22"
   wire \rhs_array_muxed10
-  attribute \src "ls180.v:1364.5-1364.22"
+  attribute \src "ls180.v:1357.5-1357.22"
   wire \rhs_array_muxed11
-  attribute \src "ls180.v:1368.12-1368.29"
+  attribute \src "ls180.v:1361.12-1361.29"
   wire width 22 \rhs_array_muxed12
-  attribute \src "ls180.v:1369.5-1369.22"
+  attribute \src "ls180.v:1362.5-1362.22"
   wire \rhs_array_muxed13
-  attribute \src "ls180.v:1370.5-1370.22"
+  attribute \src "ls180.v:1363.5-1363.22"
   wire \rhs_array_muxed14
-  attribute \src "ls180.v:1371.12-1371.29"
+  attribute \src "ls180.v:1364.12-1364.29"
   wire width 22 \rhs_array_muxed15
-  attribute \src "ls180.v:1372.5-1372.22"
+  attribute \src "ls180.v:1365.5-1365.22"
   wire \rhs_array_muxed16
-  attribute \src "ls180.v:1373.5-1373.22"
+  attribute \src "ls180.v:1366.5-1366.22"
   wire \rhs_array_muxed17
-  attribute \src "ls180.v:1374.12-1374.29"
+  attribute \src "ls180.v:1367.12-1367.29"
   wire width 22 \rhs_array_muxed18
-  attribute \src "ls180.v:1375.5-1375.22"
+  attribute \src "ls180.v:1368.5-1368.22"
   wire \rhs_array_muxed19
-  attribute \src "ls180.v:1352.11-1352.27"
+  attribute \src "ls180.v:1345.11-1345.27"
   wire width 2 \rhs_array_muxed2
-  attribute \src "ls180.v:1376.5-1376.22"
+  attribute \src "ls180.v:1369.5-1369.22"
   wire \rhs_array_muxed20
-  attribute \src "ls180.v:1377.12-1377.29"
+  attribute \src "ls180.v:1370.12-1370.29"
   wire width 22 \rhs_array_muxed21
-  attribute \src "ls180.v:1378.5-1378.22"
+  attribute \src "ls180.v:1371.5-1371.22"
   wire \rhs_array_muxed22
-  attribute \src "ls180.v:1379.5-1379.22"
+  attribute \src "ls180.v:1372.5-1372.22"
   wire \rhs_array_muxed23
-  attribute \src "ls180.v:1380.12-1380.29"
-  wire width 29 \rhs_array_muxed24
-  attribute \src "ls180.v:1381.12-1381.29"
-  wire width 64 \rhs_array_muxed25
-  attribute \src "ls180.v:1382.11-1382.28"
-  wire width 8 \rhs_array_muxed26
-  attribute \src "ls180.v:1383.5-1383.22"
+  attribute \src "ls180.v:1373.12-1373.29"
+  wire width 30 \rhs_array_muxed24
+  attribute \src "ls180.v:1374.12-1374.29"
+  wire width 32 \rhs_array_muxed25
+  attribute \src "ls180.v:1375.11-1375.28"
+  wire width 4 \rhs_array_muxed26
+  attribute \src "ls180.v:1376.5-1376.22"
   wire \rhs_array_muxed27
-  attribute \src "ls180.v:1384.5-1384.22"
+  attribute \src "ls180.v:1377.5-1377.22"
   wire \rhs_array_muxed28
-  attribute \src "ls180.v:1385.5-1385.22"
+  attribute \src "ls180.v:1378.5-1378.22"
   wire \rhs_array_muxed29
-  attribute \src "ls180.v:1353.5-1353.21"
+  attribute \src "ls180.v:1346.5-1346.21"
   wire \rhs_array_muxed3
-  attribute \src "ls180.v:1386.11-1386.28"
+  attribute \src "ls180.v:1379.11-1379.28"
   wire width 3 \rhs_array_muxed30
-  attribute \src "ls180.v:1387.11-1387.28"
+  attribute \src "ls180.v:1380.11-1380.28"
   wire width 2 \rhs_array_muxed31
-  attribute \src "ls180.v:1354.5-1354.21"
+  attribute \src "ls180.v:1347.5-1347.21"
   wire \rhs_array_muxed4
-  attribute \src "ls180.v:1355.5-1355.21"
+  attribute \src "ls180.v:1348.5-1348.21"
   wire \rhs_array_muxed5
-  attribute \src "ls180.v:1359.5-1359.21"
+  attribute \src "ls180.v:1352.5-1352.21"
   wire \rhs_array_muxed6
-  attribute \src "ls180.v:1360.12-1360.28"
+  attribute \src "ls180.v:1353.12-1353.28"
   wire width 13 \rhs_array_muxed7
-  attribute \src "ls180.v:1361.11-1361.27"
+  attribute \src "ls180.v:1354.11-1354.27"
   wire width 2 \rhs_array_muxed8
-  attribute \src "ls180.v:1362.5-1362.21"
+  attribute \src "ls180.v:1355.5-1355.21"
   wire \rhs_array_muxed9
-  attribute \src "ls180.v:877.5-877.13"
+  attribute \src "ls180.v:878.5-878.13"
   wire \rx_clear
-  attribute \src "ls180.v:961.11-961.26"
+  attribute \src "ls180.v:962.11-962.26"
   wire width 4 \rx_fifo_consume
-  attribute \src "ls180.v:966.6-966.21"
+  attribute \src "ls180.v:967.6-967.21"
   wire \rx_fifo_do_read
-  attribute \src "ls180.v:972.6-972.27"
+  attribute \src "ls180.v:973.6-973.27"
   wire \rx_fifo_fifo_in_first
-  attribute \src "ls180.v:973.6-973.26"
+  attribute \src "ls180.v:974.6-974.26"
   wire \rx_fifo_fifo_in_last
-  attribute \src "ls180.v:971.12-971.40"
+  attribute \src "ls180.v:972.12-972.40"
   wire width 8 \rx_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:975.6-975.28"
+  attribute \src "ls180.v:976.6-976.28"
   wire \rx_fifo_fifo_out_first
-  attribute \src "ls180.v:976.6-976.27"
+  attribute \src "ls180.v:977.6-977.27"
   wire \rx_fifo_fifo_out_last
-  attribute \src "ls180.v:974.12-974.41"
+  attribute \src "ls180.v:975.12-975.41"
   wire width 8 \rx_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:958.11-958.25"
+  attribute \src "ls180.v:959.11-959.25"
   wire width 5 \rx_fifo_level0
-  attribute \src "ls180.v:970.12-970.26"
+  attribute \src "ls180.v:971.12-971.26"
   wire width 5 \rx_fifo_level1
-  attribute \src "ls180.v:960.11-960.26"
+  attribute \src "ls180.v:961.11-961.26"
   wire width 4 \rx_fifo_produce
-  attribute \src "ls180.v:967.12-967.30"
+  attribute \src "ls180.v:968.12-968.30"
   wire width 4 \rx_fifo_rdport_adr
-  attribute \src "ls180.v:968.12-968.32"
+  attribute \src "ls180.v:969.12-969.32"
   wire width 10 \rx_fifo_rdport_dat_r
-  attribute \src "ls180.v:969.6-969.23"
+  attribute \src "ls180.v:970.6-970.23"
   wire \rx_fifo_rdport_re
-  attribute \src "ls180.v:950.6-950.16"
+  attribute \src "ls180.v:951.6-951.16"
   wire \rx_fifo_re
-  attribute \src "ls180.v:951.5-951.21"
+  attribute \src "ls180.v:952.5-952.21"
   wire \rx_fifo_readable
-  attribute \src "ls180.v:959.5-959.20"
+  attribute \src "ls180.v:960.5-960.20"
   wire \rx_fifo_replace
-  attribute \src "ls180.v:942.6-942.24"
+  attribute \src "ls180.v:943.6-943.24"
   wire \rx_fifo_sink_first
-  attribute \src "ls180.v:943.6-943.23"
+  attribute \src "ls180.v:944.6-944.23"
   wire \rx_fifo_sink_last
-  attribute \src "ls180.v:944.12-944.37"
+  attribute \src "ls180.v:945.12-945.37"
   wire width 8 \rx_fifo_sink_payload_data
-  attribute \src "ls180.v:941.6-941.24"
+  attribute \src "ls180.v:942.6-942.24"
   wire \rx_fifo_sink_ready
-  attribute \src "ls180.v:940.6-940.24"
+  attribute \src "ls180.v:941.6-941.24"
   wire \rx_fifo_sink_valid
-  attribute \src "ls180.v:947.6-947.26"
+  attribute \src "ls180.v:948.6-948.26"
   wire \rx_fifo_source_first
-  attribute \src "ls180.v:948.6-948.25"
+  attribute \src "ls180.v:949.6-949.25"
   wire \rx_fifo_source_last
-  attribute \src "ls180.v:949.12-949.39"
+  attribute \src "ls180.v:950.12-950.39"
   wire width 8 \rx_fifo_source_payload_data
-  attribute \src "ls180.v:946.6-946.26"
+  attribute \src "ls180.v:947.6-947.26"
   wire \rx_fifo_source_ready
-  attribute \src "ls180.v:945.6-945.26"
+  attribute \src "ls180.v:946.6-946.26"
   wire \rx_fifo_source_valid
-  attribute \src "ls180.v:956.12-956.32"
+  attribute \src "ls180.v:957.12-957.32"
   wire width 10 \rx_fifo_syncfifo_din
-  attribute \src "ls180.v:957.12-957.33"
+  attribute \src "ls180.v:958.12-958.33"
   wire width 10 \rx_fifo_syncfifo_dout
-  attribute \src "ls180.v:954.6-954.25"
+  attribute \src "ls180.v:955.6-955.25"
   wire \rx_fifo_syncfifo_re
-  attribute \src "ls180.v:955.6-955.31"
+  attribute \src "ls180.v:956.6-956.31"
   wire \rx_fifo_syncfifo_readable
-  attribute \src "ls180.v:952.6-952.25"
+  attribute \src "ls180.v:953.6-953.25"
   wire \rx_fifo_syncfifo_we
-  attribute \src "ls180.v:953.6-953.31"
+  attribute \src "ls180.v:954.6-954.31"
   wire \rx_fifo_syncfifo_writable
-  attribute \src "ls180.v:962.11-962.29"
+  attribute \src "ls180.v:963.11-963.29"
   wire width 4 \rx_fifo_wrport_adr
-  attribute \src "ls180.v:963.12-963.32"
+  attribute \src "ls180.v:964.12-964.32"
   wire width 10 \rx_fifo_wrport_dat_r
-  attribute \src "ls180.v:965.12-965.32"
+  attribute \src "ls180.v:966.12-966.32"
   wire width 10 \rx_fifo_wrport_dat_w
-  attribute \src "ls180.v:964.6-964.23"
+  attribute \src "ls180.v:965.6-965.23"
   wire \rx_fifo_wrport_we
-  attribute \src "ls180.v:878.5-878.19"
+  attribute \src "ls180.v:879.5-879.19"
   wire \rx_old_trigger
-  attribute \src "ls180.v:875.5-875.15"
+  attribute \src "ls180.v:876.5-876.15"
   wire \rx_pending
-  attribute \src "ls180.v:874.6-874.15"
+  attribute \src "ls180.v:875.6-875.15"
   wire \rx_status
-  attribute \src "ls180.v:876.6-876.16"
+  attribute \src "ls180.v:877.6-877.16"
   wire \rx_trigger
-  attribute \src "ls180.v:866.6-866.20"
+  attribute \src "ls180.v:867.6-867.20"
   wire \rxempty_status
-  attribute \src "ls180.v:867.6-867.16"
+  attribute \src "ls180.v:868.6-868.16"
   wire \rxempty_we
-  attribute \src "ls180.v:891.6-891.19"
+  attribute \src "ls180.v:892.6-892.19"
   wire \rxfull_status
-  attribute \src "ls180.v:892.6-892.15"
+  attribute \src "ls180.v:893.6-893.15"
   wire \rxfull_we
-  attribute \src "ls180.v:861.12-861.18"
+  attribute \src "ls180.v:862.12-862.18"
   wire width 8 \rxtx_r
-  attribute \src "ls180.v:860.6-860.13"
+  attribute \src "ls180.v:861.6-861.13"
   wire \rxtx_re
-  attribute \src "ls180.v:863.12-863.18"
+  attribute \src "ls180.v:864.12-864.18"
   wire width 8 \rxtx_w
-  attribute \src "ls180.v:862.6-862.13"
+  attribute \src "ls180.v:863.6-863.13"
   wire \rxtx_we
   attribute \src "ls180.v:10.21-10.28"
   wire width 13 output 6 \sdram_a
-  attribute \src "ls180.v:314.5-314.21"
+  attribute \src "ls180.v:327.5-327.21"
   wire \sdram_address_re
-  attribute \src "ls180.v:313.12-313.33"
+  attribute \src "ls180.v:326.12-326.33"
   wire width 13 \sdram_address_storage
   attribute \src "ls180.v:19.20-19.28"
   wire width 2 output 15 \sdram_ba
-  attribute \src "ls180.v:316.5-316.22"
+  attribute \src "ls180.v:329.5-329.22"
   wire \sdram_baddress_re
-  attribute \src "ls180.v:315.11-315.33"
+  attribute \src "ls180.v:328.11-328.33"
   wire width 2 \sdram_baddress_storage
-  attribute \src "ls180.v:412.5-412.38"
+  attribute \src "ls180.v:425.5-425.38"
   wire \sdram_bankmachine0_auto_precharge
-  attribute \src "ls180.v:434.11-434.58"
+  attribute \src "ls180.v:447.11-447.58"
   wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:439.6-439.53"
+  attribute \src "ls180.v:452.6-452.53"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:444.6-444.59"
+  attribute \src "ls180.v:457.6-457.59"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:445.6-445.58"
+  attribute \src "ls180.v:458.6-458.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:443.13-443.73"
+  attribute \src "ls180.v:456.13-456.73"
   wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:442.6-442.64"
+  attribute \src "ls180.v:455.6-455.64"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:448.6-448.60"
+  attribute \src "ls180.v:461.6-461.60"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:449.6-449.59"
+  attribute \src "ls180.v:462.6-462.59"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:447.13-447.74"
+  attribute \src "ls180.v:460.13-460.74"
   wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:446.6-446.65"
+  attribute \src "ls180.v:459.6-459.65"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:431.11-431.56"
+  attribute \src "ls180.v:444.11-444.56"
   wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:433.11-433.58"
+  attribute \src "ls180.v:446.11-446.58"
   wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:440.12-440.62"
+  attribute \src "ls180.v:453.12-453.62"
   wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:441.13-441.65"
+  attribute \src "ls180.v:454.13-454.65"
   wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:432.5-432.52"
+  attribute \src "ls180.v:445.5-445.52"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:415.5-415.55"
+  attribute \src "ls180.v:428.5-428.55"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:416.5-416.54"
+  attribute \src "ls180.v:429.5-429.54"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:418.13-418.70"
+  attribute \src "ls180.v:431.13-431.70"
   wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:417.6-417.61"
+  attribute \src "ls180.v:430.6-430.61"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:414.6-414.56"
+  attribute \src "ls180.v:427.6-427.56"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:413.6-413.56"
+  attribute \src "ls180.v:426.6-426.56"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:421.6-421.58"
+  attribute \src "ls180.v:434.6-434.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:422.6-422.57"
+  attribute \src "ls180.v:435.6-435.57"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:424.13-424.72"
+  attribute \src "ls180.v:437.13-437.72"
   wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:423.6-423.63"
+  attribute \src "ls180.v:436.6-436.63"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:420.6-420.58"
+  attribute \src "ls180.v:433.6-433.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:419.6-419.58"
+  attribute \src "ls180.v:432.6-432.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:429.13-429.66"
+  attribute \src "ls180.v:442.13-442.66"
   wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
-  attribute \src "ls180.v:430.13-430.67"
+  attribute \src "ls180.v:443.13-443.67"
   wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
-  attribute \src "ls180.v:427.6-427.58"
+  attribute \src "ls180.v:440.6-440.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
-  attribute \src "ls180.v:428.6-428.64"
+  attribute \src "ls180.v:441.6-441.64"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
-  attribute \src "ls180.v:425.6-425.58"
+  attribute \src "ls180.v:438.6-438.58"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
-  attribute \src "ls180.v:426.6-426.64"
+  attribute \src "ls180.v:439.6-439.64"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-  attribute \src "ls180.v:435.11-435.61"
+  attribute \src "ls180.v:448.11-448.61"
   wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:436.13-436.65"
+  attribute \src "ls180.v:449.13-449.65"
   wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:438.13-438.65"
+  attribute \src "ls180.v:451.13-451.65"
   wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:437.6-437.55"
+  attribute \src "ls180.v:450.6-450.55"
   wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:452.6-452.46"
+  attribute \src "ls180.v:465.6-465.46"
   wire \sdram_bankmachine0_cmd_buffer_sink_first
-  attribute \src "ls180.v:453.6-453.45"
+  attribute \src "ls180.v:466.6-466.45"
   wire \sdram_bankmachine0_cmd_buffer_sink_last
-  attribute \src "ls180.v:455.13-455.60"
+  attribute \src "ls180.v:468.13-468.60"
   wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:454.6-454.51"
+  attribute \src "ls180.v:467.6-467.51"
   wire \sdram_bankmachine0_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:451.6-451.46"
+  attribute \src "ls180.v:464.6-464.46"
   wire \sdram_bankmachine0_cmd_buffer_sink_ready
-  attribute \src "ls180.v:450.6-450.46"
+  attribute \src "ls180.v:463.6-463.46"
   wire \sdram_bankmachine0_cmd_buffer_sink_valid
-  attribute \src "ls180.v:458.5-458.47"
+  attribute \src "ls180.v:471.5-471.47"
   wire \sdram_bankmachine0_cmd_buffer_source_first
-  attribute \src "ls180.v:459.5-459.46"
+  attribute \src "ls180.v:472.5-472.46"
   wire \sdram_bankmachine0_cmd_buffer_source_last
-  attribute \src "ls180.v:461.12-461.61"
+  attribute \src "ls180.v:474.12-474.61"
   wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:460.5-460.52"
+  attribute \src "ls180.v:473.5-473.52"
   wire \sdram_bankmachine0_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:457.6-457.48"
+  attribute \src "ls180.v:470.6-470.48"
   wire \sdram_bankmachine0_cmd_buffer_source_ready
-  attribute \src "ls180.v:456.5-456.47"
+  attribute \src "ls180.v:469.5-469.47"
   wire \sdram_bankmachine0_cmd_buffer_source_valid
-  attribute \src "ls180.v:404.12-404.44"
+  attribute \src "ls180.v:417.12-417.44"
   wire width 13 \sdram_bankmachine0_cmd_payload_a
-  attribute \src "ls180.v:405.12-405.45"
+  attribute \src "ls180.v:418.12-418.45"
   wire width 2 \sdram_bankmachine0_cmd_payload_ba
-  attribute \src "ls180.v:406.5-406.39"
+  attribute \src "ls180.v:419.5-419.39"
   wire \sdram_bankmachine0_cmd_payload_cas
-  attribute \src "ls180.v:409.5-409.42"
+  attribute \src "ls180.v:422.5-422.42"
   wire \sdram_bankmachine0_cmd_payload_is_cmd
-  attribute \src "ls180.v:410.5-410.43"
+  attribute \src "ls180.v:423.5-423.43"
   wire \sdram_bankmachine0_cmd_payload_is_read
-  attribute \src "ls180.v:411.5-411.44"
+  attribute \src "ls180.v:424.5-424.44"
   wire \sdram_bankmachine0_cmd_payload_is_write
-  attribute \src "ls180.v:407.5-407.39"
+  attribute \src "ls180.v:420.5-420.39"
   wire \sdram_bankmachine0_cmd_payload_ras
-  attribute \src "ls180.v:408.5-408.38"
+  attribute \src "ls180.v:421.5-421.38"
   wire \sdram_bankmachine0_cmd_payload_we
-  attribute \src "ls180.v:403.5-403.33"
+  attribute \src "ls180.v:416.5-416.33"
   wire \sdram_bankmachine0_cmd_ready
-  attribute \src "ls180.v:402.5-402.33"
+  attribute \src "ls180.v:415.5-415.33"
   wire \sdram_bankmachine0_cmd_valid
-  attribute \src "ls180.v:401.5-401.35"
+  attribute \src "ls180.v:414.5-414.35"
   wire \sdram_bankmachine0_refresh_gnt
-  attribute \src "ls180.v:400.6-400.36"
+  attribute \src "ls180.v:413.6-413.36"
   wire \sdram_bankmachine0_refresh_req
-  attribute \src "ls180.v:396.13-396.40"
+  attribute \src "ls180.v:409.13-409.40"
   wire width 22 \sdram_bankmachine0_req_addr
-  attribute \src "ls180.v:397.6-397.33"
+  attribute \src "ls180.v:410.6-410.33"
   wire \sdram_bankmachine0_req_lock
-  attribute \src "ls180.v:399.5-399.39"
+  attribute \src "ls180.v:412.5-412.39"
   wire \sdram_bankmachine0_req_rdata_valid
-  attribute \src "ls180.v:394.6-394.34"
+  attribute \src "ls180.v:407.6-407.34"
   wire \sdram_bankmachine0_req_ready
-  attribute \src "ls180.v:393.6-393.34"
+  attribute \src "ls180.v:406.6-406.34"
   wire \sdram_bankmachine0_req_valid
-  attribute \src "ls180.v:398.5-398.39"
+  attribute \src "ls180.v:411.5-411.39"
   wire \sdram_bankmachine0_req_wdata_ready
-  attribute \src "ls180.v:395.6-395.31"
+  attribute \src "ls180.v:408.6-408.31"
   wire \sdram_bankmachine0_req_we
-  attribute \src "ls180.v:462.12-462.34"
+  attribute \src "ls180.v:475.12-475.34"
   wire width 13 \sdram_bankmachine0_row
-  attribute \src "ls180.v:466.5-466.33"
+  attribute \src "ls180.v:479.5-479.33"
   wire \sdram_bankmachine0_row_close
-  attribute \src "ls180.v:467.5-467.42"
+  attribute \src "ls180.v:480.5-480.42"
   wire \sdram_bankmachine0_row_col_n_addr_sel
-  attribute \src "ls180.v:464.6-464.32"
+  attribute \src "ls180.v:477.6-477.32"
   wire \sdram_bankmachine0_row_hit
-  attribute \src "ls180.v:465.5-465.32"
+  attribute \src "ls180.v:478.5-478.32"
   wire \sdram_bankmachine0_row_open
-  attribute \src "ls180.v:463.5-463.34"
+  attribute \src "ls180.v:476.5-476.34"
   wire \sdram_bankmachine0_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:474.32-474.64"
+  attribute \src "ls180.v:487.32-487.64"
   wire \sdram_bankmachine0_trascon_ready
-  attribute \src "ls180.v:473.6-473.38"
+  attribute \src "ls180.v:486.6-486.38"
   wire \sdram_bankmachine0_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:472.32-472.63"
+  attribute \src "ls180.v:485.32-485.63"
   wire \sdram_bankmachine0_trccon_ready
-  attribute \src "ls180.v:471.6-471.37"
+  attribute \src "ls180.v:484.6-484.37"
   wire \sdram_bankmachine0_trccon_valid
-  attribute \src "ls180.v:470.11-470.43"
+  attribute \src "ls180.v:483.11-483.43"
   wire width 3 \sdram_bankmachine0_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:469.32-469.64"
+  attribute \src "ls180.v:482.32-482.64"
   wire \sdram_bankmachine0_twtpcon_ready
-  attribute \src "ls180.v:468.6-468.38"
+  attribute \src "ls180.v:481.6-481.38"
   wire \sdram_bankmachine0_twtpcon_valid
-  attribute \src "ls180.v:494.5-494.38"
+  attribute \src "ls180.v:507.5-507.38"
   wire \sdram_bankmachine1_auto_precharge
-  attribute \src "ls180.v:516.11-516.58"
+  attribute \src "ls180.v:529.11-529.58"
   wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:521.6-521.53"
+  attribute \src "ls180.v:534.6-534.53"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:526.6-526.59"
+  attribute \src "ls180.v:539.6-539.59"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:527.6-527.58"
+  attribute \src "ls180.v:540.6-540.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:525.13-525.73"
+  attribute \src "ls180.v:538.13-538.73"
   wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:524.6-524.64"
+  attribute \src "ls180.v:537.6-537.64"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:530.6-530.60"
+  attribute \src "ls180.v:543.6-543.60"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:531.6-531.59"
+  attribute \src "ls180.v:544.6-544.59"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:529.13-529.74"
+  attribute \src "ls180.v:542.13-542.74"
   wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:528.6-528.65"
+  attribute \src "ls180.v:541.6-541.65"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:513.11-513.56"
+  attribute \src "ls180.v:526.11-526.56"
   wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:515.11-515.58"
+  attribute \src "ls180.v:528.11-528.58"
   wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:522.12-522.62"
+  attribute \src "ls180.v:535.12-535.62"
   wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:523.13-523.65"
+  attribute \src "ls180.v:536.13-536.65"
   wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:514.5-514.52"
+  attribute \src "ls180.v:527.5-527.52"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:497.5-497.55"
+  attribute \src "ls180.v:510.5-510.55"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:498.5-498.54"
+  attribute \src "ls180.v:511.5-511.54"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:500.13-500.70"
+  attribute \src "ls180.v:513.13-513.70"
   wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:499.6-499.61"
+  attribute \src "ls180.v:512.6-512.61"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:496.6-496.56"
+  attribute \src "ls180.v:509.6-509.56"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:495.6-495.56"
+  attribute \src "ls180.v:508.6-508.56"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:503.6-503.58"
+  attribute \src "ls180.v:516.6-516.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:504.6-504.57"
+  attribute \src "ls180.v:517.6-517.57"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:506.13-506.72"
+  attribute \src "ls180.v:519.13-519.72"
   wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:505.6-505.63"
+  attribute \src "ls180.v:518.6-518.63"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:502.6-502.58"
+  attribute \src "ls180.v:515.6-515.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:501.6-501.58"
+  attribute \src "ls180.v:514.6-514.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:511.13-511.66"
+  attribute \src "ls180.v:524.13-524.66"
   wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
-  attribute \src "ls180.v:512.13-512.67"
+  attribute \src "ls180.v:525.13-525.67"
   wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
-  attribute \src "ls180.v:509.6-509.58"
+  attribute \src "ls180.v:522.6-522.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
-  attribute \src "ls180.v:510.6-510.64"
+  attribute \src "ls180.v:523.6-523.64"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
-  attribute \src "ls180.v:507.6-507.58"
+  attribute \src "ls180.v:520.6-520.58"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
-  attribute \src "ls180.v:508.6-508.64"
+  attribute \src "ls180.v:521.6-521.64"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-  attribute \src "ls180.v:517.11-517.61"
+  attribute \src "ls180.v:530.11-530.61"
   wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:518.13-518.65"
+  attribute \src "ls180.v:531.13-531.65"
   wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:520.13-520.65"
+  attribute \src "ls180.v:533.13-533.65"
   wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:519.6-519.55"
+  attribute \src "ls180.v:532.6-532.55"
   wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:534.6-534.46"
+  attribute \src "ls180.v:547.6-547.46"
   wire \sdram_bankmachine1_cmd_buffer_sink_first
-  attribute \src "ls180.v:535.6-535.45"
+  attribute \src "ls180.v:548.6-548.45"
   wire \sdram_bankmachine1_cmd_buffer_sink_last
-  attribute \src "ls180.v:537.13-537.60"
+  attribute \src "ls180.v:550.13-550.60"
   wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:536.6-536.51"
+  attribute \src "ls180.v:549.6-549.51"
   wire \sdram_bankmachine1_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:533.6-533.46"
+  attribute \src "ls180.v:546.6-546.46"
   wire \sdram_bankmachine1_cmd_buffer_sink_ready
-  attribute \src "ls180.v:532.6-532.46"
+  attribute \src "ls180.v:545.6-545.46"
   wire \sdram_bankmachine1_cmd_buffer_sink_valid
-  attribute \src "ls180.v:540.5-540.47"
+  attribute \src "ls180.v:553.5-553.47"
   wire \sdram_bankmachine1_cmd_buffer_source_first
-  attribute \src "ls180.v:541.5-541.46"
+  attribute \src "ls180.v:554.5-554.46"
   wire \sdram_bankmachine1_cmd_buffer_source_last
-  attribute \src "ls180.v:543.12-543.61"
+  attribute \src "ls180.v:556.12-556.61"
   wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:542.5-542.52"
+  attribute \src "ls180.v:555.5-555.52"
   wire \sdram_bankmachine1_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:539.6-539.48"
+  attribute \src "ls180.v:552.6-552.48"
   wire \sdram_bankmachine1_cmd_buffer_source_ready
-  attribute \src "ls180.v:538.5-538.47"
+  attribute \src "ls180.v:551.5-551.47"
   wire \sdram_bankmachine1_cmd_buffer_source_valid
-  attribute \src "ls180.v:486.12-486.44"
+  attribute \src "ls180.v:499.12-499.44"
   wire width 13 \sdram_bankmachine1_cmd_payload_a
-  attribute \src "ls180.v:487.12-487.45"
+  attribute \src "ls180.v:500.12-500.45"
   wire width 2 \sdram_bankmachine1_cmd_payload_ba
-  attribute \src "ls180.v:488.5-488.39"
+  attribute \src "ls180.v:501.5-501.39"
   wire \sdram_bankmachine1_cmd_payload_cas
-  attribute \src "ls180.v:491.5-491.42"
+  attribute \src "ls180.v:504.5-504.42"
   wire \sdram_bankmachine1_cmd_payload_is_cmd
-  attribute \src "ls180.v:492.5-492.43"
+  attribute \src "ls180.v:505.5-505.43"
   wire \sdram_bankmachine1_cmd_payload_is_read
-  attribute \src "ls180.v:493.5-493.44"
+  attribute \src "ls180.v:506.5-506.44"
   wire \sdram_bankmachine1_cmd_payload_is_write
-  attribute \src "ls180.v:489.5-489.39"
+  attribute \src "ls180.v:502.5-502.39"
   wire \sdram_bankmachine1_cmd_payload_ras
-  attribute \src "ls180.v:490.5-490.38"
+  attribute \src "ls180.v:503.5-503.38"
   wire \sdram_bankmachine1_cmd_payload_we
-  attribute \src "ls180.v:485.5-485.33"
+  attribute \src "ls180.v:498.5-498.33"
   wire \sdram_bankmachine1_cmd_ready
-  attribute \src "ls180.v:484.5-484.33"
+  attribute \src "ls180.v:497.5-497.33"
   wire \sdram_bankmachine1_cmd_valid
-  attribute \src "ls180.v:483.5-483.35"
+  attribute \src "ls180.v:496.5-496.35"
   wire \sdram_bankmachine1_refresh_gnt
-  attribute \src "ls180.v:482.6-482.36"
+  attribute \src "ls180.v:495.6-495.36"
   wire \sdram_bankmachine1_refresh_req
-  attribute \src "ls180.v:478.13-478.40"
+  attribute \src "ls180.v:491.13-491.40"
   wire width 22 \sdram_bankmachine1_req_addr
-  attribute \src "ls180.v:479.6-479.33"
+  attribute \src "ls180.v:492.6-492.33"
   wire \sdram_bankmachine1_req_lock
-  attribute \src "ls180.v:481.5-481.39"
+  attribute \src "ls180.v:494.5-494.39"
   wire \sdram_bankmachine1_req_rdata_valid
-  attribute \src "ls180.v:476.6-476.34"
+  attribute \src "ls180.v:489.6-489.34"
   wire \sdram_bankmachine1_req_ready
-  attribute \src "ls180.v:475.6-475.34"
+  attribute \src "ls180.v:488.6-488.34"
   wire \sdram_bankmachine1_req_valid
-  attribute \src "ls180.v:480.5-480.39"
+  attribute \src "ls180.v:493.5-493.39"
   wire \sdram_bankmachine1_req_wdata_ready
-  attribute \src "ls180.v:477.6-477.31"
+  attribute \src "ls180.v:490.6-490.31"
   wire \sdram_bankmachine1_req_we
-  attribute \src "ls180.v:544.12-544.34"
+  attribute \src "ls180.v:557.12-557.34"
   wire width 13 \sdram_bankmachine1_row
-  attribute \src "ls180.v:548.5-548.33"
+  attribute \src "ls180.v:561.5-561.33"
   wire \sdram_bankmachine1_row_close
-  attribute \src "ls180.v:549.5-549.42"
+  attribute \src "ls180.v:562.5-562.42"
   wire \sdram_bankmachine1_row_col_n_addr_sel
-  attribute \src "ls180.v:546.6-546.32"
+  attribute \src "ls180.v:559.6-559.32"
   wire \sdram_bankmachine1_row_hit
-  attribute \src "ls180.v:547.5-547.32"
+  attribute \src "ls180.v:560.5-560.32"
   wire \sdram_bankmachine1_row_open
-  attribute \src "ls180.v:545.5-545.34"
+  attribute \src "ls180.v:558.5-558.34"
   wire \sdram_bankmachine1_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:556.32-556.64"
+  attribute \src "ls180.v:569.32-569.64"
   wire \sdram_bankmachine1_trascon_ready
-  attribute \src "ls180.v:555.6-555.38"
+  attribute \src "ls180.v:568.6-568.38"
   wire \sdram_bankmachine1_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:554.32-554.63"
+  attribute \src "ls180.v:567.32-567.63"
   wire \sdram_bankmachine1_trccon_ready
-  attribute \src "ls180.v:553.6-553.37"
+  attribute \src "ls180.v:566.6-566.37"
   wire \sdram_bankmachine1_trccon_valid
-  attribute \src "ls180.v:552.11-552.43"
+  attribute \src "ls180.v:565.11-565.43"
   wire width 3 \sdram_bankmachine1_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:551.32-551.64"
+  attribute \src "ls180.v:564.32-564.64"
   wire \sdram_bankmachine1_twtpcon_ready
-  attribute \src "ls180.v:550.6-550.38"
+  attribute \src "ls180.v:563.6-563.38"
   wire \sdram_bankmachine1_twtpcon_valid
-  attribute \src "ls180.v:576.5-576.38"
+  attribute \src "ls180.v:589.5-589.38"
   wire \sdram_bankmachine2_auto_precharge
-  attribute \src "ls180.v:598.11-598.58"
+  attribute \src "ls180.v:611.11-611.58"
   wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:603.6-603.53"
+  attribute \src "ls180.v:616.6-616.53"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:608.6-608.59"
+  attribute \src "ls180.v:621.6-621.59"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:609.6-609.58"
+  attribute \src "ls180.v:622.6-622.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:607.13-607.73"
+  attribute \src "ls180.v:620.13-620.73"
   wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:606.6-606.64"
+  attribute \src "ls180.v:619.6-619.64"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:612.6-612.60"
+  attribute \src "ls180.v:625.6-625.60"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:613.6-613.59"
+  attribute \src "ls180.v:626.6-626.59"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:611.13-611.74"
+  attribute \src "ls180.v:624.13-624.74"
   wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:610.6-610.65"
+  attribute \src "ls180.v:623.6-623.65"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:595.11-595.56"
+  attribute \src "ls180.v:608.11-608.56"
   wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:597.11-597.58"
+  attribute \src "ls180.v:610.11-610.58"
   wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:604.12-604.62"
+  attribute \src "ls180.v:617.12-617.62"
   wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:605.13-605.65"
+  attribute \src "ls180.v:618.13-618.65"
   wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:596.5-596.52"
+  attribute \src "ls180.v:609.5-609.52"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:579.5-579.55"
+  attribute \src "ls180.v:592.5-592.55"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:580.5-580.54"
+  attribute \src "ls180.v:593.5-593.54"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:582.13-582.70"
+  attribute \src "ls180.v:595.13-595.70"
   wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:581.6-581.61"
+  attribute \src "ls180.v:594.6-594.61"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:578.6-578.56"
+  attribute \src "ls180.v:591.6-591.56"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:577.6-577.56"
+  attribute \src "ls180.v:590.6-590.56"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:585.6-585.58"
+  attribute \src "ls180.v:598.6-598.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:586.6-586.57"
+  attribute \src "ls180.v:599.6-599.57"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:588.13-588.72"
+  attribute \src "ls180.v:601.13-601.72"
   wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:587.6-587.63"
+  attribute \src "ls180.v:600.6-600.63"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:584.6-584.58"
+  attribute \src "ls180.v:597.6-597.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:583.6-583.58"
+  attribute \src "ls180.v:596.6-596.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:593.13-593.66"
+  attribute \src "ls180.v:606.13-606.66"
   wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
-  attribute \src "ls180.v:594.13-594.67"
+  attribute \src "ls180.v:607.13-607.67"
   wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
-  attribute \src "ls180.v:591.6-591.58"
+  attribute \src "ls180.v:604.6-604.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
-  attribute \src "ls180.v:592.6-592.64"
+  attribute \src "ls180.v:605.6-605.64"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
-  attribute \src "ls180.v:589.6-589.58"
+  attribute \src "ls180.v:602.6-602.58"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
-  attribute \src "ls180.v:590.6-590.64"
+  attribute \src "ls180.v:603.6-603.64"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-  attribute \src "ls180.v:599.11-599.61"
+  attribute \src "ls180.v:612.11-612.61"
   wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:600.13-600.65"
+  attribute \src "ls180.v:613.13-613.65"
   wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:602.13-602.65"
+  attribute \src "ls180.v:615.13-615.65"
   wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:601.6-601.55"
+  attribute \src "ls180.v:614.6-614.55"
   wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:616.6-616.46"
+  attribute \src "ls180.v:629.6-629.46"
   wire \sdram_bankmachine2_cmd_buffer_sink_first
-  attribute \src "ls180.v:617.6-617.45"
+  attribute \src "ls180.v:630.6-630.45"
   wire \sdram_bankmachine2_cmd_buffer_sink_last
-  attribute \src "ls180.v:619.13-619.60"
+  attribute \src "ls180.v:632.13-632.60"
   wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:618.6-618.51"
+  attribute \src "ls180.v:631.6-631.51"
   wire \sdram_bankmachine2_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:615.6-615.46"
+  attribute \src "ls180.v:628.6-628.46"
   wire \sdram_bankmachine2_cmd_buffer_sink_ready
-  attribute \src "ls180.v:614.6-614.46"
+  attribute \src "ls180.v:627.6-627.46"
   wire \sdram_bankmachine2_cmd_buffer_sink_valid
-  attribute \src "ls180.v:622.5-622.47"
+  attribute \src "ls180.v:635.5-635.47"
   wire \sdram_bankmachine2_cmd_buffer_source_first
-  attribute \src "ls180.v:623.5-623.46"
+  attribute \src "ls180.v:636.5-636.46"
   wire \sdram_bankmachine2_cmd_buffer_source_last
-  attribute \src "ls180.v:625.12-625.61"
+  attribute \src "ls180.v:638.12-638.61"
   wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:624.5-624.52"
+  attribute \src "ls180.v:637.5-637.52"
   wire \sdram_bankmachine2_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:621.6-621.48"
+  attribute \src "ls180.v:634.6-634.48"
   wire \sdram_bankmachine2_cmd_buffer_source_ready
-  attribute \src "ls180.v:620.5-620.47"
+  attribute \src "ls180.v:633.5-633.47"
   wire \sdram_bankmachine2_cmd_buffer_source_valid
-  attribute \src "ls180.v:568.12-568.44"
+  attribute \src "ls180.v:581.12-581.44"
   wire width 13 \sdram_bankmachine2_cmd_payload_a
-  attribute \src "ls180.v:569.12-569.45"
+  attribute \src "ls180.v:582.12-582.45"
   wire width 2 \sdram_bankmachine2_cmd_payload_ba
-  attribute \src "ls180.v:570.5-570.39"
+  attribute \src "ls180.v:583.5-583.39"
   wire \sdram_bankmachine2_cmd_payload_cas
-  attribute \src "ls180.v:573.5-573.42"
+  attribute \src "ls180.v:586.5-586.42"
   wire \sdram_bankmachine2_cmd_payload_is_cmd
-  attribute \src "ls180.v:574.5-574.43"
+  attribute \src "ls180.v:587.5-587.43"
   wire \sdram_bankmachine2_cmd_payload_is_read
-  attribute \src "ls180.v:575.5-575.44"
+  attribute \src "ls180.v:588.5-588.44"
   wire \sdram_bankmachine2_cmd_payload_is_write
-  attribute \src "ls180.v:571.5-571.39"
+  attribute \src "ls180.v:584.5-584.39"
   wire \sdram_bankmachine2_cmd_payload_ras
-  attribute \src "ls180.v:572.5-572.38"
+  attribute \src "ls180.v:585.5-585.38"
   wire \sdram_bankmachine2_cmd_payload_we
-  attribute \src "ls180.v:567.5-567.33"
+  attribute \src "ls180.v:580.5-580.33"
   wire \sdram_bankmachine2_cmd_ready
-  attribute \src "ls180.v:566.5-566.33"
+  attribute \src "ls180.v:579.5-579.33"
   wire \sdram_bankmachine2_cmd_valid
-  attribute \src "ls180.v:565.5-565.35"
+  attribute \src "ls180.v:578.5-578.35"
   wire \sdram_bankmachine2_refresh_gnt
-  attribute \src "ls180.v:564.6-564.36"
+  attribute \src "ls180.v:577.6-577.36"
   wire \sdram_bankmachine2_refresh_req
-  attribute \src "ls180.v:560.13-560.40"
+  attribute \src "ls180.v:573.13-573.40"
   wire width 22 \sdram_bankmachine2_req_addr
-  attribute \src "ls180.v:561.6-561.33"
+  attribute \src "ls180.v:574.6-574.33"
   wire \sdram_bankmachine2_req_lock
-  attribute \src "ls180.v:563.5-563.39"
+  attribute \src "ls180.v:576.5-576.39"
   wire \sdram_bankmachine2_req_rdata_valid
-  attribute \src "ls180.v:558.6-558.34"
+  attribute \src "ls180.v:571.6-571.34"
   wire \sdram_bankmachine2_req_ready
-  attribute \src "ls180.v:557.6-557.34"
+  attribute \src "ls180.v:570.6-570.34"
   wire \sdram_bankmachine2_req_valid
-  attribute \src "ls180.v:562.5-562.39"
+  attribute \src "ls180.v:575.5-575.39"
   wire \sdram_bankmachine2_req_wdata_ready
-  attribute \src "ls180.v:559.6-559.31"
+  attribute \src "ls180.v:572.6-572.31"
   wire \sdram_bankmachine2_req_we
-  attribute \src "ls180.v:626.12-626.34"
+  attribute \src "ls180.v:639.12-639.34"
   wire width 13 \sdram_bankmachine2_row
-  attribute \src "ls180.v:630.5-630.33"
+  attribute \src "ls180.v:643.5-643.33"
   wire \sdram_bankmachine2_row_close
-  attribute \src "ls180.v:631.5-631.42"
+  attribute \src "ls180.v:644.5-644.42"
   wire \sdram_bankmachine2_row_col_n_addr_sel
-  attribute \src "ls180.v:628.6-628.32"
+  attribute \src "ls180.v:641.6-641.32"
   wire \sdram_bankmachine2_row_hit
-  attribute \src "ls180.v:629.5-629.32"
+  attribute \src "ls180.v:642.5-642.32"
   wire \sdram_bankmachine2_row_open
-  attribute \src "ls180.v:627.5-627.34"
+  attribute \src "ls180.v:640.5-640.34"
   wire \sdram_bankmachine2_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:638.32-638.64"
+  attribute \src "ls180.v:651.32-651.64"
   wire \sdram_bankmachine2_trascon_ready
-  attribute \src "ls180.v:637.6-637.38"
+  attribute \src "ls180.v:650.6-650.38"
   wire \sdram_bankmachine2_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:636.32-636.63"
+  attribute \src "ls180.v:649.32-649.63"
   wire \sdram_bankmachine2_trccon_ready
-  attribute \src "ls180.v:635.6-635.37"
+  attribute \src "ls180.v:648.6-648.37"
   wire \sdram_bankmachine2_trccon_valid
-  attribute \src "ls180.v:634.11-634.43"
+  attribute \src "ls180.v:647.11-647.43"
   wire width 3 \sdram_bankmachine2_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:633.32-633.64"
+  attribute \src "ls180.v:646.32-646.64"
   wire \sdram_bankmachine2_twtpcon_ready
-  attribute \src "ls180.v:632.6-632.38"
+  attribute \src "ls180.v:645.6-645.38"
   wire \sdram_bankmachine2_twtpcon_valid
-  attribute \src "ls180.v:658.5-658.38"
+  attribute \src "ls180.v:671.5-671.38"
   wire \sdram_bankmachine3_auto_precharge
-  attribute \src "ls180.v:680.11-680.58"
+  attribute \src "ls180.v:693.11-693.58"
   wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume
-  attribute \src "ls180.v:685.6-685.53"
+  attribute \src "ls180.v:698.6-698.53"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read
-  attribute \src "ls180.v:690.6-690.59"
+  attribute \src "ls180.v:703.6-703.59"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
-  attribute \src "ls180.v:691.6-691.58"
+  attribute \src "ls180.v:704.6-704.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
-  attribute \src "ls180.v:689.13-689.73"
+  attribute \src "ls180.v:702.13-702.73"
   wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
-  attribute \src "ls180.v:688.6-688.64"
+  attribute \src "ls180.v:701.6-701.64"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
-  attribute \src "ls180.v:694.6-694.60"
+  attribute \src "ls180.v:707.6-707.60"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
-  attribute \src "ls180.v:695.6-695.59"
+  attribute \src "ls180.v:708.6-708.59"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
-  attribute \src "ls180.v:693.13-693.74"
+  attribute \src "ls180.v:706.13-706.74"
   wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
-  attribute \src "ls180.v:692.6-692.65"
+  attribute \src "ls180.v:705.6-705.65"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
-  attribute \src "ls180.v:677.11-677.56"
+  attribute \src "ls180.v:690.11-690.56"
   wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level
-  attribute \src "ls180.v:679.11-679.58"
+  attribute \src "ls180.v:692.11-692.58"
   wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce
-  attribute \src "ls180.v:686.12-686.62"
+  attribute \src "ls180.v:699.12-699.62"
   wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
-  attribute \src "ls180.v:687.13-687.65"
+  attribute \src "ls180.v:700.13-700.65"
   wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
-  attribute \src "ls180.v:678.5-678.52"
+  attribute \src "ls180.v:691.5-691.52"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_replace
-  attribute \src "ls180.v:661.5-661.55"
+  attribute \src "ls180.v:674.5-674.55"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first
-  attribute \src "ls180.v:662.5-662.54"
+  attribute \src "ls180.v:675.5-675.54"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last
-  attribute \src "ls180.v:664.13-664.70"
+  attribute \src "ls180.v:677.13-677.70"
   wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
-  attribute \src "ls180.v:663.6-663.61"
+  attribute \src "ls180.v:676.6-676.61"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
-  attribute \src "ls180.v:660.6-660.56"
+  attribute \src "ls180.v:673.6-673.56"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
-  attribute \src "ls180.v:659.6-659.56"
+  attribute \src "ls180.v:672.6-672.56"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
-  attribute \src "ls180.v:667.6-667.58"
+  attribute \src "ls180.v:680.6-680.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first
-  attribute \src "ls180.v:668.6-668.57"
+  attribute \src "ls180.v:681.6-681.57"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last
-  attribute \src "ls180.v:670.13-670.72"
+  attribute \src "ls180.v:683.13-683.72"
   wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
-  attribute \src "ls180.v:669.6-669.63"
+  attribute \src "ls180.v:682.6-682.63"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
-  attribute \src "ls180.v:666.6-666.58"
+  attribute \src "ls180.v:679.6-679.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready
-  attribute \src "ls180.v:665.6-665.58"
+  attribute \src "ls180.v:678.6-678.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
-  attribute \src "ls180.v:675.13-675.66"
+  attribute \src "ls180.v:688.13-688.66"
   wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
-  attribute \src "ls180.v:676.13-676.67"
+  attribute \src "ls180.v:689.13-689.67"
   wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
-  attribute \src "ls180.v:673.6-673.58"
+  attribute \src "ls180.v:686.6-686.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
-  attribute \src "ls180.v:674.6-674.64"
+  attribute \src "ls180.v:687.6-687.64"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
-  attribute \src "ls180.v:671.6-671.58"
+  attribute \src "ls180.v:684.6-684.58"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
-  attribute \src "ls180.v:672.6-672.64"
+  attribute \src "ls180.v:685.6-685.64"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-  attribute \src "ls180.v:681.11-681.61"
+  attribute \src "ls180.v:694.11-694.61"
   wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
-  attribute \src "ls180.v:682.13-682.65"
+  attribute \src "ls180.v:695.13-695.65"
   wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
-  attribute \src "ls180.v:684.13-684.65"
+  attribute \src "ls180.v:697.13-697.65"
   wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
-  attribute \src "ls180.v:683.6-683.55"
+  attribute \src "ls180.v:696.6-696.55"
   wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
-  attribute \src "ls180.v:698.6-698.46"
+  attribute \src "ls180.v:711.6-711.46"
   wire \sdram_bankmachine3_cmd_buffer_sink_first
-  attribute \src "ls180.v:699.6-699.45"
+  attribute \src "ls180.v:712.6-712.45"
   wire \sdram_bankmachine3_cmd_buffer_sink_last
-  attribute \src "ls180.v:701.13-701.60"
+  attribute \src "ls180.v:714.13-714.60"
   wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr
-  attribute \src "ls180.v:700.6-700.51"
+  attribute \src "ls180.v:713.6-713.51"
   wire \sdram_bankmachine3_cmd_buffer_sink_payload_we
-  attribute \src "ls180.v:697.6-697.46"
+  attribute \src "ls180.v:710.6-710.46"
   wire \sdram_bankmachine3_cmd_buffer_sink_ready
-  attribute \src "ls180.v:696.6-696.46"
+  attribute \src "ls180.v:709.6-709.46"
   wire \sdram_bankmachine3_cmd_buffer_sink_valid
-  attribute \src "ls180.v:704.5-704.47"
+  attribute \src "ls180.v:717.5-717.47"
   wire \sdram_bankmachine3_cmd_buffer_source_first
-  attribute \src "ls180.v:705.5-705.46"
+  attribute \src "ls180.v:718.5-718.46"
   wire \sdram_bankmachine3_cmd_buffer_source_last
-  attribute \src "ls180.v:707.12-707.61"
+  attribute \src "ls180.v:720.12-720.61"
   wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr
-  attribute \src "ls180.v:706.5-706.52"
+  attribute \src "ls180.v:719.5-719.52"
   wire \sdram_bankmachine3_cmd_buffer_source_payload_we
-  attribute \src "ls180.v:703.6-703.48"
+  attribute \src "ls180.v:716.6-716.48"
   wire \sdram_bankmachine3_cmd_buffer_source_ready
-  attribute \src "ls180.v:702.5-702.47"
+  attribute \src "ls180.v:715.5-715.47"
   wire \sdram_bankmachine3_cmd_buffer_source_valid
-  attribute \src "ls180.v:650.12-650.44"
+  attribute \src "ls180.v:663.12-663.44"
   wire width 13 \sdram_bankmachine3_cmd_payload_a
-  attribute \src "ls180.v:651.12-651.45"
+  attribute \src "ls180.v:664.12-664.45"
   wire width 2 \sdram_bankmachine3_cmd_payload_ba
-  attribute \src "ls180.v:652.5-652.39"
+  attribute \src "ls180.v:665.5-665.39"
   wire \sdram_bankmachine3_cmd_payload_cas
-  attribute \src "ls180.v:655.5-655.42"
+  attribute \src "ls180.v:668.5-668.42"
   wire \sdram_bankmachine3_cmd_payload_is_cmd
-  attribute \src "ls180.v:656.5-656.43"
+  attribute \src "ls180.v:669.5-669.43"
   wire \sdram_bankmachine3_cmd_payload_is_read
-  attribute \src "ls180.v:657.5-657.44"
+  attribute \src "ls180.v:670.5-670.44"
   wire \sdram_bankmachine3_cmd_payload_is_write
-  attribute \src "ls180.v:653.5-653.39"
+  attribute \src "ls180.v:666.5-666.39"
   wire \sdram_bankmachine3_cmd_payload_ras
-  attribute \src "ls180.v:654.5-654.38"
+  attribute \src "ls180.v:667.5-667.38"
   wire \sdram_bankmachine3_cmd_payload_we
-  attribute \src "ls180.v:649.5-649.33"
+  attribute \src "ls180.v:662.5-662.33"
   wire \sdram_bankmachine3_cmd_ready
-  attribute \src "ls180.v:648.5-648.33"
+  attribute \src "ls180.v:661.5-661.33"
   wire \sdram_bankmachine3_cmd_valid
-  attribute \src "ls180.v:647.5-647.35"
+  attribute \src "ls180.v:660.5-660.35"
   wire \sdram_bankmachine3_refresh_gnt
-  attribute \src "ls180.v:646.6-646.36"
+  attribute \src "ls180.v:659.6-659.36"
   wire \sdram_bankmachine3_refresh_req
-  attribute \src "ls180.v:642.13-642.40"
+  attribute \src "ls180.v:655.13-655.40"
   wire width 22 \sdram_bankmachine3_req_addr
-  attribute \src "ls180.v:643.6-643.33"
+  attribute \src "ls180.v:656.6-656.33"
   wire \sdram_bankmachine3_req_lock
-  attribute \src "ls180.v:645.5-645.39"
+  attribute \src "ls180.v:658.5-658.39"
   wire \sdram_bankmachine3_req_rdata_valid
-  attribute \src "ls180.v:640.6-640.34"
+  attribute \src "ls180.v:653.6-653.34"
   wire \sdram_bankmachine3_req_ready
-  attribute \src "ls180.v:639.6-639.34"
+  attribute \src "ls180.v:652.6-652.34"
   wire \sdram_bankmachine3_req_valid
-  attribute \src "ls180.v:644.5-644.39"
+  attribute \src "ls180.v:657.5-657.39"
   wire \sdram_bankmachine3_req_wdata_ready
-  attribute \src "ls180.v:641.6-641.31"
+  attribute \src "ls180.v:654.6-654.31"
   wire \sdram_bankmachine3_req_we
-  attribute \src "ls180.v:708.12-708.34"
+  attribute \src "ls180.v:721.12-721.34"
   wire width 13 \sdram_bankmachine3_row
-  attribute \src "ls180.v:712.5-712.33"
+  attribute \src "ls180.v:725.5-725.33"
   wire \sdram_bankmachine3_row_close
-  attribute \src "ls180.v:713.5-713.42"
+  attribute \src "ls180.v:726.5-726.42"
   wire \sdram_bankmachine3_row_col_n_addr_sel
-  attribute \src "ls180.v:710.6-710.32"
+  attribute \src "ls180.v:723.6-723.32"
   wire \sdram_bankmachine3_row_hit
-  attribute \src "ls180.v:711.5-711.32"
+  attribute \src "ls180.v:724.5-724.32"
   wire \sdram_bankmachine3_row_open
-  attribute \src "ls180.v:709.5-709.34"
+  attribute \src "ls180.v:722.5-722.34"
   wire \sdram_bankmachine3_row_opened
   attribute \no_retiming "true"
-  attribute \src "ls180.v:720.32-720.64"
+  attribute \src "ls180.v:733.32-733.64"
   wire \sdram_bankmachine3_trascon_ready
-  attribute \src "ls180.v:719.6-719.38"
+  attribute \src "ls180.v:732.6-732.38"
   wire \sdram_bankmachine3_trascon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:718.32-718.63"
+  attribute \src "ls180.v:731.32-731.63"
   wire \sdram_bankmachine3_trccon_ready
-  attribute \src "ls180.v:717.6-717.37"
+  attribute \src "ls180.v:730.6-730.37"
   wire \sdram_bankmachine3_trccon_valid
-  attribute \src "ls180.v:716.11-716.43"
+  attribute \src "ls180.v:729.11-729.43"
   wire width 3 \sdram_bankmachine3_twtpcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:715.32-715.64"
+  attribute \src "ls180.v:728.32-728.64"
   wire \sdram_bankmachine3_twtpcon_ready
-  attribute \src "ls180.v:714.6-714.38"
+  attribute \src "ls180.v:727.6-727.38"
   wire \sdram_bankmachine3_twtpcon_valid
-  attribute \src "ls180.v:722.6-722.23"
+  attribute \src "ls180.v:735.6-735.23"
   wire \sdram_cas_allowed
   attribute \src "ls180.v:16.14-16.25"
   wire output 12 \sdram_cas_n
-  attribute \src "ls180.v:740.6-740.25"
+  attribute \src "ls180.v:753.6-753.25"
   wire \sdram_choose_cmd_ce
-  attribute \src "ls180.v:729.13-729.43"
+  attribute \src "ls180.v:742.13-742.43"
   wire width 13 \sdram_choose_cmd_cmd_payload_a
-  attribute \src "ls180.v:730.12-730.43"
+  attribute \src "ls180.v:743.12-743.43"
   wire width 2 \sdram_choose_cmd_cmd_payload_ba
-  attribute \src "ls180.v:731.5-731.37"
+  attribute \src "ls180.v:744.5-744.37"
   wire \sdram_choose_cmd_cmd_payload_cas
-  attribute \src "ls180.v:734.6-734.41"
+  attribute \src "ls180.v:747.6-747.41"
   wire \sdram_choose_cmd_cmd_payload_is_cmd
-  attribute \src "ls180.v:735.6-735.42"
+  attribute \src "ls180.v:748.6-748.42"
   wire \sdram_choose_cmd_cmd_payload_is_read
-  attribute \src "ls180.v:736.6-736.43"
+  attribute \src "ls180.v:749.6-749.43"
   wire \sdram_choose_cmd_cmd_payload_is_write
-  attribute \src "ls180.v:732.5-732.37"
+  attribute \src "ls180.v:745.5-745.37"
   wire \sdram_choose_cmd_cmd_payload_ras
-  attribute \src "ls180.v:733.5-733.36"
+  attribute \src "ls180.v:746.5-746.36"
   wire \sdram_choose_cmd_cmd_payload_we
-  attribute \src "ls180.v:728.5-728.31"
+  attribute \src "ls180.v:741.5-741.31"
   wire \sdram_choose_cmd_cmd_ready
-  attribute \src "ls180.v:727.6-727.32"
+  attribute \src "ls180.v:740.6-740.32"
   wire \sdram_choose_cmd_cmd_valid
-  attribute \src "ls180.v:739.11-739.33"
+  attribute \src "ls180.v:752.11-752.33"
   wire width 2 \sdram_choose_cmd_grant
-  attribute \src "ls180.v:738.12-738.36"
+  attribute \src "ls180.v:751.12-751.36"
   wire width 4 \sdram_choose_cmd_request
-  attribute \src "ls180.v:737.11-737.34"
+  attribute \src "ls180.v:750.11-750.34"
   wire width 4 \sdram_choose_cmd_valids
-  attribute \src "ls180.v:726.5-726.36"
+  attribute \src "ls180.v:739.5-739.36"
   wire \sdram_choose_cmd_want_activates
-  attribute \src "ls180.v:725.5-725.31"
+  attribute \src "ls180.v:738.5-738.31"
   wire \sdram_choose_cmd_want_cmds
-  attribute \src "ls180.v:723.5-723.32"
+  attribute \src "ls180.v:736.5-736.32"
   wire \sdram_choose_cmd_want_reads
-  attribute \src "ls180.v:724.5-724.33"
+  attribute \src "ls180.v:737.5-737.33"
   wire \sdram_choose_cmd_want_writes
-  attribute \src "ls180.v:758.6-758.25"
+  attribute \src "ls180.v:771.6-771.25"
   wire \sdram_choose_req_ce
-  attribute \src "ls180.v:747.13-747.43"
+  attribute \src "ls180.v:760.13-760.43"
   wire width 13 \sdram_choose_req_cmd_payload_a
-  attribute \src "ls180.v:748.12-748.43"
+  attribute \src "ls180.v:761.12-761.43"
   wire width 2 \sdram_choose_req_cmd_payload_ba
-  attribute \src "ls180.v:749.5-749.37"
+  attribute \src "ls180.v:762.5-762.37"
   wire \sdram_choose_req_cmd_payload_cas
-  attribute \src "ls180.v:752.6-752.41"
+  attribute \src "ls180.v:765.6-765.41"
   wire \sdram_choose_req_cmd_payload_is_cmd
-  attribute \src "ls180.v:753.6-753.42"
+  attribute \src "ls180.v:766.6-766.42"
   wire \sdram_choose_req_cmd_payload_is_read
-  attribute \src "ls180.v:754.6-754.43"
+  attribute \src "ls180.v:767.6-767.43"
   wire \sdram_choose_req_cmd_payload_is_write
-  attribute \src "ls180.v:750.5-750.37"
+  attribute \src "ls180.v:763.5-763.37"
   wire \sdram_choose_req_cmd_payload_ras
-  attribute \src "ls180.v:751.5-751.36"
+  attribute \src "ls180.v:764.5-764.36"
   wire \sdram_choose_req_cmd_payload_we
-  attribute \src "ls180.v:746.5-746.31"
+  attribute \src "ls180.v:759.5-759.31"
   wire \sdram_choose_req_cmd_ready
-  attribute \src "ls180.v:745.6-745.32"
+  attribute \src "ls180.v:758.6-758.32"
   wire \sdram_choose_req_cmd_valid
-  attribute \src "ls180.v:757.11-757.33"
+  attribute \src "ls180.v:770.11-770.33"
   wire width 2 \sdram_choose_req_grant
-  attribute \src "ls180.v:756.12-756.36"
+  attribute \src "ls180.v:769.12-769.36"
   wire width 4 \sdram_choose_req_request
-  attribute \src "ls180.v:755.11-755.34"
+  attribute \src "ls180.v:768.11-768.34"
   wire width 4 \sdram_choose_req_valids
-  attribute \src "ls180.v:744.5-744.36"
+  attribute \src "ls180.v:757.5-757.36"
   wire \sdram_choose_req_want_activates
-  attribute \src "ls180.v:743.6-743.32"
+  attribute \src "ls180.v:756.6-756.32"
   wire \sdram_choose_req_want_cmds
-  attribute \src "ls180.v:741.5-741.32"
+  attribute \src "ls180.v:754.5-754.32"
   wire \sdram_choose_req_want_reads
-  attribute \src "ls180.v:742.5-742.33"
+  attribute \src "ls180.v:755.5-755.33"
   wire \sdram_choose_req_want_writes
   attribute \src "ls180.v:18.14-18.23"
   wire output 14 \sdram_cke
-  attribute \src "ls180.v:302.6-302.17"
+  attribute \src "ls180.v:315.6-315.17"
   wire \sdram_cke_1
   attribute \src "ls180.v:21.14-21.25"
   wire output 17 \sdram_clock
-  attribute \src "ls180.v:370.5-370.19"
+  attribute \src "ls180.v:383.5-383.19"
   wire \sdram_cmd_last
-  attribute \src "ls180.v:371.12-371.31"
+  attribute \src "ls180.v:384.12-384.31"
   wire width 13 \sdram_cmd_payload_a
-  attribute \src "ls180.v:372.11-372.31"
+  attribute \src "ls180.v:385.11-385.31"
   wire width 2 \sdram_cmd_payload_ba
-  attribute \src "ls180.v:373.5-373.26"
+  attribute \src "ls180.v:386.5-386.26"
   wire \sdram_cmd_payload_cas
-  attribute \src "ls180.v:376.5-376.30"
+  attribute \src "ls180.v:389.5-389.30"
   wire \sdram_cmd_payload_is_read
-  attribute \src "ls180.v:377.5-377.31"
+  attribute \src "ls180.v:390.5-390.31"
   wire \sdram_cmd_payload_is_write
-  attribute \src "ls180.v:374.5-374.26"
+  attribute \src "ls180.v:387.5-387.26"
   wire \sdram_cmd_payload_ras
-  attribute \src "ls180.v:375.5-375.25"
+  attribute \src "ls180.v:388.5-388.25"
   wire \sdram_cmd_payload_we
-  attribute \src "ls180.v:369.5-369.20"
+  attribute \src "ls180.v:382.5-382.20"
   wire \sdram_cmd_ready
-  attribute \src "ls180.v:368.5-368.20"
+  attribute \src "ls180.v:381.5-381.20"
   wire \sdram_cmd_valid
-  attribute \src "ls180.v:310.6-310.27"
+  attribute \src "ls180.v:323.6-323.27"
   wire \sdram_command_issue_r
-  attribute \src "ls180.v:309.6-309.28"
+  attribute \src "ls180.v:322.6-322.28"
   wire \sdram_command_issue_re
-  attribute \src "ls180.v:312.5-312.26"
+  attribute \src "ls180.v:325.5-325.26"
   wire \sdram_command_issue_w
-  attribute \src "ls180.v:311.6-311.28"
+  attribute \src "ls180.v:324.6-324.28"
   wire \sdram_command_issue_we
-  attribute \src "ls180.v:308.5-308.21"
+  attribute \src "ls180.v:321.5-321.21"
   wire \sdram_command_re
-  attribute \src "ls180.v:307.11-307.32"
+  attribute \src "ls180.v:320.11-320.32"
   wire width 6 \sdram_command_storage
   attribute \src "ls180.v:17.14-17.24"
   wire output 13 \sdram_cs_n
-  attribute \src "ls180.v:361.5-361.23"
+  attribute \src "ls180.v:374.5-374.23"
   wire \sdram_dfi_p0_act_n
-  attribute \src "ls180.v:352.12-352.32"
+  attribute \src "ls180.v:365.12-365.32"
   wire width 13 \sdram_dfi_p0_address
-  attribute \src "ls180.v:353.11-353.28"
+  attribute \src "ls180.v:366.11-366.28"
   wire width 2 \sdram_dfi_p0_bank
-  attribute \src "ls180.v:354.5-354.23"
+  attribute \src "ls180.v:367.5-367.23"
   wire \sdram_dfi_p0_cas_n
-  attribute \src "ls180.v:358.6-358.22"
+  attribute \src "ls180.v:371.6-371.22"
   wire \sdram_dfi_p0_cke
-  attribute \src "ls180.v:355.5-355.22"
+  attribute \src "ls180.v:368.5-368.22"
   wire \sdram_dfi_p0_cs_n
-  attribute \src "ls180.v:359.6-359.22"
+  attribute \src "ls180.v:372.6-372.22"
   wire \sdram_dfi_p0_odt
-  attribute \src "ls180.v:356.5-356.23"
+  attribute \src "ls180.v:369.5-369.23"
   wire \sdram_dfi_p0_ras_n
-  attribute \src "ls180.v:366.13-366.32"
+  attribute \src "ls180.v:379.13-379.32"
   wire width 16 \sdram_dfi_p0_rddata
-  attribute \src "ls180.v:365.5-365.27"
+  attribute \src "ls180.v:378.5-378.27"
   wire \sdram_dfi_p0_rddata_en
-  attribute \src "ls180.v:367.6-367.31"
+  attribute \src "ls180.v:380.6-380.31"
   wire \sdram_dfi_p0_rddata_valid
-  attribute \src "ls180.v:360.6-360.26"
+  attribute \src "ls180.v:373.6-373.26"
   wire \sdram_dfi_p0_reset_n
-  attribute \src "ls180.v:357.5-357.22"
+  attribute \src "ls180.v:370.5-370.22"
   wire \sdram_dfi_p0_we_n
-  attribute \src "ls180.v:362.13-362.32"
+  attribute \src "ls180.v:375.13-375.32"
   wire width 16 \sdram_dfi_p0_wrdata
-  attribute \src "ls180.v:363.5-363.27"
+  attribute \src "ls180.v:376.5-376.27"
   wire \sdram_dfi_p0_wrdata_en
-  attribute \src "ls180.v:364.12-364.36"
+  attribute \src "ls180.v:377.12-377.36"
   wire width 2 \sdram_dfi_p0_wrdata_mask
   attribute \src "ls180.v:20.20-20.28"
   wire width 2 output 16 \sdram_dm
@@ -245980,605 +245788,571 @@ module \ls180
   wire width 16 output 8 \sdram_dq_o
   attribute \src "ls180.v:13.14-13.25"
   wire output 9 \sdram_dq_oe
-  attribute \src "ls180.v:776.5-776.14"
+  attribute \src "ls180.v:789.5-789.14"
   wire \sdram_en0
-  attribute \src "ls180.v:779.5-779.14"
+  attribute \src "ls180.v:792.5-792.14"
   wire \sdram_en1
-  attribute \src "ls180.v:782.6-782.25"
+  attribute \src "ls180.v:795.6-795.25"
   wire \sdram_go_to_refresh
-  attribute \src "ls180.v:324.13-324.39"
+  attribute \src "ls180.v:337.13-337.39"
   wire width 22 \sdram_interface_bank0_addr
-  attribute \src "ls180.v:325.6-325.32"
+  attribute \src "ls180.v:338.6-338.32"
   wire \sdram_interface_bank0_lock
-  attribute \src "ls180.v:327.6-327.39"
+  attribute \src "ls180.v:340.6-340.39"
   wire \sdram_interface_bank0_rdata_valid
-  attribute \src "ls180.v:322.6-322.33"
+  attribute \src "ls180.v:335.6-335.33"
   wire \sdram_interface_bank0_ready
-  attribute \src "ls180.v:321.6-321.33"
+  attribute \src "ls180.v:334.6-334.33"
   wire \sdram_interface_bank0_valid
-  attribute \src "ls180.v:326.6-326.39"
+  attribute \src "ls180.v:339.6-339.39"
   wire \sdram_interface_bank0_wdata_ready
-  attribute \src "ls180.v:323.6-323.30"
+  attribute \src "ls180.v:336.6-336.30"
   wire \sdram_interface_bank0_we
-  attribute \src "ls180.v:331.13-331.39"
+  attribute \src "ls180.v:344.13-344.39"
   wire width 22 \sdram_interface_bank1_addr
-  attribute \src "ls180.v:332.6-332.32"
+  attribute \src "ls180.v:345.6-345.32"
   wire \sdram_interface_bank1_lock
-  attribute \src "ls180.v:334.6-334.39"
+  attribute \src "ls180.v:347.6-347.39"
   wire \sdram_interface_bank1_rdata_valid
-  attribute \src "ls180.v:329.6-329.33"
+  attribute \src "ls180.v:342.6-342.33"
   wire \sdram_interface_bank1_ready
-  attribute \src "ls180.v:328.6-328.33"
+  attribute \src "ls180.v:341.6-341.33"
   wire \sdram_interface_bank1_valid
-  attribute \src "ls180.v:333.6-333.39"
+  attribute \src "ls180.v:346.6-346.39"
   wire \sdram_interface_bank1_wdata_ready
-  attribute \src "ls180.v:330.6-330.30"
+  attribute \src "ls180.v:343.6-343.30"
   wire \sdram_interface_bank1_we
-  attribute \src "ls180.v:338.13-338.39"
+  attribute \src "ls180.v:351.13-351.39"
   wire width 22 \sdram_interface_bank2_addr
-  attribute \src "ls180.v:339.6-339.32"
+  attribute \src "ls180.v:352.6-352.32"
   wire \sdram_interface_bank2_lock
-  attribute \src "ls180.v:341.6-341.39"
+  attribute \src "ls180.v:354.6-354.39"
   wire \sdram_interface_bank2_rdata_valid
-  attribute \src "ls180.v:336.6-336.33"
+  attribute \src "ls180.v:349.6-349.33"
   wire \sdram_interface_bank2_ready
-  attribute \src "ls180.v:335.6-335.33"
+  attribute \src "ls180.v:348.6-348.33"
   wire \sdram_interface_bank2_valid
-  attribute \src "ls180.v:340.6-340.39"
+  attribute \src "ls180.v:353.6-353.39"
   wire \sdram_interface_bank2_wdata_ready
-  attribute \src "ls180.v:337.6-337.30"
+  attribute \src "ls180.v:350.6-350.30"
   wire \sdram_interface_bank2_we
-  attribute \src "ls180.v:345.13-345.39"
+  attribute \src "ls180.v:358.13-358.39"
   wire width 22 \sdram_interface_bank3_addr
-  attribute \src "ls180.v:346.6-346.32"
+  attribute \src "ls180.v:359.6-359.32"
   wire \sdram_interface_bank3_lock
-  attribute \src "ls180.v:348.6-348.39"
+  attribute \src "ls180.v:361.6-361.39"
   wire \sdram_interface_bank3_rdata_valid
-  attribute \src "ls180.v:343.6-343.33"
+  attribute \src "ls180.v:356.6-356.33"
   wire \sdram_interface_bank3_ready
-  attribute \src "ls180.v:342.6-342.33"
+  attribute \src "ls180.v:355.6-355.33"
   wire \sdram_interface_bank3_valid
-  attribute \src "ls180.v:347.6-347.39"
+  attribute \src "ls180.v:360.6-360.39"
   wire \sdram_interface_bank3_wdata_ready
-  attribute \src "ls180.v:344.6-344.30"
+  attribute \src "ls180.v:357.6-357.30"
   wire \sdram_interface_bank3_we
-  attribute \src "ls180.v:351.13-351.34"
+  attribute \src "ls180.v:364.13-364.34"
   wire width 16 \sdram_interface_rdata
-  attribute \src "ls180.v:349.12-349.33"
+  attribute \src "ls180.v:362.12-362.33"
   wire width 16 \sdram_interface_wdata
-  attribute \src "ls180.v:350.11-350.35"
+  attribute \src "ls180.v:363.11-363.35"
   wire width 2 \sdram_interface_wdata_we
-  attribute \src "ls180.v:262.5-262.24"
+  attribute \src "ls180.v:275.5-275.24"
   wire \sdram_inti_p0_act_n
-  attribute \src "ls180.v:253.13-253.34"
+  attribute \src "ls180.v:266.13-266.34"
   wire width 13 \sdram_inti_p0_address
-  attribute \src "ls180.v:254.12-254.30"
+  attribute \src "ls180.v:267.12-267.30"
   wire width 2 \sdram_inti_p0_bank
-  attribute \src "ls180.v:255.5-255.24"
+  attribute \src "ls180.v:268.5-268.24"
   wire \sdram_inti_p0_cas_n
-  attribute \src "ls180.v:259.6-259.23"
+  attribute \src "ls180.v:272.6-272.23"
   wire \sdram_inti_p0_cke
-  attribute \src "ls180.v:256.5-256.23"
+  attribute \src "ls180.v:269.5-269.23"
   wire \sdram_inti_p0_cs_n
-  attribute \src "ls180.v:260.6-260.23"
+  attribute \src "ls180.v:273.6-273.23"
   wire \sdram_inti_p0_odt
-  attribute \src "ls180.v:257.5-257.24"
+  attribute \src "ls180.v:270.5-270.24"
   wire \sdram_inti_p0_ras_n
-  attribute \src "ls180.v:267.12-267.32"
+  attribute \src "ls180.v:280.12-280.32"
   wire width 16 \sdram_inti_p0_rddata
-  attribute \src "ls180.v:266.6-266.29"
+  attribute \src "ls180.v:279.6-279.29"
   wire \sdram_inti_p0_rddata_en
-  attribute \src "ls180.v:268.5-268.31"
+  attribute \src "ls180.v:281.5-281.31"
   wire \sdram_inti_p0_rddata_valid
-  attribute \src "ls180.v:261.6-261.27"
+  attribute \src "ls180.v:274.6-274.27"
   wire \sdram_inti_p0_reset_n
-  attribute \src "ls180.v:258.5-258.23"
+  attribute \src "ls180.v:271.5-271.23"
   wire \sdram_inti_p0_we_n
-  attribute \src "ls180.v:263.13-263.33"
+  attribute \src "ls180.v:276.13-276.33"
   wire width 16 \sdram_inti_p0_wrdata
-  attribute \src "ls180.v:264.6-264.29"
+  attribute \src "ls180.v:277.6-277.29"
   wire \sdram_inti_p0_wrdata_en
-  attribute \src "ls180.v:265.12-265.37"
+  attribute \src "ls180.v:278.12-278.37"
   wire width 2 \sdram_inti_p0_wrdata_mask
-  attribute \src "ls180.v:294.5-294.26"
+  attribute \src "ls180.v:307.5-307.26"
   wire \sdram_master_p0_act_n
-  attribute \src "ls180.v:285.12-285.35"
+  attribute \src "ls180.v:298.12-298.35"
   wire width 13 \sdram_master_p0_address
-  attribute \src "ls180.v:286.11-286.31"
+  attribute \src "ls180.v:299.11-299.31"
   wire width 2 \sdram_master_p0_bank
-  attribute \src "ls180.v:287.5-287.26"
+  attribute \src "ls180.v:300.5-300.26"
   wire \sdram_master_p0_cas_n
-  attribute \src "ls180.v:291.5-291.24"
+  attribute \src "ls180.v:304.5-304.24"
   wire \sdram_master_p0_cke
-  attribute \src "ls180.v:288.5-288.25"
+  attribute \src "ls180.v:301.5-301.25"
   wire \sdram_master_p0_cs_n
-  attribute \src "ls180.v:292.5-292.24"
+  attribute \src "ls180.v:305.5-305.24"
   wire \sdram_master_p0_odt
-  attribute \src "ls180.v:289.5-289.26"
+  attribute \src "ls180.v:302.5-302.26"
   wire \sdram_master_p0_ras_n
-  attribute \src "ls180.v:299.13-299.35"
+  attribute \src "ls180.v:312.13-312.35"
   wire width 16 \sdram_master_p0_rddata
-  attribute \src "ls180.v:298.5-298.30"
+  attribute \src "ls180.v:311.5-311.30"
   wire \sdram_master_p0_rddata_en
-  attribute \src "ls180.v:300.6-300.34"
+  attribute \src "ls180.v:313.6-313.34"
   wire \sdram_master_p0_rddata_valid
-  attribute \src "ls180.v:293.5-293.28"
+  attribute \src "ls180.v:306.5-306.28"
   wire \sdram_master_p0_reset_n
-  attribute \src "ls180.v:290.5-290.25"
+  attribute \src "ls180.v:303.5-303.25"
   wire \sdram_master_p0_we_n
-  attribute \src "ls180.v:295.12-295.34"
+  attribute \src "ls180.v:308.12-308.34"
   wire width 16 \sdram_master_p0_wrdata
-  attribute \src "ls180.v:296.5-296.30"
+  attribute \src "ls180.v:309.5-309.30"
   wire \sdram_master_p0_wrdata_en
-  attribute \src "ls180.v:297.11-297.38"
+  attribute \src "ls180.v:310.11-310.38"
   wire width 2 \sdram_master_p0_wrdata_mask
-  attribute \src "ls180.v:777.6-777.21"
+  attribute \src "ls180.v:790.6-790.21"
   wire \sdram_max_time0
-  attribute \src "ls180.v:780.6-780.21"
+  attribute \src "ls180.v:793.6-793.21"
   wire \sdram_max_time1
-  attribute \src "ls180.v:759.12-759.23"
+  attribute \src "ls180.v:772.12-772.23"
   wire width 13 \sdram_nop_a
-  attribute \src "ls180.v:760.11-760.23"
+  attribute \src "ls180.v:773.11-773.23"
   wire width 2 \sdram_nop_ba
-  attribute \src "ls180.v:303.6-303.15"
+  attribute \src "ls180.v:316.6-316.15"
   wire \sdram_odt
-  attribute \src "ls180.v:386.5-386.26"
+  attribute \src "ls180.v:399.5-399.26"
   wire \sdram_postponer_count
-  attribute \src "ls180.v:384.6-384.27"
+  attribute \src "ls180.v:397.6-397.27"
   wire \sdram_postponer_req_i
-  attribute \src "ls180.v:385.5-385.26"
+  attribute \src "ls180.v:398.5-398.26"
   wire \sdram_postponer_req_o
-  attribute \src "ls180.v:721.6-721.23"
+  attribute \src "ls180.v:734.6-734.23"
   wire \sdram_ras_allowed
   attribute \src "ls180.v:15.14-15.25"
   wire output 11 \sdram_ras_n
-  attribute \src "ls180.v:306.5-306.13"
+  attribute \src "ls180.v:319.5-319.13"
   wire \sdram_re
-  attribute \src "ls180.v:774.6-774.26"
+  attribute \src "ls180.v:787.6-787.26"
   wire \sdram_read_available
-  attribute \src "ls180.v:304.6-304.19"
+  attribute \src "ls180.v:317.6-317.19"
   wire \sdram_reset_n
-  attribute \src "ls180.v:301.6-301.15"
+  attribute \src "ls180.v:314.6-314.15"
   wire \sdram_sel
-  attribute \src "ls180.v:392.5-392.26"
+  attribute \src "ls180.v:405.5-405.26"
   wire \sdram_sequencer_count
-  attribute \src "ls180.v:391.11-391.34"
+  attribute \src "ls180.v:404.11-404.34"
   wire width 4 \sdram_sequencer_counter
-  attribute \src "ls180.v:388.6-388.27"
+  attribute \src "ls180.v:401.6-401.27"
   wire \sdram_sequencer_done0
-  attribute \src "ls180.v:390.5-390.26"
+  attribute \src "ls180.v:403.5-403.26"
   wire \sdram_sequencer_done1
-  attribute \src "ls180.v:387.5-387.27"
+  attribute \src "ls180.v:400.5-400.27"
   wire \sdram_sequencer_start0
-  attribute \src "ls180.v:389.6-389.28"
+  attribute \src "ls180.v:402.6-402.28"
   wire \sdram_sequencer_start1
-  attribute \src "ls180.v:278.6-278.26"
+  attribute \src "ls180.v:291.6-291.26"
   wire \sdram_slave_p0_act_n
-  attribute \src "ls180.v:269.13-269.35"
+  attribute \src "ls180.v:282.13-282.35"
   wire width 13 \sdram_slave_p0_address
-  attribute \src "ls180.v:270.12-270.31"
+  attribute \src "ls180.v:283.12-283.31"
   wire width 2 \sdram_slave_p0_bank
-  attribute \src "ls180.v:271.6-271.26"
+  attribute \src "ls180.v:284.6-284.26"
   wire \sdram_slave_p0_cas_n
-  attribute \src "ls180.v:275.6-275.24"
+  attribute \src "ls180.v:288.6-288.24"
   wire \sdram_slave_p0_cke
-  attribute \src "ls180.v:272.6-272.25"
+  attribute \src "ls180.v:285.6-285.25"
   wire \sdram_slave_p0_cs_n
-  attribute \src "ls180.v:276.6-276.24"
+  attribute \src "ls180.v:289.6-289.24"
   wire \sdram_slave_p0_odt
-  attribute \src "ls180.v:273.6-273.26"
+  attribute \src "ls180.v:286.6-286.26"
   wire \sdram_slave_p0_ras_n
-  attribute \src "ls180.v:283.12-283.33"
+  attribute \src "ls180.v:296.12-296.33"
   wire width 16 \sdram_slave_p0_rddata
-  attribute \src "ls180.v:282.6-282.30"
+  attribute \src "ls180.v:295.6-295.30"
   wire \sdram_slave_p0_rddata_en
-  attribute \src "ls180.v:284.5-284.32"
+  attribute \src "ls180.v:297.5-297.32"
   wire \sdram_slave_p0_rddata_valid
-  attribute \src "ls180.v:277.6-277.28"
+  attribute \src "ls180.v:290.6-290.28"
   wire \sdram_slave_p0_reset_n
-  attribute \src "ls180.v:274.6-274.25"
+  attribute \src "ls180.v:287.6-287.25"
   wire \sdram_slave_p0_we_n
-  attribute \src "ls180.v:279.13-279.34"
+  attribute \src "ls180.v:292.13-292.34"
   wire width 16 \sdram_slave_p0_wrdata
-  attribute \src "ls180.v:280.6-280.30"
+  attribute \src "ls180.v:293.6-293.30"
   wire \sdram_slave_p0_wrdata_en
-  attribute \src "ls180.v:281.12-281.38"
+  attribute \src "ls180.v:294.12-294.38"
   wire width 2 \sdram_slave_p0_wrdata_mask
-  attribute \src "ls180.v:319.12-319.24"
+  attribute \src "ls180.v:332.12-332.24"
   wire width 16 \sdram_status
-  attribute \src "ls180.v:762.5-762.19"
+  attribute \src "ls180.v:775.5-775.19"
   wire \sdram_steerer0
-  attribute \src "ls180.v:763.5-763.19"
+  attribute \src "ls180.v:776.5-776.19"
   wire \sdram_steerer1
-  attribute \src "ls180.v:761.11-761.28"
+  attribute \src "ls180.v:774.11-774.28"
   wire width 2 \sdram_steerer_sel
-  attribute \src "ls180.v:305.11-305.24"
+  attribute \src "ls180.v:318.11-318.24"
   wire width 4 \sdram_storage
-  attribute \src "ls180.v:770.5-770.24"
+  attribute \src "ls180.v:783.5-783.24"
   wire \sdram_tccdcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:769.32-769.51"
+  attribute \src "ls180.v:782.32-782.51"
   wire \sdram_tccdcon_ready
-  attribute \src "ls180.v:768.6-768.25"
+  attribute \src "ls180.v:781.6-781.25"
   wire \sdram_tccdcon_valid
   attribute \no_retiming "true"
-  attribute \src "ls180.v:767.32-767.51"
+  attribute \src "ls180.v:780.32-780.51"
   wire \sdram_tfawcon_ready
-  attribute \src "ls180.v:766.6-766.25"
+  attribute \src "ls180.v:779.6-779.25"
   wire \sdram_tfawcon_valid
-  attribute \src "ls180.v:778.11-778.22"
+  attribute \src "ls180.v:791.11-791.22"
   wire width 5 \sdram_time0
-  attribute \src "ls180.v:781.11-781.22"
+  attribute \src "ls180.v:794.11-794.22"
   wire width 4 \sdram_time1
-  attribute \src "ls180.v:381.12-381.30"
+  attribute \src "ls180.v:394.12-394.30"
   wire width 10 \sdram_timer_count0
-  attribute \src "ls180.v:383.11-383.29"
+  attribute \src "ls180.v:396.11-396.29"
   wire width 10 \sdram_timer_count1
-  attribute \src "ls180.v:380.6-380.23"
+  attribute \src "ls180.v:393.6-393.23"
   wire \sdram_timer_done0
-  attribute \src "ls180.v:382.6-382.23"
+  attribute \src "ls180.v:395.6-395.23"
   wire \sdram_timer_done1
-  attribute \src "ls180.v:379.6-379.22"
+  attribute \src "ls180.v:392.6-392.22"
   wire \sdram_timer_wait
   attribute \no_retiming "true"
-  attribute \src "ls180.v:765.32-765.51"
+  attribute \src "ls180.v:778.32-778.51"
   wire \sdram_trrdcon_ready
-  attribute \src "ls180.v:764.6-764.25"
+  attribute \src "ls180.v:777.6-777.25"
   wire \sdram_trrdcon_valid
-  attribute \src "ls180.v:773.11-773.30"
+  attribute \src "ls180.v:786.11-786.30"
   wire width 3 \sdram_twtrcon_count
   attribute \no_retiming "true"
-  attribute \src "ls180.v:772.32-772.51"
+  attribute \src "ls180.v:785.32-785.51"
   wire \sdram_twtrcon_ready
-  attribute \src "ls180.v:771.6-771.25"
+  attribute \src "ls180.v:784.6-784.25"
   wire \sdram_twtrcon_valid
-  attribute \src "ls180.v:378.6-378.25"
+  attribute \src "ls180.v:391.6-391.25"
   wire \sdram_wants_refresh
-  attribute \src "ls180.v:320.6-320.14"
+  attribute \src "ls180.v:333.6-333.14"
   wire \sdram_we
   attribute \src "ls180.v:14.14-14.24"
   wire output 10 \sdram_we_n
-  attribute \src "ls180.v:318.5-318.20"
+  attribute \src "ls180.v:331.5-331.20"
   wire \sdram_wrdata_re
-  attribute \src "ls180.v:317.12-317.32"
+  attribute \src "ls180.v:330.12-330.32"
   wire width 16 \sdram_wrdata_storage
-  attribute \src "ls180.v:775.6-775.27"
+  attribute \src "ls180.v:788.6-788.27"
   wire \sdram_write_available
-  attribute \src "ls180.v:1395.6-1395.15"
+  attribute \src "ls180.v:1388.6-1388.15"
   wire \sdrio_clk
-  attribute \src "ls180.v:1396.6-1396.17"
+  attribute \src "ls180.v:1389.6-1389.17"
   wire \sdrio_clk_1
-  attribute \src "ls180.v:1405.6-1405.18"
+  attribute \src "ls180.v:1398.6-1398.18"
   wire \sdrio_clk_10
-  attribute \src "ls180.v:1497.6-1497.19"
+  attribute \src "ls180.v:1490.6-1490.19"
   wire \sdrio_clk_100
-  attribute \src "ls180.v:1498.6-1498.19"
+  attribute \src "ls180.v:1491.6-1491.19"
   wire \sdrio_clk_101
-  attribute \src "ls180.v:1499.6-1499.19"
+  attribute \src "ls180.v:1492.6-1492.19"
   wire \sdrio_clk_102
-  attribute \src "ls180.v:1500.6-1500.19"
+  attribute \src "ls180.v:1493.6-1493.19"
   wire \sdrio_clk_103
-  attribute \src "ls180.v:1406.6-1406.18"
+  attribute \src "ls180.v:1399.6-1399.18"
   wire \sdrio_clk_11
-  attribute \src "ls180.v:1407.6-1407.18"
+  attribute \src "ls180.v:1400.6-1400.18"
   wire \sdrio_clk_12
-  attribute \src "ls180.v:1408.6-1408.18"
+  attribute \src "ls180.v:1401.6-1401.18"
   wire \sdrio_clk_13
-  attribute \src "ls180.v:1409.6-1409.18"
+  attribute \src "ls180.v:1402.6-1402.18"
   wire \sdrio_clk_14
-  attribute \src "ls180.v:1410.6-1410.18"
+  attribute \src "ls180.v:1403.6-1403.18"
   wire \sdrio_clk_15
-  attribute \src "ls180.v:1411.6-1411.18"
+  attribute \src "ls180.v:1404.6-1404.18"
   wire \sdrio_clk_16
-  attribute \src "ls180.v:1412.6-1412.18"
+  attribute \src "ls180.v:1405.6-1405.18"
   wire \sdrio_clk_17
-  attribute \src "ls180.v:1413.6-1413.18"
+  attribute \src "ls180.v:1406.6-1406.18"
   wire \sdrio_clk_18
-  attribute \src "ls180.v:1414.6-1414.18"
+  attribute \src "ls180.v:1407.6-1407.18"
   wire \sdrio_clk_19
-  attribute \src "ls180.v:1397.6-1397.17"
+  attribute \src "ls180.v:1390.6-1390.17"
   wire \sdrio_clk_2
-  attribute \src "ls180.v:1415.6-1415.18"
+  attribute \src "ls180.v:1408.6-1408.18"
   wire \sdrio_clk_20
-  attribute \src "ls180.v:1416.6-1416.18"
+  attribute \src "ls180.v:1409.6-1409.18"
   wire \sdrio_clk_21
-  attribute \src "ls180.v:1417.6-1417.18"
+  attribute \src "ls180.v:1410.6-1410.18"
   wire \sdrio_clk_22
-  attribute \src "ls180.v:1418.6-1418.18"
+  attribute \src "ls180.v:1411.6-1411.18"
   wire \sdrio_clk_23
-  attribute \src "ls180.v:1419.6-1419.18"
+  attribute \src "ls180.v:1412.6-1412.18"
   wire \sdrio_clk_24
-  attribute \src "ls180.v:1420.6-1420.18"
+  attribute \src "ls180.v:1413.6-1413.18"
   wire \sdrio_clk_25
-  attribute \src "ls180.v:1421.6-1421.18"
+  attribute \src "ls180.v:1414.6-1414.18"
   wire \sdrio_clk_26
-  attribute \src "ls180.v:1422.6-1422.18"
+  attribute \src "ls180.v:1415.6-1415.18"
   wire \sdrio_clk_27
-  attribute \src "ls180.v:1423.6-1423.18"
+  attribute \src "ls180.v:1416.6-1416.18"
   wire \sdrio_clk_28
-  attribute \src "ls180.v:1424.6-1424.18"
+  attribute \src "ls180.v:1417.6-1417.18"
   wire \sdrio_clk_29
-  attribute \src "ls180.v:1398.6-1398.17"
+  attribute \src "ls180.v:1391.6-1391.17"
   wire \sdrio_clk_3
-  attribute \src "ls180.v:1425.6-1425.18"
+  attribute \src "ls180.v:1418.6-1418.18"
   wire \sdrio_clk_30
-  attribute \src "ls180.v:1426.6-1426.18"
+  attribute \src "ls180.v:1419.6-1419.18"
   wire \sdrio_clk_31
-  attribute \src "ls180.v:1427.6-1427.18"
+  attribute \src "ls180.v:1420.6-1420.18"
   wire \sdrio_clk_32
-  attribute \src "ls180.v:1428.6-1428.18"
+  attribute \src "ls180.v:1421.6-1421.18"
   wire \sdrio_clk_33
-  attribute \src "ls180.v:1429.6-1429.18"
+  attribute \src "ls180.v:1422.6-1422.18"
   wire \sdrio_clk_34
-  attribute \src "ls180.v:1430.6-1430.18"
+  attribute \src "ls180.v:1423.6-1423.18"
   wire \sdrio_clk_35
-  attribute \src "ls180.v:1431.6-1431.18"
+  attribute \src "ls180.v:1424.6-1424.18"
   wire \sdrio_clk_36
-  attribute \src "ls180.v:1432.6-1432.18"
+  attribute \src "ls180.v:1425.6-1425.18"
   wire \sdrio_clk_37
-  attribute \src "ls180.v:1433.6-1433.18"
+  attribute \src "ls180.v:1426.6-1426.18"
   wire \sdrio_clk_38
-  attribute \src "ls180.v:1434.6-1434.18"
+  attribute \src "ls180.v:1427.6-1427.18"
   wire \sdrio_clk_39
-  attribute \src "ls180.v:1399.6-1399.17"
+  attribute \src "ls180.v:1392.6-1392.17"
   wire \sdrio_clk_4
-  attribute \src "ls180.v:1435.6-1435.18"
+  attribute \src "ls180.v:1428.6-1428.18"
   wire \sdrio_clk_40
-  attribute \src "ls180.v:1436.6-1436.18"
+  attribute \src "ls180.v:1429.6-1429.18"
   wire \sdrio_clk_41
-  attribute \src "ls180.v:1437.6-1437.18"
+  attribute \src "ls180.v:1430.6-1430.18"
   wire \sdrio_clk_42
-  attribute \src "ls180.v:1438.6-1438.18"
+  attribute \src "ls180.v:1431.6-1431.18"
   wire \sdrio_clk_43
-  attribute \src "ls180.v:1439.6-1439.18"
+  attribute \src "ls180.v:1432.6-1432.18"
   wire \sdrio_clk_44
-  attribute \src "ls180.v:1440.6-1440.18"
+  attribute \src "ls180.v:1433.6-1433.18"
   wire \sdrio_clk_45
-  attribute \src "ls180.v:1441.6-1441.18"
+  attribute \src "ls180.v:1434.6-1434.18"
   wire \sdrio_clk_46
-  attribute \src "ls180.v:1442.6-1442.18"
+  attribute \src "ls180.v:1435.6-1435.18"
   wire \sdrio_clk_47
-  attribute \src "ls180.v:1443.6-1443.18"
+  attribute \src "ls180.v:1436.6-1436.18"
   wire \sdrio_clk_48
-  attribute \src "ls180.v:1444.6-1444.18"
+  attribute \src "ls180.v:1437.6-1437.18"
   wire \sdrio_clk_49
-  attribute \src "ls180.v:1400.6-1400.17"
+  attribute \src "ls180.v:1393.6-1393.17"
   wire \sdrio_clk_5
-  attribute \src "ls180.v:1445.6-1445.18"
+  attribute \src "ls180.v:1438.6-1438.18"
   wire \sdrio_clk_50
-  attribute \src "ls180.v:1446.6-1446.18"
+  attribute \src "ls180.v:1439.6-1439.18"
   wire \sdrio_clk_51
-  attribute \src "ls180.v:1447.6-1447.18"
+  attribute \src "ls180.v:1440.6-1440.18"
   wire \sdrio_clk_52
-  attribute \src "ls180.v:1448.6-1448.18"
+  attribute \src "ls180.v:1441.6-1441.18"
   wire \sdrio_clk_53
-  attribute \src "ls180.v:1449.6-1449.18"
+  attribute \src "ls180.v:1442.6-1442.18"
   wire \sdrio_clk_54
-  attribute \src "ls180.v:1450.6-1450.18"
+  attribute \src "ls180.v:1443.6-1443.18"
   wire \sdrio_clk_55
-  attribute \src "ls180.v:1453.6-1453.18"
+  attribute \src "ls180.v:1446.6-1446.18"
   wire \sdrio_clk_56
-  attribute \src "ls180.v:1454.6-1454.18"
+  attribute \src "ls180.v:1447.6-1447.18"
   wire \sdrio_clk_57
-  attribute \src "ls180.v:1455.6-1455.18"
+  attribute \src "ls180.v:1448.6-1448.18"
   wire \sdrio_clk_58
-  attribute \src "ls180.v:1456.6-1456.18"
+  attribute \src "ls180.v:1449.6-1449.18"
   wire \sdrio_clk_59
-  attribute \src "ls180.v:1401.6-1401.17"
+  attribute \src "ls180.v:1394.6-1394.17"
   wire \sdrio_clk_6
-  attribute \src "ls180.v:1457.6-1457.18"
+  attribute \src "ls180.v:1450.6-1450.18"
   wire \sdrio_clk_60
-  attribute \src "ls180.v:1458.6-1458.18"
+  attribute \src "ls180.v:1451.6-1451.18"
   wire \sdrio_clk_61
-  attribute \src "ls180.v:1459.6-1459.18"
+  attribute \src "ls180.v:1452.6-1452.18"
   wire \sdrio_clk_62
-  attribute \src "ls180.v:1460.6-1460.18"
+  attribute \src "ls180.v:1453.6-1453.18"
   wire \sdrio_clk_63
-  attribute \src "ls180.v:1461.6-1461.18"
+  attribute \src "ls180.v:1454.6-1454.18"
   wire \sdrio_clk_64
-  attribute \src "ls180.v:1462.6-1462.18"
+  attribute \src "ls180.v:1455.6-1455.18"
   wire \sdrio_clk_65
-  attribute \src "ls180.v:1463.6-1463.18"
+  attribute \src "ls180.v:1456.6-1456.18"
   wire \sdrio_clk_66
-  attribute \src "ls180.v:1464.6-1464.18"
+  attribute \src "ls180.v:1457.6-1457.18"
   wire \sdrio_clk_67
-  attribute \src "ls180.v:1465.6-1465.18"
+  attribute \src "ls180.v:1458.6-1458.18"
   wire \sdrio_clk_68
-  attribute \src "ls180.v:1466.6-1466.18"
+  attribute \src "ls180.v:1459.6-1459.18"
   wire \sdrio_clk_69
-  attribute \src "ls180.v:1402.6-1402.17"
+  attribute \src "ls180.v:1395.6-1395.17"
   wire \sdrio_clk_7
-  attribute \src "ls180.v:1467.6-1467.18"
+  attribute \src "ls180.v:1460.6-1460.18"
   wire \sdrio_clk_70
-  attribute \src "ls180.v:1468.6-1468.18"
+  attribute \src "ls180.v:1461.6-1461.18"
   wire \sdrio_clk_71
-  attribute \src "ls180.v:1469.6-1469.18"
+  attribute \src "ls180.v:1462.6-1462.18"
   wire \sdrio_clk_72
-  attribute \src "ls180.v:1470.6-1470.18"
+  attribute \src "ls180.v:1463.6-1463.18"
   wire \sdrio_clk_73
-  attribute \src "ls180.v:1471.6-1471.18"
+  attribute \src "ls180.v:1464.6-1464.18"
   wire \sdrio_clk_74
-  attribute \src "ls180.v:1472.6-1472.18"
+  attribute \src "ls180.v:1465.6-1465.18"
   wire \sdrio_clk_75
-  attribute \src "ls180.v:1473.6-1473.18"
+  attribute \src "ls180.v:1466.6-1466.18"
   wire \sdrio_clk_76
-  attribute \src "ls180.v:1474.6-1474.18"
+  attribute \src "ls180.v:1467.6-1467.18"
   wire \sdrio_clk_77
-  attribute \src "ls180.v:1475.6-1475.18"
+  attribute \src "ls180.v:1468.6-1468.18"
   wire \sdrio_clk_78
-  attribute \src "ls180.v:1476.6-1476.18"
+  attribute \src "ls180.v:1469.6-1469.18"
   wire \sdrio_clk_79
-  attribute \src "ls180.v:1403.6-1403.17"
+  attribute \src "ls180.v:1396.6-1396.17"
   wire \sdrio_clk_8
-  attribute \src "ls180.v:1477.6-1477.18"
+  attribute \src "ls180.v:1470.6-1470.18"
   wire \sdrio_clk_80
-  attribute \src "ls180.v:1478.6-1478.18"
+  attribute \src "ls180.v:1471.6-1471.18"
   wire \sdrio_clk_81
-  attribute \src "ls180.v:1479.6-1479.18"
+  attribute \src "ls180.v:1472.6-1472.18"
   wire \sdrio_clk_82
-  attribute \src "ls180.v:1480.6-1480.18"
+  attribute \src "ls180.v:1473.6-1473.18"
   wire \sdrio_clk_83
-  attribute \src "ls180.v:1481.6-1481.18"
+  attribute \src "ls180.v:1474.6-1474.18"
   wire \sdrio_clk_84
-  attribute \src "ls180.v:1482.6-1482.18"
+  attribute \src "ls180.v:1475.6-1475.18"
   wire \sdrio_clk_85
-  attribute \src "ls180.v:1483.6-1483.18"
+  attribute \src "ls180.v:1476.6-1476.18"
   wire \sdrio_clk_86
-  attribute \src "ls180.v:1484.6-1484.18"
+  attribute \src "ls180.v:1477.6-1477.18"
   wire \sdrio_clk_87
-  attribute \src "ls180.v:1485.6-1485.18"
+  attribute \src "ls180.v:1478.6-1478.18"
   wire \sdrio_clk_88
-  attribute \src "ls180.v:1486.6-1486.18"
+  attribute \src "ls180.v:1479.6-1479.18"
   wire \sdrio_clk_89
-  attribute \src "ls180.v:1404.6-1404.17"
+  attribute \src "ls180.v:1397.6-1397.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:1487.6-1487.18"
+  attribute \src "ls180.v:1480.6-1480.18"
   wire \sdrio_clk_90
-  attribute \src "ls180.v:1488.6-1488.18"
+  attribute \src "ls180.v:1481.6-1481.18"
   wire \sdrio_clk_91
-  attribute \src "ls180.v:1489.6-1489.18"
+  attribute \src "ls180.v:1482.6-1482.18"
   wire \sdrio_clk_92
-  attribute \src "ls180.v:1490.6-1490.18"
+  attribute \src "ls180.v:1483.6-1483.18"
   wire \sdrio_clk_93
-  attribute \src "ls180.v:1491.6-1491.18"
+  attribute \src "ls180.v:1484.6-1484.18"
   wire \sdrio_clk_94
-  attribute \src "ls180.v:1492.6-1492.18"
+  attribute \src "ls180.v:1485.6-1485.18"
   wire \sdrio_clk_95
-  attribute \src "ls180.v:1493.6-1493.18"
+  attribute \src "ls180.v:1486.6-1486.18"
   wire \sdrio_clk_96
-  attribute \src "ls180.v:1494.6-1494.18"
+  attribute \src "ls180.v:1487.6-1487.18"
   wire \sdrio_clk_97
-  attribute \src "ls180.v:1495.6-1495.18"
+  attribute \src "ls180.v:1488.6-1488.18"
   wire \sdrio_clk_98
-  attribute \src "ls180.v:1496.6-1496.18"
+  attribute \src "ls180.v:1489.6-1489.18"
   wire \sdrio_clk_99
-  attribute \src "ls180.v:810.5-810.42"
-  wire \socbushandler_converted_interface_ack
-  attribute \src "ls180.v:804.13-804.50"
-  wire width 30 \socbushandler_converted_interface_adr
-  attribute \src "ls180.v:813.12-813.49"
-  wire width 2 \socbushandler_converted_interface_bte
-  attribute \src "ls180.v:812.12-812.49"
-  wire width 3 \socbushandler_converted_interface_cti
-  attribute \src "ls180.v:808.6-808.43"
-  wire \socbushandler_converted_interface_cyc
-  attribute \src "ls180.v:806.13-806.52"
-  wire width 64 \socbushandler_converted_interface_dat_r
-  attribute \src "ls180.v:805.13-805.52"
-  wire width 64 \socbushandler_converted_interface_dat_w
-  attribute \src "ls180.v:814.5-814.42"
-  wire \socbushandler_converted_interface_err
-  attribute \src "ls180.v:807.12-807.49"
-  wire width 8 \socbushandler_converted_interface_sel
-  attribute \src "ls180.v:809.6-809.43"
-  wire \socbushandler_converted_interface_stb
-  attribute \src "ls180.v:811.6-811.42"
-  wire \socbushandler_converted_interface_we
-  attribute \src "ls180.v:816.5-816.26"
-  wire \socbushandler_counter
-  attribute \src "ls180.v:1017.5-1017.61"
-  wire \socbushandler_counter_subfragments_converter2_next_value
-  attribute \src "ls180.v:1018.5-1018.64"
-  wire \socbushandler_counter_subfragments_converter2_next_value_ce
-  attribute \src "ls180.v:818.12-818.31"
-  wire width 64 \socbushandler_dat_r
-  attribute \src "ls180.v:817.6-817.25"
-  wire \socbushandler_reset
-  attribute \src "ls180.v:815.5-815.23"
-  wire \socbushandler_skip
-  attribute \src "ls180.v:22.14-22.27"
-  wire output 18 \spimaster_clk
-  attribute \src "ls180.v:24.14-24.28"
-  wire output 20 \spimaster_cs_n
-  attribute \src "ls180.v:25.13-25.27"
-  wire input 21 \spimaster_miso
-  attribute \src "ls180.v:23.14-23.28"
-  wire output 19 \spimaster_mosi
-  attribute \src "ls180.v:1022.11-1022.47"
+  attribute \src "ls180.v:26.14-26.27"
+  wire output 22 \spimaster_clk
+  attribute \src "ls180.v:28.14-28.28"
+  wire output 24 \spimaster_cs_n
+  attribute \src "ls180.v:29.13-29.27"
+  wire input 25 \spimaster_miso
+  attribute \src "ls180.v:27.14-27.28"
+  wire output 23 \spimaster_mosi
+  attribute \src "ls180.v:1023.11-1023.47"
   wire width 3 \subfragments_bankmachine0_next_state
-  attribute \src "ls180.v:1021.11-1021.42"
+  attribute \src "ls180.v:1022.11-1022.42"
   wire width 3 \subfragments_bankmachine0_state
-  attribute \src "ls180.v:1024.11-1024.47"
+  attribute \src "ls180.v:1025.11-1025.47"
   wire width 3 \subfragments_bankmachine1_next_state
-  attribute \src "ls180.v:1023.11-1023.42"
+  attribute \src "ls180.v:1024.11-1024.42"
   wire width 3 \subfragments_bankmachine1_state
-  attribute \src "ls180.v:1026.11-1026.47"
+  attribute \src "ls180.v:1027.11-1027.47"
   wire width 3 \subfragments_bankmachine2_next_state
-  attribute \src "ls180.v:1025.11-1025.42"
+  attribute \src "ls180.v:1026.11-1026.42"
   wire width 3 \subfragments_bankmachine2_state
-  attribute \src "ls180.v:1028.11-1028.47"
+  attribute \src "ls180.v:1029.11-1029.47"
   wire width 3 \subfragments_bankmachine3_next_state
-  attribute \src "ls180.v:1027.11-1027.42"
+  attribute \src "ls180.v:1028.11-1028.42"
   wire width 3 \subfragments_bankmachine3_state
-  attribute \src "ls180.v:1008.5-1008.39"
+  attribute \src "ls180.v:1009.5-1009.39"
   wire \subfragments_converter0_next_state
-  attribute \src "ls180.v:1007.5-1007.34"
+  attribute \src "ls180.v:1008.5-1008.34"
   wire \subfragments_converter0_state
-  attribute \src "ls180.v:1012.5-1012.39"
+  attribute \src "ls180.v:1013.5-1013.39"
   wire \subfragments_converter1_next_state
-  attribute \src "ls180.v:1011.5-1011.34"
+  attribute \src "ls180.v:1012.5-1012.34"
   wire \subfragments_converter1_state
-  attribute \src "ls180.v:1016.5-1016.39"
+  attribute \src "ls180.v:1017.5-1017.39"
   wire \subfragments_converter2_next_state
-  attribute \src "ls180.v:1015.5-1015.34"
+  attribute \src "ls180.v:1016.5-1016.34"
   wire \subfragments_converter2_state
-  attribute \src "ls180.v:1043.5-1043.25"
-  wire \subfragments_locked0
   attribute \src "ls180.v:1044.5-1044.25"
-  wire \subfragments_locked1
+  wire \subfragments_locked0
   attribute \src "ls180.v:1045.5-1045.25"
-  wire \subfragments_locked2
+  wire \subfragments_locked1
   attribute \src "ls180.v:1046.5-1046.25"
+  wire \subfragments_locked2
+  attribute \src "ls180.v:1047.5-1047.25"
   wire \subfragments_locked3
-  attribute \src "ls180.v:1030.11-1030.46"
+  attribute \src "ls180.v:1031.11-1031.46"
   wire width 3 \subfragments_multiplexer_next_state
-  attribute \src "ls180.v:1029.11-1029.41"
+  attribute \src "ls180.v:1030.11-1030.41"
   wire width 3 \subfragments_multiplexer_state
-  attribute \src "ls180.v:1048.5-1048.41"
-  wire \subfragments_new_master_rdata_valid0
   attribute \src "ls180.v:1049.5-1049.41"
-  wire \subfragments_new_master_rdata_valid1
+  wire \subfragments_new_master_rdata_valid0
   attribute \src "ls180.v:1050.5-1050.41"
-  wire \subfragments_new_master_rdata_valid2
+  wire \subfragments_new_master_rdata_valid1
   attribute \src "ls180.v:1051.5-1051.41"
+  wire \subfragments_new_master_rdata_valid2
+  attribute \src "ls180.v:1052.5-1052.41"
   wire \subfragments_new_master_rdata_valid3
-  attribute \src "ls180.v:1047.5-1047.40"
+  attribute \src "ls180.v:1048.5-1048.40"
   wire \subfragments_new_master_wdata_ready
-  attribute \src "ls180.v:1053.5-1053.28"
+  attribute \src "ls180.v:1054.5-1054.28"
   wire \subfragments_next_state
-  attribute \src "ls180.v:1020.11-1020.44"
+  attribute \src "ls180.v:1021.11-1021.44"
   wire width 2 \subfragments_refresher_next_state
-  attribute \src "ls180.v:1019.11-1019.39"
+  attribute \src "ls180.v:1020.11-1020.39"
   wire width 2 \subfragments_refresher_state
-  attribute \src "ls180.v:1033.6-1033.33"
+  attribute \src "ls180.v:1034.6-1034.33"
   wire \subfragments_roundrobin0_ce
-  attribute \src "ls180.v:1032.6-1032.36"
+  attribute \src "ls180.v:1033.6-1033.36"
   wire \subfragments_roundrobin0_grant
-  attribute \src "ls180.v:1031.6-1031.38"
+  attribute \src "ls180.v:1032.6-1032.38"
   wire \subfragments_roundrobin0_request
-  attribute \src "ls180.v:1036.6-1036.33"
+  attribute \src "ls180.v:1037.6-1037.33"
   wire \subfragments_roundrobin1_ce
-  attribute \src "ls180.v:1035.6-1035.36"
+  attribute \src "ls180.v:1036.6-1036.36"
   wire \subfragments_roundrobin1_grant
-  attribute \src "ls180.v:1034.6-1034.38"
+  attribute \src "ls180.v:1035.6-1035.38"
   wire \subfragments_roundrobin1_request
-  attribute \src "ls180.v:1039.6-1039.33"
+  attribute \src "ls180.v:1040.6-1040.33"
   wire \subfragments_roundrobin2_ce
-  attribute \src "ls180.v:1038.6-1038.36"
+  attribute \src "ls180.v:1039.6-1039.36"
   wire \subfragments_roundrobin2_grant
-  attribute \src "ls180.v:1037.6-1037.38"
+  attribute \src "ls180.v:1038.6-1038.38"
   wire \subfragments_roundrobin2_request
-  attribute \src "ls180.v:1042.6-1042.33"
+  attribute \src "ls180.v:1043.6-1043.33"
   wire \subfragments_roundrobin3_ce
-  attribute \src "ls180.v:1041.6-1041.36"
+  attribute \src "ls180.v:1042.6-1042.36"
   wire \subfragments_roundrobin3_grant
-  attribute \src "ls180.v:1040.6-1040.38"
+  attribute \src "ls180.v:1041.6-1041.38"
   wire \subfragments_roundrobin3_request
-  attribute \src "ls180.v:1052.5-1052.23"
+  attribute \src "ls180.v:1053.5-1053.23"
   wire \subfragments_state
   attribute \src "ls180.v:33.13-33.20"
   wire input 29 \sys_clk
-  attribute \src "ls180.v:232.6-232.15"
+  attribute \src "ls180.v:245.6-245.15"
   wire \sys_clk_1
   attribute \src "ls180.v:35.19-35.31"
   wire width 2 input 31 \sys_clksel_i
@@ -246588,253 +246362,259 @@ module \ls180
   wire output 33 \sys_pll_lck_o
   attribute \src "ls180.v:34.13-34.20"
   wire input 30 \sys_rst
-  attribute \src "ls180.v:233.6-233.15"
+  attribute \src "ls180.v:246.6-246.15"
   wire \sys_rst_1
-  attribute \src "ls180.v:1356.5-1356.19"
+  attribute \src "ls180.v:1349.5-1349.19"
   wire \t_array_muxed0
-  attribute \src "ls180.v:1357.5-1357.19"
+  attribute \src "ls180.v:1350.5-1350.19"
   wire \t_array_muxed1
-  attribute \src "ls180.v:1358.5-1358.19"
+  attribute \src "ls180.v:1351.5-1351.19"
   wire \t_array_muxed2
-  attribute \src "ls180.v:1365.5-1365.19"
+  attribute \src "ls180.v:1358.5-1358.19"
   wire \t_array_muxed3
-  attribute \src "ls180.v:1366.5-1366.19"
+  attribute \src "ls180.v:1359.5-1359.19"
   wire \t_array_muxed4
-  attribute \src "ls180.v:1367.5-1367.19"
+  attribute \src "ls180.v:1360.5-1360.19"
   wire \t_array_muxed5
-  attribute \src "ls180.v:872.5-872.13"
+  attribute \src "ls180.v:873.5-873.13"
   wire \tx_clear
-  attribute \src "ls180.v:924.11-924.26"
+  attribute \src "ls180.v:925.11-925.26"
   wire width 4 \tx_fifo_consume
-  attribute \src "ls180.v:929.6-929.21"
+  attribute \src "ls180.v:930.6-930.21"
   wire \tx_fifo_do_read
-  attribute \src "ls180.v:935.6-935.27"
+  attribute \src "ls180.v:936.6-936.27"
   wire \tx_fifo_fifo_in_first
-  attribute \src "ls180.v:936.6-936.26"
+  attribute \src "ls180.v:937.6-937.26"
   wire \tx_fifo_fifo_in_last
-  attribute \src "ls180.v:934.12-934.40"
+  attribute \src "ls180.v:935.12-935.40"
   wire width 8 \tx_fifo_fifo_in_payload_data
-  attribute \src "ls180.v:938.6-938.28"
+  attribute \src "ls180.v:939.6-939.28"
   wire \tx_fifo_fifo_out_first
-  attribute \src "ls180.v:939.6-939.27"
+  attribute \src "ls180.v:940.6-940.27"
   wire \tx_fifo_fifo_out_last
-  attribute \src "ls180.v:937.12-937.41"
+  attribute \src "ls180.v:938.12-938.41"
   wire width 8 \tx_fifo_fifo_out_payload_data
-  attribute \src "ls180.v:921.11-921.25"
+  attribute \src "ls180.v:922.11-922.25"
   wire width 5 \tx_fifo_level0
-  attribute \src "ls180.v:933.12-933.26"
+  attribute \src "ls180.v:934.12-934.26"
   wire width 5 \tx_fifo_level1
-  attribute \src "ls180.v:923.11-923.26"
+  attribute \src "ls180.v:924.11-924.26"
   wire width 4 \tx_fifo_produce
-  attribute \src "ls180.v:930.12-930.30"
+  attribute \src "ls180.v:931.12-931.30"
   wire width 4 \tx_fifo_rdport_adr
-  attribute \src "ls180.v:931.12-931.32"
+  attribute \src "ls180.v:932.12-932.32"
   wire width 10 \tx_fifo_rdport_dat_r
-  attribute \src "ls180.v:932.6-932.23"
+  attribute \src "ls180.v:933.6-933.23"
   wire \tx_fifo_rdport_re
-  attribute \src "ls180.v:913.6-913.16"
+  attribute \src "ls180.v:914.6-914.16"
   wire \tx_fifo_re
-  attribute \src "ls180.v:914.5-914.21"
+  attribute \src "ls180.v:915.5-915.21"
   wire \tx_fifo_readable
-  attribute \src "ls180.v:922.5-922.20"
+  attribute \src "ls180.v:923.5-923.20"
   wire \tx_fifo_replace
-  attribute \src "ls180.v:905.5-905.23"
+  attribute \src "ls180.v:906.5-906.23"
   wire \tx_fifo_sink_first
-  attribute \src "ls180.v:906.5-906.22"
+  attribute \src "ls180.v:907.5-907.22"
   wire \tx_fifo_sink_last
-  attribute \src "ls180.v:907.12-907.37"
+  attribute \src "ls180.v:908.12-908.37"
   wire width 8 \tx_fifo_sink_payload_data
-  attribute \src "ls180.v:904.6-904.24"
+  attribute \src "ls180.v:905.6-905.24"
   wire \tx_fifo_sink_ready
-  attribute \src "ls180.v:903.6-903.24"
+  attribute \src "ls180.v:904.6-904.24"
   wire \tx_fifo_sink_valid
-  attribute \src "ls180.v:910.6-910.26"
+  attribute \src "ls180.v:911.6-911.26"
   wire \tx_fifo_source_first
-  attribute \src "ls180.v:911.6-911.25"
+  attribute \src "ls180.v:912.6-912.25"
   wire \tx_fifo_source_last
-  attribute \src "ls180.v:912.12-912.39"
+  attribute \src "ls180.v:913.12-913.39"
   wire width 8 \tx_fifo_source_payload_data
-  attribute \src "ls180.v:909.6-909.26"
+  attribute \src "ls180.v:910.6-910.26"
   wire \tx_fifo_source_ready
-  attribute \src "ls180.v:908.6-908.26"
+  attribute \src "ls180.v:909.6-909.26"
   wire \tx_fifo_source_valid
-  attribute \src "ls180.v:919.12-919.32"
+  attribute \src "ls180.v:920.12-920.32"
   wire width 10 \tx_fifo_syncfifo_din
-  attribute \src "ls180.v:920.12-920.33"
+  attribute \src "ls180.v:921.12-921.33"
   wire width 10 \tx_fifo_syncfifo_dout
-  attribute \src "ls180.v:917.6-917.25"
+  attribute \src "ls180.v:918.6-918.25"
   wire \tx_fifo_syncfifo_re
-  attribute \src "ls180.v:918.6-918.31"
+  attribute \src "ls180.v:919.6-919.31"
   wire \tx_fifo_syncfifo_readable
-  attribute \src "ls180.v:915.6-915.25"
+  attribute \src "ls180.v:916.6-916.25"
   wire \tx_fifo_syncfifo_we
-  attribute \src "ls180.v:916.6-916.31"
+  attribute \src "ls180.v:917.6-917.31"
   wire \tx_fifo_syncfifo_writable
-  attribute \src "ls180.v:925.11-925.29"
+  attribute \src "ls180.v:926.11-926.29"
   wire width 4 \tx_fifo_wrport_adr
-  attribute \src "ls180.v:926.12-926.32"
+  attribute \src "ls180.v:927.12-927.32"
   wire width 10 \tx_fifo_wrport_dat_r
-  attribute \src "ls180.v:928.12-928.32"
+  attribute \src "ls180.v:929.12-929.32"
   wire width 10 \tx_fifo_wrport_dat_w
-  attribute \src "ls180.v:927.6-927.23"
+  attribute \src "ls180.v:928.6-928.23"
   wire \tx_fifo_wrport_we
-  attribute \src "ls180.v:873.5-873.19"
+  attribute \src "ls180.v:874.5-874.19"
   wire \tx_old_trigger
-  attribute \src "ls180.v:870.5-870.15"
+  attribute \src "ls180.v:871.5-871.15"
   wire \tx_pending
-  attribute \src "ls180.v:869.6-869.15"
+  attribute \src "ls180.v:870.6-870.15"
   wire \tx_status
-  attribute \src "ls180.v:871.6-871.16"
+  attribute \src "ls180.v:872.6-872.16"
   wire \tx_trigger
-  attribute \src "ls180.v:889.6-889.20"
+  attribute \src "ls180.v:890.6-890.20"
   wire \txempty_status
-  attribute \src "ls180.v:890.6-890.16"
+  attribute \src "ls180.v:891.6-891.16"
   wire \txempty_we
-  attribute \src "ls180.v:864.6-864.19"
+  attribute \src "ls180.v:865.6-865.19"
   wire \txfull_status
-  attribute \src "ls180.v:865.6-865.15"
+  attribute \src "ls180.v:866.6-866.15"
   wire \txfull_we
-  attribute \src "ls180.v:854.12-854.41"
+  attribute \src "ls180.v:855.12-855.41"
   wire width 32 \uart_phy_phase_accumulator_rx
-  attribute \src "ls180.v:844.12-844.41"
+  attribute \src "ls180.v:845.12-845.41"
   wire width 32 \uart_phy_phase_accumulator_tx
-  attribute \src "ls180.v:837.5-837.16"
+  attribute \src "ls180.v:838.5-838.16"
   wire \uart_phy_re
-  attribute \src "ls180.v:855.6-855.17"
+  attribute \src "ls180.v:856.6-856.17"
   wire \uart_phy_rx
-  attribute \src "ls180.v:858.11-858.31"
+  attribute \src "ls180.v:859.11-859.31"
   wire width 4 \uart_phy_rx_bitcount
-  attribute \src "ls180.v:859.5-859.21"
+  attribute \src "ls180.v:860.5-860.21"
   wire \uart_phy_rx_busy
-  attribute \src "ls180.v:856.5-856.18"
+  attribute \src "ls180.v:857.5-857.18"
   wire \uart_phy_rx_r
-  attribute \src "ls180.v:857.11-857.26"
+  attribute \src "ls180.v:858.11-858.26"
   wire width 8 \uart_phy_rx_reg
-  attribute \src "ls180.v:840.6-840.25"
+  attribute \src "ls180.v:841.6-841.25"
   wire \uart_phy_sink_first
-  attribute \src "ls180.v:841.6-841.24"
+  attribute \src "ls180.v:842.6-842.24"
   wire \uart_phy_sink_last
-  attribute \src "ls180.v:842.12-842.38"
+  attribute \src "ls180.v:843.12-843.38"
   wire width 8 \uart_phy_sink_payload_data
-  attribute \src "ls180.v:839.5-839.24"
+  attribute \src "ls180.v:840.5-840.24"
   wire \uart_phy_sink_ready
-  attribute \src "ls180.v:838.6-838.25"
+  attribute \src "ls180.v:839.6-839.25"
   wire \uart_phy_sink_valid
-  attribute \src "ls180.v:850.5-850.26"
+  attribute \src "ls180.v:851.5-851.26"
   wire \uart_phy_source_first
-  attribute \src "ls180.v:851.5-851.25"
+  attribute \src "ls180.v:852.5-852.25"
   wire \uart_phy_source_last
-  attribute \src "ls180.v:852.11-852.39"
+  attribute \src "ls180.v:853.11-853.39"
   wire width 8 \uart_phy_source_payload_data
-  attribute \src "ls180.v:849.6-849.27"
+  attribute \src "ls180.v:850.6-850.27"
   wire \uart_phy_source_ready
-  attribute \src "ls180.v:848.5-848.26"
+  attribute \src "ls180.v:849.5-849.26"
   wire \uart_phy_source_valid
-  attribute \src "ls180.v:836.12-836.28"
+  attribute \src "ls180.v:837.12-837.28"
   wire width 32 \uart_phy_storage
-  attribute \src "ls180.v:846.11-846.31"
+  attribute \src "ls180.v:847.11-847.31"
   wire width 4 \uart_phy_tx_bitcount
-  attribute \src "ls180.v:847.5-847.21"
+  attribute \src "ls180.v:848.5-848.21"
   wire \uart_phy_tx_busy
-  attribute \src "ls180.v:845.11-845.26"
+  attribute \src "ls180.v:846.11-846.26"
   wire width 8 \uart_phy_tx_reg
-  attribute \src "ls180.v:853.5-853.27"
+  attribute \src "ls180.v:854.5-854.27"
   wire \uart_phy_uart_clk_rxen
-  attribute \src "ls180.v:843.5-843.27"
+  attribute \src "ls180.v:844.5-844.27"
   wire \uart_phy_uart_clk_txen
-  attribute \src "ls180.v:9.13-9.20"
-  wire input 5 \uart_rx
-  attribute \src "ls180.v:895.6-895.21"
+  attribute \src "ls180.v:6.13-6.20"
+  wire input 2 \uart_rx
+  attribute \src "ls180.v:896.6-896.21"
   wire \uart_sink_first
-  attribute \src "ls180.v:896.6-896.20"
+  attribute \src "ls180.v:897.6-897.20"
   wire \uart_sink_last
-  attribute \src "ls180.v:897.12-897.34"
+  attribute \src "ls180.v:898.12-898.34"
   wire width 8 \uart_sink_payload_data
-  attribute \src "ls180.v:894.6-894.21"
+  attribute \src "ls180.v:895.6-895.21"
   wire \uart_sink_ready
-  attribute \src "ls180.v:893.6-893.21"
+  attribute \src "ls180.v:894.6-894.21"
   wire \uart_sink_valid
-  attribute \src "ls180.v:900.6-900.23"
+  attribute \src "ls180.v:901.6-901.23"
   wire \uart_source_first
-  attribute \src "ls180.v:901.6-901.22"
+  attribute \src "ls180.v:902.6-902.22"
   wire \uart_source_last
-  attribute \src "ls180.v:902.12-902.36"
+  attribute \src "ls180.v:903.12-903.36"
   wire width 8 \uart_source_payload_data
-  attribute \src "ls180.v:899.6-899.23"
+  attribute \src "ls180.v:900.6-900.23"
   wire \uart_source_ready
-  attribute \src "ls180.v:898.6-898.23"
+  attribute \src "ls180.v:899.6-899.23"
   wire \uart_source_valid
-  attribute \src "ls180.v:8.13-8.20"
-  wire input 4 \uart_tx
-  attribute \src "ls180.v:802.5-802.17"
+  attribute \src "ls180.v:5.13-5.20"
+  wire input 1 \uart_tx
+  attribute \src "ls180.v:815.5-815.17"
   wire \wb_sdram_ack
-  attribute \src "ls180.v:796.12-796.24"
+  attribute \src "ls180.v:809.13-809.25"
   wire width 30 \wb_sdram_adr
-  attribute \src "ls180.v:800.5-800.17"
+  attribute \src "ls180.v:818.12-818.24"
+  wire width 2 \wb_sdram_bte
+  attribute \src "ls180.v:817.12-817.24"
+  wire width 3 \wb_sdram_cti
+  attribute \src "ls180.v:813.6-813.18"
   wire \wb_sdram_cyc
-  attribute \src "ls180.v:798.13-798.27"
+  attribute \src "ls180.v:811.13-811.27"
   wire width 32 \wb_sdram_dat_r
-  attribute \src "ls180.v:797.12-797.26"
+  attribute \src "ls180.v:810.13-810.27"
   wire width 32 \wb_sdram_dat_w
-  attribute \src "ls180.v:799.11-799.23"
+  attribute \src "ls180.v:819.5-819.17"
+  wire \wb_sdram_err
+  attribute \src "ls180.v:812.12-812.24"
   wire width 4 \wb_sdram_sel
-  attribute \src "ls180.v:801.5-801.17"
+  attribute \src "ls180.v:814.6-814.18"
   wire \wb_sdram_stb
-  attribute \src "ls180.v:803.5-803.16"
+  attribute \src "ls180.v:816.6-816.17"
   wire \wb_sdram_we
-  attribute \src "ls180.v:832.5-832.19"
+  attribute \src "ls180.v:833.5-833.19"
   wire \wdata_consumed
-  attribute \src "ls180.v:5508.12-5508.15"
-  memory width 64 size 64 \mem
-  attribute \src "ls180.v:5536.12-5536.17"
-  memory width 64 size 16 \mem_1
-  attribute \src "ls180.v:5564.12-5564.19"
+  attribute \src "ls180.v:5493.12-5493.15"
+  memory width 32 size 128 \mem
+  attribute \src "ls180.v:5513.12-5513.17"
+  memory width 32 size 32 \mem_1
+  attribute \src "ls180.v:5533.12-5533.19"
   memory width 25 size 8 \storage
-  attribute \src "ls180.v:5578.12-5578.21"
+  attribute \src "ls180.v:5547.12-5547.21"
   memory width 25 size 8 \storage_1
-  attribute \src "ls180.v:5592.12-5592.21"
+  attribute \src "ls180.v:5561.12-5561.21"
   memory width 25 size 8 \storage_2
-  attribute \src "ls180.v:5606.12-5606.21"
+  attribute \src "ls180.v:5575.12-5575.21"
   memory width 25 size 8 \storage_3
-  attribute \src "ls180.v:5620.11-5620.20"
+  attribute \src "ls180.v:5589.11-5589.20"
   memory width 10 size 16 \storage_4
-  attribute \src "ls180.v:5637.11-5637.20"
+  attribute \src "ls180.v:5606.11-5606.20"
   memory width 10 size 16 \storage_5
-  attribute \src "ls180.v:1568.64-1568.89"
-  cell $add $add$ls180.v:1568$33
+  attribute \src "ls180.v:1561.76-1561.113"
+  cell $add $add$ls180.v:1561$25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter0_counter
+    connect \A \libresocsim_converter0_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:1568$33_Y
+    connect \Y $add$ls180.v:1561$25_Y
   end
-  attribute \src "ls180.v:1628.64-1628.89"
-  cell $add $add$ls180.v:1628$44
+  attribute \src "ls180.v:1621.76-1621.113"
+  cell $add $add$ls180.v:1621$36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter1_counter
+    connect \A \libresocsim_converter1_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:1628$44_Y
+    connect \Y $add$ls180.v:1621$36_Y
   end
-  attribute \src "ls180.v:1688.67-1688.95"
-  cell $add $add$ls180.v:1688$55
+  attribute \src "ls180.v:1681.76-1681.113"
+  cell $add $add$ls180.v:1681$47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_counter
+    connect \A \libresocsim_converter2_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:1688$55_Y
+    connect \Y $add$ls180.v:1681$47_Y
   end
-  attribute \src "ls180.v:2839.52-2839.76"
-  cell $add $add$ls180.v:2839$585
+  attribute \src "ls180.v:2824.52-2824.76"
+  cell $add $add$ls180.v:2824$553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -246842,10 +246622,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \converter_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:2839$585_Y
+    connect \Y $add$ls180.v:2824$553_Y
   end
-  attribute \src "ls180.v:2939.26-2939.59"
-  cell $add $add$ls180.v:2939$631
+  attribute \src "ls180.v:2924.26-2924.59"
+  cell $add $add$ls180.v:2924$599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -246853,10 +246633,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \tx_fifo_level0
     connect \B \tx_fifo_readable
-    connect \Y $add$ls180.v:2939$631_Y
+    connect \Y $add$ls180.v:2924$599_Y
   end
-  attribute \src "ls180.v:2969.26-2969.59"
-  cell $add $add$ls180.v:2969$642
+  attribute \src "ls180.v:2954.26-2954.59"
+  cell $add $add$ls180.v:2954$610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -246864,10 +246644,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \rx_fifo_level0
     connect \B \rx_fifo_readable
-    connect \Y $add$ls180.v:2969$642_Y
+    connect \Y $add$ls180.v:2954$610_Y
   end
-  attribute \src "ls180.v:4372.31-4372.60"
-  cell $add $add$ls180.v:4372$1288
+  attribute \src "ls180.v:4357.31-4357.60"
+  cell $add $add$ls180.v:4357$1256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -246875,10 +246655,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \libresocsim_bus_errors
     connect \B 1'1
-    connect \Y $add$ls180.v:4372$1288_Y
+    connect \Y $add$ls180.v:4357$1256_Y
   end
-  attribute \src "ls180.v:4461.32-4461.62"
-  cell $add $add$ls180.v:4461$1312
+  attribute \src "ls180.v:4446.32-4446.62"
+  cell $add $add$ls180.v:4446$1280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -246886,10 +246666,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_sequencer_counter
     connect \B 1'1
-    connect \Y $add$ls180.v:4461$1312_Y
+    connect \Y $add$ls180.v:4446$1280_Y
   end
-  attribute \src "ls180.v:4478.55-4478.109"
-  cell $add $add$ls180.v:4478$1316
+  attribute \src "ls180.v:4463.55-4463.109"
+  cell $add $add$ls180.v:4463$1284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246897,10 +246677,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4478$1316_Y
+    connect \Y $add$ls180.v:4463$1284_Y
   end
-  attribute \src "ls180.v:4481.55-4481.109"
-  cell $add $add$ls180.v:4481$1317
+  attribute \src "ls180.v:4466.55-4466.109"
+  cell $add $add$ls180.v:4466$1285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246908,10 +246688,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4481$1317_Y
+    connect \Y $add$ls180.v:4466$1285_Y
   end
-  attribute \src "ls180.v:4485.54-4485.106"
-  cell $add $add$ls180.v:4485$1322
+  attribute \src "ls180.v:4470.54-4470.106"
+  cell $add $add$ls180.v:4470$1290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -246919,10 +246699,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:4485$1322_Y
+    connect \Y $add$ls180.v:4470$1290_Y
   end
-  attribute \src "ls180.v:4524.55-4524.109"
-  cell $add $add$ls180.v:4524$1332
+  attribute \src "ls180.v:4509.55-4509.109"
+  cell $add $add$ls180.v:4509$1300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246930,10 +246710,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4524$1332_Y
+    connect \Y $add$ls180.v:4509$1300_Y
   end
-  attribute \src "ls180.v:4527.55-4527.109"
-  cell $add $add$ls180.v:4527$1333
+  attribute \src "ls180.v:4512.55-4512.109"
+  cell $add $add$ls180.v:4512$1301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246941,10 +246721,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4527$1333_Y
+    connect \Y $add$ls180.v:4512$1301_Y
   end
-  attribute \src "ls180.v:4531.54-4531.106"
-  cell $add $add$ls180.v:4531$1338
+  attribute \src "ls180.v:4516.54-4516.106"
+  cell $add $add$ls180.v:4516$1306
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -246952,10 +246732,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:4531$1338_Y
+    connect \Y $add$ls180.v:4516$1306_Y
   end
-  attribute \src "ls180.v:4570.55-4570.109"
-  cell $add $add$ls180.v:4570$1348
+  attribute \src "ls180.v:4555.55-4555.109"
+  cell $add $add$ls180.v:4555$1316
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246963,10 +246743,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4570$1348_Y
+    connect \Y $add$ls180.v:4555$1316_Y
   end
-  attribute \src "ls180.v:4573.55-4573.109"
-  cell $add $add$ls180.v:4573$1349
+  attribute \src "ls180.v:4558.55-4558.109"
+  cell $add $add$ls180.v:4558$1317
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246974,10 +246754,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4573$1349_Y
+    connect \Y $add$ls180.v:4558$1317_Y
   end
-  attribute \src "ls180.v:4577.54-4577.106"
-  cell $add $add$ls180.v:4577$1354
+  attribute \src "ls180.v:4562.54-4562.106"
+  cell $add $add$ls180.v:4562$1322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -246985,10 +246765,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:4577$1354_Y
+    connect \Y $add$ls180.v:4562$1322_Y
   end
-  attribute \src "ls180.v:4616.55-4616.109"
-  cell $add $add$ls180.v:4616$1364
+  attribute \src "ls180.v:4601.55-4601.109"
+  cell $add $add$ls180.v:4601$1332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -246996,10 +246776,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4616$1364_Y
+    connect \Y $add$ls180.v:4601$1332_Y
   end
-  attribute \src "ls180.v:4619.55-4619.109"
-  cell $add $add$ls180.v:4619$1365
+  attribute \src "ls180.v:4604.55-4604.109"
+  cell $add $add$ls180.v:4604$1333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -247007,10 +246787,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4619$1365_Y
+    connect \Y $add$ls180.v:4604$1333_Y
   end
-  attribute \src "ls180.v:4623.54-4623.106"
-  cell $add $add$ls180.v:4623$1370
+  attribute \src "ls180.v:4608.54-4608.106"
+  cell $add $add$ls180.v:4608$1338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247018,10 +246798,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $add$ls180.v:4623$1370_Y
+    connect \Y $add$ls180.v:4608$1338_Y
   end
-  attribute \src "ls180.v:4853.29-4853.56"
-  cell $add $add$ls180.v:4853$1424
+  attribute \src "ls180.v:4838.29-4838.56"
+  cell $add $add$ls180.v:4838$1392
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247029,10 +246809,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \uart_phy_tx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:4853$1424_Y
+    connect \Y $add$ls180.v:4838$1392_Y
   end
-  attribute \src "ls180.v:4869.63-4869.111"
-  cell $add $add$ls180.v:4869$1427
+  attribute \src "ls180.v:4854.63-4854.111"
+  cell $add $add$ls180.v:4854$1395
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -247040,10 +246820,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \uart_phy_phase_accumulator_tx
     connect \B \uart_phy_storage
-    connect \Y $add$ls180.v:4869$1427_Y
+    connect \Y $add$ls180.v:4854$1395_Y
   end
-  attribute \src "ls180.v:4882.29-4882.56"
-  cell $add $add$ls180.v:4882$1431
+  attribute \src "ls180.v:4867.29-4867.56"
+  cell $add $add$ls180.v:4867$1399
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247051,10 +246831,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \uart_phy_rx_bitcount
     connect \B 1'1
-    connect \Y $add$ls180.v:4882$1431_Y
+    connect \Y $add$ls180.v:4867$1399_Y
   end
-  attribute \src "ls180.v:4901.63-4901.111"
-  cell $add $add$ls180.v:4901$1434
+  attribute \src "ls180.v:4886.63-4886.111"
+  cell $add $add$ls180.v:4886$1402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -247062,10 +246842,10 @@ module \ls180
     parameter \Y_WIDTH 33
     connect \A \uart_phy_phase_accumulator_rx
     connect \B \uart_phy_storage
-    connect \Y $add$ls180.v:4901$1434_Y
+    connect \Y $add$ls180.v:4886$1402_Y
   end
-  attribute \src "ls180.v:4927.23-4927.45"
-  cell $add $add$ls180.v:4927$1442
+  attribute \src "ls180.v:4912.23-4912.45"
+  cell $add $add$ls180.v:4912$1410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247073,10 +246853,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \tx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4927$1442_Y
+    connect \Y $add$ls180.v:4912$1410_Y
   end
-  attribute \src "ls180.v:4930.23-4930.45"
-  cell $add $add$ls180.v:4930$1443
+  attribute \src "ls180.v:4915.23-4915.45"
+  cell $add $add$ls180.v:4915$1411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247084,10 +246864,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \tx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4930$1443_Y
+    connect \Y $add$ls180.v:4915$1411_Y
   end
-  attribute \src "ls180.v:4934.23-4934.44"
-  cell $add $add$ls180.v:4934$1448
+  attribute \src "ls180.v:4919.23-4919.44"
+  cell $add $add$ls180.v:4919$1416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -247095,10 +246875,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \tx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:4934$1448_Y
+    connect \Y $add$ls180.v:4919$1416_Y
   end
-  attribute \src "ls180.v:4949.23-4949.45"
-  cell $add $add$ls180.v:4949$1453
+  attribute \src "ls180.v:4934.23-4934.45"
+  cell $add $add$ls180.v:4934$1421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247106,10 +246886,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \rx_fifo_produce
     connect \B 1'1
-    connect \Y $add$ls180.v:4949$1453_Y
+    connect \Y $add$ls180.v:4934$1421_Y
   end
-  attribute \src "ls180.v:4952.23-4952.45"
-  cell $add $add$ls180.v:4952$1454
+  attribute \src "ls180.v:4937.23-4937.45"
+  cell $add $add$ls180.v:4937$1422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -247117,10 +246897,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \rx_fifo_consume
     connect \B 1'1
-    connect \Y $add$ls180.v:4952$1454_Y
+    connect \Y $add$ls180.v:4937$1422_Y
   end
-  attribute \src "ls180.v:4956.23-4956.44"
-  cell $add $add$ls180.v:4956$1459
+  attribute \src "ls180.v:4941.23-4941.44"
+  cell $add $add$ls180.v:4941$1427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -247128,76 +246908,76 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \rx_fifo_level0
     connect \B 1'1
-    connect \Y $add$ls180.v:4956$1459_Y
+    connect \Y $add$ls180.v:4941$1427_Y
   end
-  attribute \src "ls180.v:1562.9-1562.80"
-  cell $and $and$ls180.v:1562$28
+  attribute \src "ls180.v:1555.9-1555.70"
+  cell $and $and$ls180.v:1555$20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface0_converted_interface_stb
-    connect \B \interface0_converted_interface_cyc
-    connect \Y $and$ls180.v:1562$28_Y
+    connect \A \libresocsim_libresoc_ibus_stb
+    connect \B \libresocsim_libresoc_ibus_cyc
+    connect \Y $and$ls180.v:1555$20_Y
   end
-  attribute \src "ls180.v:1580.9-1580.80"
-  cell $and $and$ls180.v:1580$35
+  attribute \src "ls180.v:1573.9-1573.70"
+  cell $and $and$ls180.v:1573$27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface0_converted_interface_stb
-    connect \B \interface0_converted_interface_cyc
-    connect \Y $and$ls180.v:1580$35_Y
+    connect \A \libresocsim_libresoc_ibus_stb
+    connect \B \libresocsim_libresoc_ibus_cyc
+    connect \Y $and$ls180.v:1573$27_Y
   end
-  attribute \src "ls180.v:1622.9-1622.80"
-  cell $and $and$ls180.v:1622$39
+  attribute \src "ls180.v:1615.9-1615.70"
+  cell $and $and$ls180.v:1615$31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface1_converted_interface_stb
-    connect \B \interface1_converted_interface_cyc
-    connect \Y $and$ls180.v:1622$39_Y
+    connect \A \libresocsim_libresoc_dbus_stb
+    connect \B \libresocsim_libresoc_dbus_cyc
+    connect \Y $and$ls180.v:1615$31_Y
   end
-  attribute \src "ls180.v:1640.9-1640.80"
-  cell $and $and$ls180.v:1640$46
+  attribute \src "ls180.v:1633.9-1633.70"
+  cell $and $and$ls180.v:1633$38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface1_converted_interface_stb
-    connect \B \interface1_converted_interface_cyc
-    connect \Y $and$ls180.v:1640$46_Y
+    connect \A \libresocsim_libresoc_dbus_stb
+    connect \B \libresocsim_libresoc_dbus_cyc
+    connect \Y $and$ls180.v:1633$38_Y
   end
-  attribute \src "ls180.v:1682.9-1682.86"
-  cell $and $and$ls180.v:1682$50
+  attribute \src "ls180.v:1675.9-1675.76"
+  cell $and $and$ls180.v:1675$42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_converted_interface_stb
-    connect \B \socbushandler_converted_interface_cyc
-    connect \Y $and$ls180.v:1682$50_Y
+    connect \A \libresocsim_libresoc_jtag_wb_stb
+    connect \B \libresocsim_libresoc_jtag_wb_cyc
+    connect \Y $and$ls180.v:1675$42_Y
   end
-  attribute \src "ls180.v:1700.9-1700.86"
-  cell $and $and$ls180.v:1700$57
+  attribute \src "ls180.v:1693.9-1693.76"
+  cell $and $and$ls180.v:1693$49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_converted_interface_stb
-    connect \B \socbushandler_converted_interface_cyc
-    connect \Y $and$ls180.v:1700$57_Y
+    connect \A \libresocsim_libresoc_jtag_wb_stb
+    connect \B \libresocsim_libresoc_jtag_wb_cyc
+    connect \Y $and$ls180.v:1693$49_Y
   end
-  attribute \src "ls180.v:1710.26-1710.75"
-  cell $and $and$ls180.v:1710$59
+  attribute \src "ls180.v:1703.26-1703.75"
+  cell $and $and$ls180.v:1703$51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247205,32 +246985,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_cyc
     connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1710$59_Y
+    connect \Y $and$ls180.v:1703$51_Y
   end
-  attribute \src "ls180.v:1710.25-1710.101"
-  cell $and $and$ls180.v:1710$60
+  attribute \src "ls180.v:1703.25-1703.101"
+  cell $and $and$ls180.v:1703$52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1710$59_Y
+    connect \A $and$ls180.v:1703$51_Y
     connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1710$60_Y
+    connect \Y $and$ls180.v:1703$52_Y
   end
-  attribute \src "ls180.v:1710.24-1710.131"
-  cell $and $and$ls180.v:1710$61
+  attribute \src "ls180.v:1703.24-1703.131"
+  cell $and $and$ls180.v:1703$53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1710$60_Y
+    connect \A $and$ls180.v:1703$52_Y
     connect \B \libresocsim_ram_bus_sel [0]
-    connect \Y $and$ls180.v:1710$61_Y
+    connect \Y $and$ls180.v:1703$53_Y
   end
-  attribute \src "ls180.v:1711.26-1711.75"
-  cell $and $and$ls180.v:1711$62
+  attribute \src "ls180.v:1704.26-1704.75"
+  cell $and $and$ls180.v:1704$54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247238,32 +247018,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_cyc
     connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1711$62_Y
+    connect \Y $and$ls180.v:1704$54_Y
   end
-  attribute \src "ls180.v:1711.25-1711.101"
-  cell $and $and$ls180.v:1711$63
+  attribute \src "ls180.v:1704.25-1704.101"
+  cell $and $and$ls180.v:1704$55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1711$62_Y
+    connect \A $and$ls180.v:1704$54_Y
     connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1711$63_Y
+    connect \Y $and$ls180.v:1704$55_Y
   end
-  attribute \src "ls180.v:1711.24-1711.131"
-  cell $and $and$ls180.v:1711$64
+  attribute \src "ls180.v:1704.24-1704.131"
+  cell $and $and$ls180.v:1704$56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1711$63_Y
+    connect \A $and$ls180.v:1704$55_Y
     connect \B \libresocsim_ram_bus_sel [1]
-    connect \Y $and$ls180.v:1711$64_Y
+    connect \Y $and$ls180.v:1704$56_Y
   end
-  attribute \src "ls180.v:1712.26-1712.75"
-  cell $and $and$ls180.v:1712$65
+  attribute \src "ls180.v:1705.26-1705.75"
+  cell $and $and$ls180.v:1705$57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247271,32 +247051,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_cyc
     connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1712$65_Y
+    connect \Y $and$ls180.v:1705$57_Y
   end
-  attribute \src "ls180.v:1712.25-1712.101"
-  cell $and $and$ls180.v:1712$66
+  attribute \src "ls180.v:1705.25-1705.101"
+  cell $and $and$ls180.v:1705$58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1712$65_Y
+    connect \A $and$ls180.v:1705$57_Y
     connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1712$66_Y
+    connect \Y $and$ls180.v:1705$58_Y
   end
-  attribute \src "ls180.v:1712.24-1712.131"
-  cell $and $and$ls180.v:1712$67
+  attribute \src "ls180.v:1705.24-1705.131"
+  cell $and $and$ls180.v:1705$59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1712$66_Y
+    connect \A $and$ls180.v:1705$58_Y
     connect \B \libresocsim_ram_bus_sel [2]
-    connect \Y $and$ls180.v:1712$67_Y
+    connect \Y $and$ls180.v:1705$59_Y
   end
-  attribute \src "ls180.v:1713.26-1713.75"
-  cell $and $and$ls180.v:1713$68
+  attribute \src "ls180.v:1706.26-1706.75"
+  cell $and $and$ls180.v:1706$60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247304,164 +247084,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_cyc
     connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1713$68_Y
+    connect \Y $and$ls180.v:1706$60_Y
   end
-  attribute \src "ls180.v:1713.25-1713.101"
-  cell $and $and$ls180.v:1713$69
+  attribute \src "ls180.v:1706.25-1706.101"
+  cell $and $and$ls180.v:1706$61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1713$68_Y
+    connect \A $and$ls180.v:1706$60_Y
     connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1713$69_Y
+    connect \Y $and$ls180.v:1706$61_Y
   end
-  attribute \src "ls180.v:1713.24-1713.131"
-  cell $and $and$ls180.v:1713$70
+  attribute \src "ls180.v:1706.24-1706.131"
+  cell $and $and$ls180.v:1706$62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1713$69_Y
+    connect \A $and$ls180.v:1706$61_Y
     connect \B \libresocsim_ram_bus_sel [3]
-    connect \Y $and$ls180.v:1713$70_Y
-  end
-  attribute \src "ls180.v:1714.26-1714.75"
-  cell $and $and$ls180.v:1714$71
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \libresocsim_ram_bus_cyc
-    connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1714$71_Y
-  end
-  attribute \src "ls180.v:1714.25-1714.101"
-  cell $and $and$ls180.v:1714$72
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1714$71_Y
-    connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1714$72_Y
-  end
-  attribute \src "ls180.v:1714.24-1714.131"
-  cell $and $and$ls180.v:1714$73
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1714$72_Y
-    connect \B \libresocsim_ram_bus_sel [4]
-    connect \Y $and$ls180.v:1714$73_Y
-  end
-  attribute \src "ls180.v:1715.26-1715.75"
-  cell $and $and$ls180.v:1715$74
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \libresocsim_ram_bus_cyc
-    connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1715$74_Y
-  end
-  attribute \src "ls180.v:1715.25-1715.101"
-  cell $and $and$ls180.v:1715$75
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1715$74_Y
-    connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1715$75_Y
-  end
-  attribute \src "ls180.v:1715.24-1715.131"
-  cell $and $and$ls180.v:1715$76
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1715$75_Y
-    connect \B \libresocsim_ram_bus_sel [5]
-    connect \Y $and$ls180.v:1715$76_Y
-  end
-  attribute \src "ls180.v:1716.26-1716.75"
-  cell $and $and$ls180.v:1716$77
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \libresocsim_ram_bus_cyc
-    connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1716$77_Y
+    connect \Y $and$ls180.v:1706$62_Y
   end
-  attribute \src "ls180.v:1716.25-1716.101"
-  cell $and $and$ls180.v:1716$78
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1716$77_Y
-    connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1716$78_Y
-  end
-  attribute \src "ls180.v:1716.24-1716.131"
-  cell $and $and$ls180.v:1716$79
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1716$78_Y
-    connect \B \libresocsim_ram_bus_sel [6]
-    connect \Y $and$ls180.v:1716$79_Y
-  end
-  attribute \src "ls180.v:1717.26-1717.75"
-  cell $and $and$ls180.v:1717$80
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \libresocsim_ram_bus_cyc
-    connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:1717$80_Y
-  end
-  attribute \src "ls180.v:1717.25-1717.101"
-  cell $and $and$ls180.v:1717$81
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1717$80_Y
-    connect \B \libresocsim_ram_bus_we
-    connect \Y $and$ls180.v:1717$81_Y
-  end
-  attribute \src "ls180.v:1717.24-1717.131"
-  cell $and $and$ls180.v:1717$82
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1717$81_Y
-    connect \B \libresocsim_ram_bus_sel [7]
-    connect \Y $and$ls180.v:1717$82_Y
-  end
-  attribute \src "ls180.v:1726.7-1726.79"
-  cell $and $and$ls180.v:1726$85
+  attribute \src "ls180.v:1715.7-1715.79"
+  cell $and $and$ls180.v:1715$65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247469,10 +247117,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_eventmanager_pending_re
     connect \B \libresocsim_eventmanager_pending_r
-    connect \Y $and$ls180.v:1726$85_Y
+    connect \Y $and$ls180.v:1715$65_Y
   end
-  attribute \src "ls180.v:1731.27-1731.96"
-  cell $and $and$ls180.v:1731$86
+  attribute \src "ls180.v:1720.27-1720.96"
+  cell $and $and$ls180.v:1720$66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247480,10 +247128,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_eventmanager_pending_w
     connect \B \libresocsim_eventmanager_storage
-    connect \Y $and$ls180.v:1731$86_Y
+    connect \Y $and$ls180.v:1720$66_Y
   end
-  attribute \src "ls180.v:1735.18-1735.59"
-  cell $and $and$ls180.v:1735$88
+  attribute \src "ls180.v:1724.18-1724.59"
+  cell $and $and$ls180.v:1724$68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247491,32 +247139,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_cyc
     connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1735$88_Y
+    connect \Y $and$ls180.v:1724$68_Y
   end
-  attribute \src "ls180.v:1735.17-1735.81"
-  cell $and $and$ls180.v:1735$89
+  attribute \src "ls180.v:1724.17-1724.81"
+  cell $and $and$ls180.v:1724$69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1735$88_Y
+    connect \A $and$ls180.v:1724$68_Y
     connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1735$89_Y
+    connect \Y $and$ls180.v:1724$69_Y
   end
-  attribute \src "ls180.v:1735.16-1735.107"
-  cell $and $and$ls180.v:1735$90
+  attribute \src "ls180.v:1724.16-1724.107"
+  cell $and $and$ls180.v:1724$70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1735$89_Y
+    connect \A $and$ls180.v:1724$69_Y
     connect \B \ram_bus_ram_bus_sel [0]
-    connect \Y $and$ls180.v:1735$90_Y
+    connect \Y $and$ls180.v:1724$70_Y
   end
-  attribute \src "ls180.v:1736.18-1736.59"
-  cell $and $and$ls180.v:1736$91
+  attribute \src "ls180.v:1725.18-1725.59"
+  cell $and $and$ls180.v:1725$71
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247524,32 +247172,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_cyc
     connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1736$91_Y
+    connect \Y $and$ls180.v:1725$71_Y
   end
-  attribute \src "ls180.v:1736.17-1736.81"
-  cell $and $and$ls180.v:1736$92
+  attribute \src "ls180.v:1725.17-1725.81"
+  cell $and $and$ls180.v:1725$72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1736$91_Y
+    connect \A $and$ls180.v:1725$71_Y
     connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1736$92_Y
+    connect \Y $and$ls180.v:1725$72_Y
   end
-  attribute \src "ls180.v:1736.16-1736.107"
-  cell $and $and$ls180.v:1736$93
+  attribute \src "ls180.v:1725.16-1725.107"
+  cell $and $and$ls180.v:1725$73
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1736$92_Y
+    connect \A $and$ls180.v:1725$72_Y
     connect \B \ram_bus_ram_bus_sel [1]
-    connect \Y $and$ls180.v:1736$93_Y
+    connect \Y $and$ls180.v:1725$73_Y
   end
-  attribute \src "ls180.v:1737.18-1737.59"
-  cell $and $and$ls180.v:1737$94
+  attribute \src "ls180.v:1726.18-1726.59"
+  cell $and $and$ls180.v:1726$74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247557,32 +247205,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_cyc
     connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1737$94_Y
+    connect \Y $and$ls180.v:1726$74_Y
   end
-  attribute \src "ls180.v:1737.17-1737.81"
-  cell $and $and$ls180.v:1737$95
+  attribute \src "ls180.v:1726.17-1726.81"
+  cell $and $and$ls180.v:1726$75
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1737$94_Y
+    connect \A $and$ls180.v:1726$74_Y
     connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1737$95_Y
+    connect \Y $and$ls180.v:1726$75_Y
   end
-  attribute \src "ls180.v:1737.16-1737.107"
-  cell $and $and$ls180.v:1737$96
+  attribute \src "ls180.v:1726.16-1726.107"
+  cell $and $and$ls180.v:1726$76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1737$95_Y
+    connect \A $and$ls180.v:1726$75_Y
     connect \B \ram_bus_ram_bus_sel [2]
-    connect \Y $and$ls180.v:1737$96_Y
+    connect \Y $and$ls180.v:1726$76_Y
   end
-  attribute \src "ls180.v:1738.18-1738.59"
-  cell $and $and$ls180.v:1738$97
+  attribute \src "ls180.v:1727.18-1727.59"
+  cell $and $and$ls180.v:1727$77
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247590,164 +247238,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_cyc
     connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1738$97_Y
+    connect \Y $and$ls180.v:1727$77_Y
   end
-  attribute \src "ls180.v:1738.17-1738.81"
-  cell $and $and$ls180.v:1738$98
+  attribute \src "ls180.v:1727.17-1727.81"
+  cell $and $and$ls180.v:1727$78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1738$97_Y
+    connect \A $and$ls180.v:1727$77_Y
     connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1738$98_Y
+    connect \Y $and$ls180.v:1727$78_Y
   end
-  attribute \src "ls180.v:1738.16-1738.107"
-  cell $and $and$ls180.v:1738$99
+  attribute \src "ls180.v:1727.16-1727.107"
+  cell $and $and$ls180.v:1727$79
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1738$98_Y
+    connect \A $and$ls180.v:1727$78_Y
     connect \B \ram_bus_ram_bus_sel [3]
-    connect \Y $and$ls180.v:1738$99_Y
-  end
-  attribute \src "ls180.v:1739.18-1739.59"
-  cell $and $and$ls180.v:1739$100
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ram_bus_ram_bus_cyc
-    connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1739$100_Y
-  end
-  attribute \src "ls180.v:1739.17-1739.81"
-  cell $and $and$ls180.v:1739$101
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1739$100_Y
-    connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1739$101_Y
-  end
-  attribute \src "ls180.v:1739.16-1739.107"
-  cell $and $and$ls180.v:1739$102
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1739$101_Y
-    connect \B \ram_bus_ram_bus_sel [4]
-    connect \Y $and$ls180.v:1739$102_Y
-  end
-  attribute \src "ls180.v:1740.18-1740.59"
-  cell $and $and$ls180.v:1740$103
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ram_bus_ram_bus_cyc
-    connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1740$103_Y
-  end
-  attribute \src "ls180.v:1740.17-1740.81"
-  cell $and $and$ls180.v:1740$104
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1740$103_Y
-    connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1740$104_Y
-  end
-  attribute \src "ls180.v:1740.16-1740.107"
-  cell $and $and$ls180.v:1740$105
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1740$104_Y
-    connect \B \ram_bus_ram_bus_sel [5]
-    connect \Y $and$ls180.v:1740$105_Y
-  end
-  attribute \src "ls180.v:1741.18-1741.59"
-  cell $and $and$ls180.v:1741$106
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ram_bus_ram_bus_cyc
-    connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1741$106_Y
-  end
-  attribute \src "ls180.v:1741.17-1741.81"
-  cell $and $and$ls180.v:1741$107
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1741$106_Y
-    connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1741$107_Y
-  end
-  attribute \src "ls180.v:1741.16-1741.107"
-  cell $and $and$ls180.v:1741$108
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1741$107_Y
-    connect \B \ram_bus_ram_bus_sel [6]
-    connect \Y $and$ls180.v:1741$108_Y
-  end
-  attribute \src "ls180.v:1742.18-1742.59"
-  cell $and $and$ls180.v:1742$109
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ram_bus_ram_bus_cyc
-    connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:1742$109_Y
-  end
-  attribute \src "ls180.v:1742.17-1742.81"
-  cell $and $and$ls180.v:1742$110
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1742$109_Y
-    connect \B \ram_bus_ram_bus_we
-    connect \Y $and$ls180.v:1742$110_Y
+    connect \Y $and$ls180.v:1727$79_Y
   end
-  attribute \src "ls180.v:1742.16-1742.107"
-  cell $and $and$ls180.v:1742$111
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1742$110_Y
-    connect \B \ram_bus_ram_bus_sel [7]
-    connect \Y $and$ls180.v:1742$111_Y
-  end
-  attribute \src "ls180.v:1859.35-1859.84"
-  cell $and $and$ls180.v:1859$118
+  attribute \src "ls180.v:1844.35-1844.84"
+  cell $and $and$ls180.v:1844$86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247755,10 +247271,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_command_issue_re
     connect \B \sdram_command_storage [4]
-    connect \Y $and$ls180.v:1859$118_Y
+    connect \Y $and$ls180.v:1844$86_Y
   end
-  attribute \src "ls180.v:1860.35-1860.84"
-  cell $and $and$ls180.v:1860$119
+  attribute \src "ls180.v:1845.35-1845.84"
+  cell $and $and$ls180.v:1845$87
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247766,21 +247282,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_command_issue_re
     connect \B \sdram_command_storage [5]
-    connect \Y $and$ls180.v:1860$119_Y
+    connect \Y $and$ls180.v:1845$87_Y
   end
-  attribute \src "ls180.v:1898.33-1898.88"
-  cell $and $and$ls180.v:1898$125
+  attribute \src "ls180.v:1883.33-1883.88"
+  cell $and $and$ls180.v:1883$93
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_done1
-    connect \B $eq$ls180.v:1898$124_Y
-    connect \Y $and$ls180.v:1898$125_Y
+    connect \B $eq$ls180.v:1883$92_Y
+    connect \Y $and$ls180.v:1883$93_Y
   end
-  attribute \src "ls180.v:1952.45-1952.104"
-  cell $and $and$ls180.v:1952$133
+  attribute \src "ls180.v:1937.45-1937.104"
+  cell $and $and$ls180.v:1937$101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247788,21 +247304,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
     connect \B \sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:1952$133_Y
+    connect \Y $and$ls180.v:1937$101_Y
   end
-  attribute \src "ls180.v:1952.44-1952.147"
-  cell $and $and$ls180.v:1952$134
+  attribute \src "ls180.v:1937.44-1937.147"
+  cell $and $and$ls180.v:1937$102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1952$133_Y
+    connect \A $and$ls180.v:1937$101_Y
     connect \B \sdram_bankmachine0_cmd_payload_is_write
-    connect \Y $and$ls180.v:1952$134_Y
+    connect \Y $and$ls180.v:1937$102_Y
   end
-  attribute \src "ls180.v:1953.44-1953.103"
-  cell $and $and$ls180.v:1953$135
+  attribute \src "ls180.v:1938.44-1938.103"
+  cell $and $and$ls180.v:1938$103
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247810,21 +247326,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
     connect \B \sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:1953$135_Y
+    connect \Y $and$ls180.v:1938$103_Y
   end
-  attribute \src "ls180.v:1953.43-1953.134"
-  cell $and $and$ls180.v:1953$136
+  attribute \src "ls180.v:1938.43-1938.134"
+  cell $and $and$ls180.v:1938$104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1953$135_Y
+    connect \A $and$ls180.v:1938$103_Y
     connect \B \sdram_bankmachine0_row_open
-    connect \Y $and$ls180.v:1953$136_Y
+    connect \Y $and$ls180.v:1938$104_Y
   end
-  attribute \src "ls180.v:1954.45-1954.104"
-  cell $and $and$ls180.v:1954$137
+  attribute \src "ls180.v:1939.45-1939.104"
+  cell $and $and$ls180.v:1939$105
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247832,21 +247348,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
     connect \B \sdram_bankmachine0_cmd_ready
-    connect \Y $and$ls180.v:1954$137_Y
+    connect \Y $and$ls180.v:1939$105_Y
   end
-  attribute \src "ls180.v:1954.44-1954.135"
-  cell $and $and$ls180.v:1954$138
+  attribute \src "ls180.v:1939.44-1939.135"
+  cell $and $and$ls180.v:1939$106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:1954$137_Y
+    connect \A $and$ls180.v:1939$105_Y
     connect \B \sdram_bankmachine0_row_open
-    connect \Y $and$ls180.v:1954$138_Y
+    connect \Y $and$ls180.v:1939$106_Y
   end
-  attribute \src "ls180.v:1957.7-1957.104"
-  cell $and $and$ls180.v:1957$140
+  attribute \src "ls180.v:1942.7-1942.104"
+  cell $and $and$ls180.v:1942$108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247854,21 +247370,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:1957$140_Y
+    connect \Y $and$ls180.v:1942$108_Y
   end
-  attribute \src "ls180.v:1986.61-1986.226"
-  cell $and $and$ls180.v:1986$146
+  attribute \src "ls180.v:1971.61-1971.226"
+  cell $and $and$ls180.v:1971$114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
-    connect \B $or$ls180.v:1986$145_Y
-    connect \Y $and$ls180.v:1986$146_Y
+    connect \B $or$ls180.v:1971$113_Y
+    connect \Y $and$ls180.v:1971$114_Y
   end
-  attribute \src "ls180.v:1987.59-1987.172"
-  cell $and $and$ls180.v:1987$147
+  attribute \src "ls180.v:1972.59-1972.172"
+  cell $and $and$ls180.v:1972$115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247876,10 +247392,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
     connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
-    connect \Y $and$ls180.v:1987$147_Y
+    connect \Y $and$ls180.v:1972$115_Y
   end
-  attribute \src "ls180.v:2011.9-2011.76"
-  cell $and $and$ls180.v:2011$153
+  attribute \src "ls180.v:1996.9-1996.76"
+  cell $and $and$ls180.v:1996$121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247887,10 +247403,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_twtpcon_ready
     connect \B \sdram_bankmachine0_trascon_ready
-    connect \Y $and$ls180.v:2011$153_Y
+    connect \Y $and$ls180.v:1996$121_Y
   end
-  attribute \src "ls180.v:2023.9-2023.76"
-  cell $and $and$ls180.v:2023$154
+  attribute \src "ls180.v:2008.9-2008.76"
+  cell $and $and$ls180.v:2008$122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247898,10 +247414,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_twtpcon_ready
     connect \B \sdram_bankmachine0_trascon_ready
-    connect \Y $and$ls180.v:2023$154_Y
+    connect \Y $and$ls180.v:2008$122_Y
   end
-  attribute \src "ls180.v:2073.13-2073.77"
-  cell $and $and$ls180.v:2073$156
+  attribute \src "ls180.v:2058.13-2058.77"
+  cell $and $and$ls180.v:2058$124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247909,10 +247425,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_ready
     connect \B \sdram_bankmachine0_auto_precharge
-    connect \Y $and$ls180.v:2073$156_Y
+    connect \Y $and$ls180.v:2058$124_Y
   end
-  attribute \src "ls180.v:2109.45-2109.104"
-  cell $and $and$ls180.v:2109$163
+  attribute \src "ls180.v:2094.45-2094.104"
+  cell $and $and$ls180.v:2094$131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247920,21 +247436,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
     connect \B \sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:2109$163_Y
+    connect \Y $and$ls180.v:2094$131_Y
   end
-  attribute \src "ls180.v:2109.44-2109.147"
-  cell $and $and$ls180.v:2109$164
+  attribute \src "ls180.v:2094.44-2094.147"
+  cell $and $and$ls180.v:2094$132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2109$163_Y
+    connect \A $and$ls180.v:2094$131_Y
     connect \B \sdram_bankmachine1_cmd_payload_is_write
-    connect \Y $and$ls180.v:2109$164_Y
+    connect \Y $and$ls180.v:2094$132_Y
   end
-  attribute \src "ls180.v:2110.44-2110.103"
-  cell $and $and$ls180.v:2110$165
+  attribute \src "ls180.v:2095.44-2095.103"
+  cell $and $and$ls180.v:2095$133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247942,21 +247458,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
     connect \B \sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:2110$165_Y
+    connect \Y $and$ls180.v:2095$133_Y
   end
-  attribute \src "ls180.v:2110.43-2110.134"
-  cell $and $and$ls180.v:2110$166
+  attribute \src "ls180.v:2095.43-2095.134"
+  cell $and $and$ls180.v:2095$134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2110$165_Y
+    connect \A $and$ls180.v:2095$133_Y
     connect \B \sdram_bankmachine1_row_open
-    connect \Y $and$ls180.v:2110$166_Y
+    connect \Y $and$ls180.v:2095$134_Y
   end
-  attribute \src "ls180.v:2111.45-2111.104"
-  cell $and $and$ls180.v:2111$167
+  attribute \src "ls180.v:2096.45-2096.104"
+  cell $and $and$ls180.v:2096$135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247964,21 +247480,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
     connect \B \sdram_bankmachine1_cmd_ready
-    connect \Y $and$ls180.v:2111$167_Y
+    connect \Y $and$ls180.v:2096$135_Y
   end
-  attribute \src "ls180.v:2111.44-2111.135"
-  cell $and $and$ls180.v:2111$168
+  attribute \src "ls180.v:2096.44-2096.135"
+  cell $and $and$ls180.v:2096$136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2111$167_Y
+    connect \A $and$ls180.v:2096$135_Y
     connect \B \sdram_bankmachine1_row_open
-    connect \Y $and$ls180.v:2111$168_Y
+    connect \Y $and$ls180.v:2096$136_Y
   end
-  attribute \src "ls180.v:2114.7-2114.104"
-  cell $and $and$ls180.v:2114$170
+  attribute \src "ls180.v:2099.7-2099.104"
+  cell $and $and$ls180.v:2099$138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -247986,21 +247502,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:2114$170_Y
+    connect \Y $and$ls180.v:2099$138_Y
   end
-  attribute \src "ls180.v:2143.61-2143.226"
-  cell $and $and$ls180.v:2143$176
+  attribute \src "ls180.v:2128.61-2128.226"
+  cell $and $and$ls180.v:2128$144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
-    connect \B $or$ls180.v:2143$175_Y
-    connect \Y $and$ls180.v:2143$176_Y
+    connect \B $or$ls180.v:2128$143_Y
+    connect \Y $and$ls180.v:2128$144_Y
   end
-  attribute \src "ls180.v:2144.59-2144.172"
-  cell $and $and$ls180.v:2144$177
+  attribute \src "ls180.v:2129.59-2129.172"
+  cell $and $and$ls180.v:2129$145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248008,10 +247524,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
     connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
-    connect \Y $and$ls180.v:2144$177_Y
+    connect \Y $and$ls180.v:2129$145_Y
   end
-  attribute \src "ls180.v:2168.9-2168.76"
-  cell $and $and$ls180.v:2168$183
+  attribute \src "ls180.v:2153.9-2153.76"
+  cell $and $and$ls180.v:2153$151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248019,10 +247535,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_twtpcon_ready
     connect \B \sdram_bankmachine1_trascon_ready
-    connect \Y $and$ls180.v:2168$183_Y
+    connect \Y $and$ls180.v:2153$151_Y
   end
-  attribute \src "ls180.v:2180.9-2180.76"
-  cell $and $and$ls180.v:2180$184
+  attribute \src "ls180.v:2165.9-2165.76"
+  cell $and $and$ls180.v:2165$152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248030,10 +247546,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_twtpcon_ready
     connect \B \sdram_bankmachine1_trascon_ready
-    connect \Y $and$ls180.v:2180$184_Y
+    connect \Y $and$ls180.v:2165$152_Y
   end
-  attribute \src "ls180.v:2230.13-2230.77"
-  cell $and $and$ls180.v:2230$186
+  attribute \src "ls180.v:2215.13-2215.77"
+  cell $and $and$ls180.v:2215$154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248041,10 +247557,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_ready
     connect \B \sdram_bankmachine1_auto_precharge
-    connect \Y $and$ls180.v:2230$186_Y
+    connect \Y $and$ls180.v:2215$154_Y
   end
-  attribute \src "ls180.v:2266.45-2266.104"
-  cell $and $and$ls180.v:2266$193
+  attribute \src "ls180.v:2251.45-2251.104"
+  cell $and $and$ls180.v:2251$161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248052,21 +247568,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
     connect \B \sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:2266$193_Y
+    connect \Y $and$ls180.v:2251$161_Y
   end
-  attribute \src "ls180.v:2266.44-2266.147"
-  cell $and $and$ls180.v:2266$194
+  attribute \src "ls180.v:2251.44-2251.147"
+  cell $and $and$ls180.v:2251$162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2266$193_Y
+    connect \A $and$ls180.v:2251$161_Y
     connect \B \sdram_bankmachine2_cmd_payload_is_write
-    connect \Y $and$ls180.v:2266$194_Y
+    connect \Y $and$ls180.v:2251$162_Y
   end
-  attribute \src "ls180.v:2267.44-2267.103"
-  cell $and $and$ls180.v:2267$195
+  attribute \src "ls180.v:2252.44-2252.103"
+  cell $and $and$ls180.v:2252$163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248074,21 +247590,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
     connect \B \sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:2267$195_Y
+    connect \Y $and$ls180.v:2252$163_Y
   end
-  attribute \src "ls180.v:2267.43-2267.134"
-  cell $and $and$ls180.v:2267$196
+  attribute \src "ls180.v:2252.43-2252.134"
+  cell $and $and$ls180.v:2252$164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2267$195_Y
+    connect \A $and$ls180.v:2252$163_Y
     connect \B \sdram_bankmachine2_row_open
-    connect \Y $and$ls180.v:2267$196_Y
+    connect \Y $and$ls180.v:2252$164_Y
   end
-  attribute \src "ls180.v:2268.45-2268.104"
-  cell $and $and$ls180.v:2268$197
+  attribute \src "ls180.v:2253.45-2253.104"
+  cell $and $and$ls180.v:2253$165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248096,21 +247612,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
     connect \B \sdram_bankmachine2_cmd_ready
-    connect \Y $and$ls180.v:2268$197_Y
+    connect \Y $and$ls180.v:2253$165_Y
   end
-  attribute \src "ls180.v:2268.44-2268.135"
-  cell $and $and$ls180.v:2268$198
+  attribute \src "ls180.v:2253.44-2253.135"
+  cell $and $and$ls180.v:2253$166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2268$197_Y
+    connect \A $and$ls180.v:2253$165_Y
     connect \B \sdram_bankmachine2_row_open
-    connect \Y $and$ls180.v:2268$198_Y
+    connect \Y $and$ls180.v:2253$166_Y
   end
-  attribute \src "ls180.v:2271.7-2271.104"
-  cell $and $and$ls180.v:2271$200
+  attribute \src "ls180.v:2256.7-2256.104"
+  cell $and $and$ls180.v:2256$168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248118,21 +247634,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:2271$200_Y
+    connect \Y $and$ls180.v:2256$168_Y
   end
-  attribute \src "ls180.v:2300.61-2300.226"
-  cell $and $and$ls180.v:2300$206
+  attribute \src "ls180.v:2285.61-2285.226"
+  cell $and $and$ls180.v:2285$174
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
-    connect \B $or$ls180.v:2300$205_Y
-    connect \Y $and$ls180.v:2300$206_Y
+    connect \B $or$ls180.v:2285$173_Y
+    connect \Y $and$ls180.v:2285$174_Y
   end
-  attribute \src "ls180.v:2301.59-2301.172"
-  cell $and $and$ls180.v:2301$207
+  attribute \src "ls180.v:2286.59-2286.172"
+  cell $and $and$ls180.v:2286$175
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248140,10 +247656,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
     connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
-    connect \Y $and$ls180.v:2301$207_Y
+    connect \Y $and$ls180.v:2286$175_Y
   end
-  attribute \src "ls180.v:2325.9-2325.76"
-  cell $and $and$ls180.v:2325$213
+  attribute \src "ls180.v:2310.9-2310.76"
+  cell $and $and$ls180.v:2310$181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248151,10 +247667,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_twtpcon_ready
     connect \B \sdram_bankmachine2_trascon_ready
-    connect \Y $and$ls180.v:2325$213_Y
+    connect \Y $and$ls180.v:2310$181_Y
   end
-  attribute \src "ls180.v:2337.9-2337.76"
-  cell $and $and$ls180.v:2337$214
+  attribute \src "ls180.v:2322.9-2322.76"
+  cell $and $and$ls180.v:2322$182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248162,10 +247678,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_twtpcon_ready
     connect \B \sdram_bankmachine2_trascon_ready
-    connect \Y $and$ls180.v:2337$214_Y
+    connect \Y $and$ls180.v:2322$182_Y
   end
-  attribute \src "ls180.v:2387.13-2387.77"
-  cell $and $and$ls180.v:2387$216
+  attribute \src "ls180.v:2372.13-2372.77"
+  cell $and $and$ls180.v:2372$184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248173,10 +247689,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_ready
     connect \B \sdram_bankmachine2_auto_precharge
-    connect \Y $and$ls180.v:2387$216_Y
+    connect \Y $and$ls180.v:2372$184_Y
   end
-  attribute \src "ls180.v:2423.45-2423.104"
-  cell $and $and$ls180.v:2423$223
+  attribute \src "ls180.v:2408.45-2408.104"
+  cell $and $and$ls180.v:2408$191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248184,21 +247700,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
     connect \B \sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:2423$223_Y
+    connect \Y $and$ls180.v:2408$191_Y
   end
-  attribute \src "ls180.v:2423.44-2423.147"
-  cell $and $and$ls180.v:2423$224
+  attribute \src "ls180.v:2408.44-2408.147"
+  cell $and $and$ls180.v:2408$192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2423$223_Y
+    connect \A $and$ls180.v:2408$191_Y
     connect \B \sdram_bankmachine3_cmd_payload_is_write
-    connect \Y $and$ls180.v:2423$224_Y
+    connect \Y $and$ls180.v:2408$192_Y
   end
-  attribute \src "ls180.v:2424.44-2424.103"
-  cell $and $and$ls180.v:2424$225
+  attribute \src "ls180.v:2409.44-2409.103"
+  cell $and $and$ls180.v:2409$193
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248206,21 +247722,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
     connect \B \sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:2424$225_Y
+    connect \Y $and$ls180.v:2409$193_Y
   end
-  attribute \src "ls180.v:2424.43-2424.134"
-  cell $and $and$ls180.v:2424$226
+  attribute \src "ls180.v:2409.43-2409.134"
+  cell $and $and$ls180.v:2409$194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2424$225_Y
+    connect \A $and$ls180.v:2409$193_Y
     connect \B \sdram_bankmachine3_row_open
-    connect \Y $and$ls180.v:2424$226_Y
+    connect \Y $and$ls180.v:2409$194_Y
   end
-  attribute \src "ls180.v:2425.45-2425.104"
-  cell $and $and$ls180.v:2425$227
+  attribute \src "ls180.v:2410.45-2410.104"
+  cell $and $and$ls180.v:2410$195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248228,21 +247744,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
     connect \B \sdram_bankmachine3_cmd_ready
-    connect \Y $and$ls180.v:2425$227_Y
+    connect \Y $and$ls180.v:2410$195_Y
   end
-  attribute \src "ls180.v:2425.44-2425.135"
-  cell $and $and$ls180.v:2425$228
+  attribute \src "ls180.v:2410.44-2410.135"
+  cell $and $and$ls180.v:2410$196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2425$227_Y
+    connect \A $and$ls180.v:2410$195_Y
     connect \B \sdram_bankmachine3_row_open
-    connect \Y $and$ls180.v:2425$228_Y
+    connect \Y $and$ls180.v:2410$196_Y
   end
-  attribute \src "ls180.v:2428.7-2428.104"
-  cell $and $and$ls180.v:2428$230
+  attribute \src "ls180.v:2413.7-2413.104"
+  cell $and $and$ls180.v:2413$198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248250,21 +247766,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $and$ls180.v:2428$230_Y
+    connect \Y $and$ls180.v:2413$198_Y
   end
-  attribute \src "ls180.v:2457.61-2457.226"
-  cell $and $and$ls180.v:2457$236
+  attribute \src "ls180.v:2442.61-2442.226"
+  cell $and $and$ls180.v:2442$204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
-    connect \B $or$ls180.v:2457$235_Y
-    connect \Y $and$ls180.v:2457$236_Y
+    connect \B $or$ls180.v:2442$203_Y
+    connect \Y $and$ls180.v:2442$204_Y
   end
-  attribute \src "ls180.v:2458.59-2458.172"
-  cell $and $and$ls180.v:2458$237
+  attribute \src "ls180.v:2443.59-2443.172"
+  cell $and $and$ls180.v:2443$205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248272,10 +247788,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
     connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
-    connect \Y $and$ls180.v:2458$237_Y
+    connect \Y $and$ls180.v:2443$205_Y
   end
-  attribute \src "ls180.v:2482.9-2482.76"
-  cell $and $and$ls180.v:2482$243
+  attribute \src "ls180.v:2467.9-2467.76"
+  cell $and $and$ls180.v:2467$211
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248283,10 +247799,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_twtpcon_ready
     connect \B \sdram_bankmachine3_trascon_ready
-    connect \Y $and$ls180.v:2482$243_Y
+    connect \Y $and$ls180.v:2467$211_Y
   end
-  attribute \src "ls180.v:2494.9-2494.76"
-  cell $and $and$ls180.v:2494$244
+  attribute \src "ls180.v:2479.9-2479.76"
+  cell $and $and$ls180.v:2479$212
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248294,10 +247810,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_twtpcon_ready
     connect \B \sdram_bankmachine3_trascon_ready
-    connect \Y $and$ls180.v:2494$244_Y
+    connect \Y $and$ls180.v:2479$212_Y
   end
-  attribute \src "ls180.v:2544.13-2544.77"
-  cell $and $and$ls180.v:2544$246
+  attribute \src "ls180.v:2529.13-2529.77"
+  cell $and $and$ls180.v:2529$214
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248305,10 +247821,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_ready
     connect \B \sdram_bankmachine3_auto_precharge
-    connect \Y $and$ls180.v:2544$246_Y
+    connect \Y $and$ls180.v:2529$214_Y
   end
-  attribute \src "ls180.v:2559.32-2559.87"
-  cell $and $and$ls180.v:2559$247
+  attribute \src "ls180.v:2544.32-2544.87"
+  cell $and $and$ls180.v:2544$215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248316,43 +247832,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2559$247_Y
+    connect \Y $and$ls180.v:2544$215_Y
   end
-  attribute \src "ls180.v:2559.93-2559.163"
-  cell $and $and$ls180.v:2559$249
+  attribute \src "ls180.v:2544.93-2544.163"
+  cell $and $and$ls180.v:2544$217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:2559$248_Y
-    connect \Y $and$ls180.v:2559$249_Y
+    connect \B $not$ls180.v:2544$216_Y
+    connect \Y $and$ls180.v:2544$217_Y
   end
-  attribute \src "ls180.v:2559.92-2559.201"
-  cell $and $and$ls180.v:2559$251
+  attribute \src "ls180.v:2544.92-2544.201"
+  cell $and $and$ls180.v:2544$219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2559$249_Y
-    connect \B $not$ls180.v:2559$250_Y
-    connect \Y $and$ls180.v:2559$251_Y
+    connect \A $and$ls180.v:2544$217_Y
+    connect \B $not$ls180.v:2544$218_Y
+    connect \Y $and$ls180.v:2544$219_Y
   end
-  attribute \src "ls180.v:2559.31-2559.202"
-  cell $and $and$ls180.v:2559$252
+  attribute \src "ls180.v:2544.31-2544.202"
+  cell $and $and$ls180.v:2544$220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2559$247_Y
-    connect \B $and$ls180.v:2559$251_Y
-    connect \Y $and$ls180.v:2559$252_Y
+    connect \A $and$ls180.v:2544$215_Y
+    connect \B $and$ls180.v:2544$219_Y
+    connect \Y $and$ls180.v:2544$220_Y
   end
-  attribute \src "ls180.v:2560.32-2560.87"
-  cell $and $and$ls180.v:2560$253
+  attribute \src "ls180.v:2545.32-2545.87"
+  cell $and $and$ls180.v:2545$221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248360,43 +247876,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2560$253_Y
+    connect \Y $and$ls180.v:2545$221_Y
   end
-  attribute \src "ls180.v:2560.93-2560.163"
-  cell $and $and$ls180.v:2560$255
+  attribute \src "ls180.v:2545.93-2545.163"
+  cell $and $and$ls180.v:2545$223
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:2560$254_Y
-    connect \Y $and$ls180.v:2560$255_Y
+    connect \B $not$ls180.v:2545$222_Y
+    connect \Y $and$ls180.v:2545$223_Y
   end
-  attribute \src "ls180.v:2560.92-2560.201"
-  cell $and $and$ls180.v:2560$257
+  attribute \src "ls180.v:2545.92-2545.201"
+  cell $and $and$ls180.v:2545$225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2560$255_Y
-    connect \B $not$ls180.v:2560$256_Y
-    connect \Y $and$ls180.v:2560$257_Y
+    connect \A $and$ls180.v:2545$223_Y
+    connect \B $not$ls180.v:2545$224_Y
+    connect \Y $and$ls180.v:2545$225_Y
   end
-  attribute \src "ls180.v:2560.31-2560.202"
-  cell $and $and$ls180.v:2560$258
+  attribute \src "ls180.v:2545.31-2545.202"
+  cell $and $and$ls180.v:2545$226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2560$253_Y
-    connect \B $and$ls180.v:2560$257_Y
-    connect \Y $and$ls180.v:2560$258_Y
+    connect \A $and$ls180.v:2545$221_Y
+    connect \B $and$ls180.v:2545$225_Y
+    connect \Y $and$ls180.v:2545$226_Y
   end
-  attribute \src "ls180.v:2561.29-2561.70"
-  cell $and $and$ls180.v:2561$259
+  attribute \src "ls180.v:2546.29-2546.70"
+  cell $and $and$ls180.v:2546$227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248404,10 +247920,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_trrdcon_ready
     connect \B \sdram_tfawcon_ready
-    connect \Y $and$ls180.v:2561$259_Y
+    connect \Y $and$ls180.v:2546$227_Y
   end
-  attribute \src "ls180.v:2562.32-2562.87"
-  cell $and $and$ls180.v:2562$260
+  attribute \src "ls180.v:2547.32-2547.87"
+  cell $and $and$ls180.v:2547$228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248415,21 +247931,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2562$260_Y
+    connect \Y $and$ls180.v:2547$228_Y
   end
-  attribute \src "ls180.v:2562.31-2562.169"
-  cell $and $and$ls180.v:2562$262
+  attribute \src "ls180.v:2547.31-2547.169"
+  cell $and $and$ls180.v:2547$230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2562$260_Y
-    connect \B $or$ls180.v:2562$261_Y
-    connect \Y $and$ls180.v:2562$262_Y
+    connect \A $and$ls180.v:2547$228_Y
+    connect \B $or$ls180.v:2547$229_Y
+    connect \Y $and$ls180.v:2547$230_Y
   end
-  attribute \src "ls180.v:2564.32-2564.87"
-  cell $and $and$ls180.v:2564$263
+  attribute \src "ls180.v:2549.32-2549.87"
+  cell $and $and$ls180.v:2549$231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248437,21 +247953,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2564$263_Y
+    connect \Y $and$ls180.v:2549$231_Y
   end
-  attribute \src "ls180.v:2564.31-2564.128"
-  cell $and $and$ls180.v:2564$264
+  attribute \src "ls180.v:2549.31-2549.128"
+  cell $and $and$ls180.v:2549$232
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2564$263_Y
+    connect \A $and$ls180.v:2549$231_Y
     connect \B \sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:2564$264_Y
+    connect \Y $and$ls180.v:2549$232_Y
   end
-  attribute \src "ls180.v:2565.35-2565.104"
-  cell $and $and$ls180.v:2565$265
+  attribute \src "ls180.v:2550.35-2550.104"
+  cell $and $and$ls180.v:2550$233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248459,10 +247975,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
     connect \B \sdram_bankmachine0_cmd_payload_is_read
-    connect \Y $and$ls180.v:2565$265_Y
+    connect \Y $and$ls180.v:2550$233_Y
   end
-  attribute \src "ls180.v:2565.109-2565.178"
-  cell $and $and$ls180.v:2565$266
+  attribute \src "ls180.v:2550.109-2550.178"
+  cell $and $and$ls180.v:2550$234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248470,10 +247986,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
     connect \B \sdram_bankmachine1_cmd_payload_is_read
-    connect \Y $and$ls180.v:2565$266_Y
+    connect \Y $and$ls180.v:2550$234_Y
   end
-  attribute \src "ls180.v:2565.184-2565.253"
-  cell $and $and$ls180.v:2565$268
+  attribute \src "ls180.v:2550.184-2550.253"
+  cell $and $and$ls180.v:2550$236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248481,10 +247997,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
     connect \B \sdram_bankmachine2_cmd_payload_is_read
-    connect \Y $and$ls180.v:2565$268_Y
+    connect \Y $and$ls180.v:2550$236_Y
   end
-  attribute \src "ls180.v:2565.259-2565.328"
-  cell $and $and$ls180.v:2565$270
+  attribute \src "ls180.v:2550.259-2550.328"
+  cell $and $and$ls180.v:2550$238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248492,10 +248008,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
     connect \B \sdram_bankmachine3_cmd_payload_is_read
-    connect \Y $and$ls180.v:2565$270_Y
+    connect \Y $and$ls180.v:2550$238_Y
   end
-  attribute \src "ls180.v:2566.36-2566.106"
-  cell $and $and$ls180.v:2566$272
+  attribute \src "ls180.v:2551.36-2551.106"
+  cell $and $and$ls180.v:2551$240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248503,10 +248019,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
     connect \B \sdram_bankmachine0_cmd_payload_is_write
-    connect \Y $and$ls180.v:2566$272_Y
+    connect \Y $and$ls180.v:2551$240_Y
   end
-  attribute \src "ls180.v:2566.111-2566.181"
-  cell $and $and$ls180.v:2566$273
+  attribute \src "ls180.v:2551.111-2551.181"
+  cell $and $and$ls180.v:2551$241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248514,10 +248030,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
     connect \B \sdram_bankmachine1_cmd_payload_is_write
-    connect \Y $and$ls180.v:2566$273_Y
+    connect \Y $and$ls180.v:2551$241_Y
   end
-  attribute \src "ls180.v:2566.187-2566.257"
-  cell $and $and$ls180.v:2566$275
+  attribute \src "ls180.v:2551.187-2551.257"
+  cell $and $and$ls180.v:2551$243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248525,10 +248041,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
     connect \B \sdram_bankmachine2_cmd_payload_is_write
-    connect \Y $and$ls180.v:2566$275_Y
+    connect \Y $and$ls180.v:2551$243_Y
   end
-  attribute \src "ls180.v:2566.263-2566.333"
-  cell $and $and$ls180.v:2566$277
+  attribute \src "ls180.v:2551.263-2551.333"
+  cell $and $and$ls180.v:2551$245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248536,10 +248052,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
     connect \B \sdram_bankmachine3_cmd_payload_is_write
-    connect \Y $and$ls180.v:2566$277_Y
+    connect \Y $and$ls180.v:2551$245_Y
   end
-  attribute \src "ls180.v:2573.33-2573.96"
-  cell $and $and$ls180.v:2573$281
+  attribute \src "ls180.v:2558.33-2558.96"
+  cell $and $and$ls180.v:2558$249
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248547,32 +248063,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_refresh_gnt
     connect \B \sdram_bankmachine1_refresh_gnt
-    connect \Y $and$ls180.v:2573$281_Y
+    connect \Y $and$ls180.v:2558$249_Y
   end
-  attribute \src "ls180.v:2573.32-2573.130"
-  cell $and $and$ls180.v:2573$282
+  attribute \src "ls180.v:2558.32-2558.130"
+  cell $and $and$ls180.v:2558$250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2573$281_Y
+    connect \A $and$ls180.v:2558$249_Y
     connect \B \sdram_bankmachine2_refresh_gnt
-    connect \Y $and$ls180.v:2573$282_Y
+    connect \Y $and$ls180.v:2558$250_Y
   end
-  attribute \src "ls180.v:2573.31-2573.164"
-  cell $and $and$ls180.v:2573$283
+  attribute \src "ls180.v:2558.31-2558.164"
+  cell $and $and$ls180.v:2558$251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2573$282_Y
+    connect \A $and$ls180.v:2558$250_Y
     connect \B \sdram_bankmachine3_refresh_gnt
-    connect \Y $and$ls180.v:2573$283_Y
+    connect \Y $and$ls180.v:2558$251_Y
   end
-  attribute \src "ls180.v:2579.67-2579.133"
-  cell $and $and$ls180.v:2579$286
+  attribute \src "ls180.v:2564.67-2564.133"
+  cell $and $and$ls180.v:2564$254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248580,65 +248096,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_cmd
     connect \B \sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:2579$286_Y
+    connect \Y $and$ls180.v:2564$254_Y
   end
-  attribute \src "ls180.v:2579.142-2579.216"
-  cell $and $and$ls180.v:2579$288
+  attribute \src "ls180.v:2564.142-2564.216"
+  cell $and $and$ls180.v:2564$256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_ras
-    connect \B $not$ls180.v:2579$287_Y
-    connect \Y $and$ls180.v:2579$288_Y
+    connect \B $not$ls180.v:2564$255_Y
+    connect \Y $and$ls180.v:2564$256_Y
   end
-  attribute \src "ls180.v:2579.141-2579.256"
-  cell $and $and$ls180.v:2579$290
+  attribute \src "ls180.v:2564.141-2564.256"
+  cell $and $and$ls180.v:2564$258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2579$288_Y
-    connect \B $not$ls180.v:2579$289_Y
-    connect \Y $and$ls180.v:2579$290_Y
+    connect \A $and$ls180.v:2564$256_Y
+    connect \B $not$ls180.v:2564$257_Y
+    connect \Y $and$ls180.v:2564$258_Y
   end
-  attribute \src "ls180.v:2579.66-2579.293"
-  cell $and $and$ls180.v:2579$293
+  attribute \src "ls180.v:2564.66-2564.293"
+  cell $and $and$ls180.v:2564$261
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2579$286_Y
-    connect \B $or$ls180.v:2579$292_Y
-    connect \Y $and$ls180.v:2579$293_Y
+    connect \A $and$ls180.v:2564$254_Y
+    connect \B $or$ls180.v:2564$260_Y
+    connect \Y $and$ls180.v:2564$261_Y
   end
-  attribute \src "ls180.v:2579.298-2579.445"
-  cell $and $and$ls180.v:2579$296
+  attribute \src "ls180.v:2564.298-2564.445"
+  cell $and $and$ls180.v:2564$264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2579$294_Y
-    connect \B $eq$ls180.v:2579$295_Y
-    connect \Y $and$ls180.v:2579$296_Y
+    connect \A $eq$ls180.v:2564$262_Y
+    connect \B $eq$ls180.v:2564$263_Y
+    connect \Y $and$ls180.v:2564$264_Y
   end
-  attribute \src "ls180.v:2579.33-2579.447"
-  cell $and $and$ls180.v:2579$298
+  attribute \src "ls180.v:2564.33-2564.447"
+  cell $and $and$ls180.v:2564$266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
-    connect \B $or$ls180.v:2579$297_Y
-    connect \Y $and$ls180.v:2579$298_Y
+    connect \B $or$ls180.v:2564$265_Y
+    connect \Y $and$ls180.v:2564$266_Y
   end
-  attribute \src "ls180.v:2580.67-2580.133"
-  cell $and $and$ls180.v:2580$299
+  attribute \src "ls180.v:2565.67-2565.133"
+  cell $and $and$ls180.v:2565$267
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248646,65 +248162,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_cmd
     connect \B \sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:2580$299_Y
+    connect \Y $and$ls180.v:2565$267_Y
   end
-  attribute \src "ls180.v:2580.142-2580.216"
-  cell $and $and$ls180.v:2580$301
+  attribute \src "ls180.v:2565.142-2565.216"
+  cell $and $and$ls180.v:2565$269
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_ras
-    connect \B $not$ls180.v:2580$300_Y
-    connect \Y $and$ls180.v:2580$301_Y
+    connect \B $not$ls180.v:2565$268_Y
+    connect \Y $and$ls180.v:2565$269_Y
   end
-  attribute \src "ls180.v:2580.141-2580.256"
-  cell $and $and$ls180.v:2580$303
+  attribute \src "ls180.v:2565.141-2565.256"
+  cell $and $and$ls180.v:2565$271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2580$301_Y
-    connect \B $not$ls180.v:2580$302_Y
-    connect \Y $and$ls180.v:2580$303_Y
+    connect \A $and$ls180.v:2565$269_Y
+    connect \B $not$ls180.v:2565$270_Y
+    connect \Y $and$ls180.v:2565$271_Y
   end
-  attribute \src "ls180.v:2580.66-2580.293"
-  cell $and $and$ls180.v:2580$306
+  attribute \src "ls180.v:2565.66-2565.293"
+  cell $and $and$ls180.v:2565$274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2580$299_Y
-    connect \B $or$ls180.v:2580$305_Y
-    connect \Y $and$ls180.v:2580$306_Y
+    connect \A $and$ls180.v:2565$267_Y
+    connect \B $or$ls180.v:2565$273_Y
+    connect \Y $and$ls180.v:2565$274_Y
   end
-  attribute \src "ls180.v:2580.298-2580.445"
-  cell $and $and$ls180.v:2580$309
+  attribute \src "ls180.v:2565.298-2565.445"
+  cell $and $and$ls180.v:2565$277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2580$307_Y
-    connect \B $eq$ls180.v:2580$308_Y
-    connect \Y $and$ls180.v:2580$309_Y
+    connect \A $eq$ls180.v:2565$275_Y
+    connect \B $eq$ls180.v:2565$276_Y
+    connect \Y $and$ls180.v:2565$277_Y
   end
-  attribute \src "ls180.v:2580.33-2580.447"
-  cell $and $and$ls180.v:2580$311
+  attribute \src "ls180.v:2565.33-2565.447"
+  cell $and $and$ls180.v:2565$279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
-    connect \B $or$ls180.v:2580$310_Y
-    connect \Y $and$ls180.v:2580$311_Y
+    connect \B $or$ls180.v:2565$278_Y
+    connect \Y $and$ls180.v:2565$279_Y
   end
-  attribute \src "ls180.v:2581.67-2581.133"
-  cell $and $and$ls180.v:2581$312
+  attribute \src "ls180.v:2566.67-2566.133"
+  cell $and $and$ls180.v:2566$280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248712,65 +248228,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_cmd
     connect \B \sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:2581$312_Y
+    connect \Y $and$ls180.v:2566$280_Y
   end
-  attribute \src "ls180.v:2581.142-2581.216"
-  cell $and $and$ls180.v:2581$314
+  attribute \src "ls180.v:2566.142-2566.216"
+  cell $and $and$ls180.v:2566$282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_ras
-    connect \B $not$ls180.v:2581$313_Y
-    connect \Y $and$ls180.v:2581$314_Y
+    connect \B $not$ls180.v:2566$281_Y
+    connect \Y $and$ls180.v:2566$282_Y
   end
-  attribute \src "ls180.v:2581.141-2581.256"
-  cell $and $and$ls180.v:2581$316
+  attribute \src "ls180.v:2566.141-2566.256"
+  cell $and $and$ls180.v:2566$284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2581$314_Y
-    connect \B $not$ls180.v:2581$315_Y
-    connect \Y $and$ls180.v:2581$316_Y
+    connect \A $and$ls180.v:2566$282_Y
+    connect \B $not$ls180.v:2566$283_Y
+    connect \Y $and$ls180.v:2566$284_Y
   end
-  attribute \src "ls180.v:2581.66-2581.293"
-  cell $and $and$ls180.v:2581$319
+  attribute \src "ls180.v:2566.66-2566.293"
+  cell $and $and$ls180.v:2566$287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2581$312_Y
-    connect \B $or$ls180.v:2581$318_Y
-    connect \Y $and$ls180.v:2581$319_Y
+    connect \A $and$ls180.v:2566$280_Y
+    connect \B $or$ls180.v:2566$286_Y
+    connect \Y $and$ls180.v:2566$287_Y
   end
-  attribute \src "ls180.v:2581.298-2581.445"
-  cell $and $and$ls180.v:2581$322
+  attribute \src "ls180.v:2566.298-2566.445"
+  cell $and $and$ls180.v:2566$290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2581$320_Y
-    connect \B $eq$ls180.v:2581$321_Y
-    connect \Y $and$ls180.v:2581$322_Y
+    connect \A $eq$ls180.v:2566$288_Y
+    connect \B $eq$ls180.v:2566$289_Y
+    connect \Y $and$ls180.v:2566$290_Y
   end
-  attribute \src "ls180.v:2581.33-2581.447"
-  cell $and $and$ls180.v:2581$324
+  attribute \src "ls180.v:2566.33-2566.447"
+  cell $and $and$ls180.v:2566$292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
-    connect \B $or$ls180.v:2581$323_Y
-    connect \Y $and$ls180.v:2581$324_Y
+    connect \B $or$ls180.v:2566$291_Y
+    connect \Y $and$ls180.v:2566$292_Y
   end
-  attribute \src "ls180.v:2582.67-2582.133"
-  cell $and $and$ls180.v:2582$325
+  attribute \src "ls180.v:2567.67-2567.133"
+  cell $and $and$ls180.v:2567$293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248778,65 +248294,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_cmd
     connect \B \sdram_choose_cmd_want_cmds
-    connect \Y $and$ls180.v:2582$325_Y
+    connect \Y $and$ls180.v:2567$293_Y
   end
-  attribute \src "ls180.v:2582.142-2582.216"
-  cell $and $and$ls180.v:2582$327
+  attribute \src "ls180.v:2567.142-2567.216"
+  cell $and $and$ls180.v:2567$295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_ras
-    connect \B $not$ls180.v:2582$326_Y
-    connect \Y $and$ls180.v:2582$327_Y
+    connect \B $not$ls180.v:2567$294_Y
+    connect \Y $and$ls180.v:2567$295_Y
   end
-  attribute \src "ls180.v:2582.141-2582.256"
-  cell $and $and$ls180.v:2582$329
+  attribute \src "ls180.v:2567.141-2567.256"
+  cell $and $and$ls180.v:2567$297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2582$327_Y
-    connect \B $not$ls180.v:2582$328_Y
-    connect \Y $and$ls180.v:2582$329_Y
+    connect \A $and$ls180.v:2567$295_Y
+    connect \B $not$ls180.v:2567$296_Y
+    connect \Y $and$ls180.v:2567$297_Y
   end
-  attribute \src "ls180.v:2582.66-2582.293"
-  cell $and $and$ls180.v:2582$332
+  attribute \src "ls180.v:2567.66-2567.293"
+  cell $and $and$ls180.v:2567$300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2582$325_Y
-    connect \B $or$ls180.v:2582$331_Y
-    connect \Y $and$ls180.v:2582$332_Y
+    connect \A $and$ls180.v:2567$293_Y
+    connect \B $or$ls180.v:2567$299_Y
+    connect \Y $and$ls180.v:2567$300_Y
   end
-  attribute \src "ls180.v:2582.298-2582.445"
-  cell $and $and$ls180.v:2582$335
+  attribute \src "ls180.v:2567.298-2567.445"
+  cell $and $and$ls180.v:2567$303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2582$333_Y
-    connect \B $eq$ls180.v:2582$334_Y
-    connect \Y $and$ls180.v:2582$335_Y
+    connect \A $eq$ls180.v:2567$301_Y
+    connect \B $eq$ls180.v:2567$302_Y
+    connect \Y $and$ls180.v:2567$303_Y
   end
-  attribute \src "ls180.v:2582.33-2582.447"
-  cell $and $and$ls180.v:2582$337
+  attribute \src "ls180.v:2567.33-2567.447"
+  cell $and $and$ls180.v:2567$305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
-    connect \B $or$ls180.v:2582$336_Y
-    connect \Y $and$ls180.v:2582$337_Y
+    connect \B $or$ls180.v:2567$304_Y
+    connect \Y $and$ls180.v:2567$305_Y
   end
-  attribute \src "ls180.v:2612.67-2612.133"
-  cell $and $and$ls180.v:2612$344
+  attribute \src "ls180.v:2597.67-2597.133"
+  cell $and $and$ls180.v:2597$312
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248844,65 +248360,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_cmd
     connect \B \sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:2612$344_Y
+    connect \Y $and$ls180.v:2597$312_Y
   end
-  attribute \src "ls180.v:2612.142-2612.216"
-  cell $and $and$ls180.v:2612$346
+  attribute \src "ls180.v:2597.142-2597.216"
+  cell $and $and$ls180.v:2597$314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_ras
-    connect \B $not$ls180.v:2612$345_Y
-    connect \Y $and$ls180.v:2612$346_Y
+    connect \B $not$ls180.v:2597$313_Y
+    connect \Y $and$ls180.v:2597$314_Y
   end
-  attribute \src "ls180.v:2612.141-2612.256"
-  cell $and $and$ls180.v:2612$348
+  attribute \src "ls180.v:2597.141-2597.256"
+  cell $and $and$ls180.v:2597$316
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2612$346_Y
-    connect \B $not$ls180.v:2612$347_Y
-    connect \Y $and$ls180.v:2612$348_Y
+    connect \A $and$ls180.v:2597$314_Y
+    connect \B $not$ls180.v:2597$315_Y
+    connect \Y $and$ls180.v:2597$316_Y
   end
-  attribute \src "ls180.v:2612.66-2612.293"
-  cell $and $and$ls180.v:2612$351
+  attribute \src "ls180.v:2597.66-2597.293"
+  cell $and $and$ls180.v:2597$319
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2612$344_Y
-    connect \B $or$ls180.v:2612$350_Y
-    connect \Y $and$ls180.v:2612$351_Y
+    connect \A $and$ls180.v:2597$312_Y
+    connect \B $or$ls180.v:2597$318_Y
+    connect \Y $and$ls180.v:2597$319_Y
   end
-  attribute \src "ls180.v:2612.298-2612.445"
-  cell $and $and$ls180.v:2612$354
+  attribute \src "ls180.v:2597.298-2597.445"
+  cell $and $and$ls180.v:2597$322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2612$352_Y
-    connect \B $eq$ls180.v:2612$353_Y
-    connect \Y $and$ls180.v:2612$354_Y
+    connect \A $eq$ls180.v:2597$320_Y
+    connect \B $eq$ls180.v:2597$321_Y
+    connect \Y $and$ls180.v:2597$322_Y
   end
-  attribute \src "ls180.v:2612.33-2612.447"
-  cell $and $and$ls180.v:2612$356
+  attribute \src "ls180.v:2597.33-2597.447"
+  cell $and $and$ls180.v:2597$324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_valid
-    connect \B $or$ls180.v:2612$355_Y
-    connect \Y $and$ls180.v:2612$356_Y
+    connect \B $or$ls180.v:2597$323_Y
+    connect \Y $and$ls180.v:2597$324_Y
   end
-  attribute \src "ls180.v:2613.67-2613.133"
-  cell $and $and$ls180.v:2613$357
+  attribute \src "ls180.v:2598.67-2598.133"
+  cell $and $and$ls180.v:2598$325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248910,65 +248426,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_cmd
     connect \B \sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:2613$357_Y
+    connect \Y $and$ls180.v:2598$325_Y
   end
-  attribute \src "ls180.v:2613.142-2613.216"
-  cell $and $and$ls180.v:2613$359
+  attribute \src "ls180.v:2598.142-2598.216"
+  cell $and $and$ls180.v:2598$327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_ras
-    connect \B $not$ls180.v:2613$358_Y
-    connect \Y $and$ls180.v:2613$359_Y
+    connect \B $not$ls180.v:2598$326_Y
+    connect \Y $and$ls180.v:2598$327_Y
   end
-  attribute \src "ls180.v:2613.141-2613.256"
-  cell $and $and$ls180.v:2613$361
+  attribute \src "ls180.v:2598.141-2598.256"
+  cell $and $and$ls180.v:2598$329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2613$359_Y
-    connect \B $not$ls180.v:2613$360_Y
-    connect \Y $and$ls180.v:2613$361_Y
+    connect \A $and$ls180.v:2598$327_Y
+    connect \B $not$ls180.v:2598$328_Y
+    connect \Y $and$ls180.v:2598$329_Y
   end
-  attribute \src "ls180.v:2613.66-2613.293"
-  cell $and $and$ls180.v:2613$364
+  attribute \src "ls180.v:2598.66-2598.293"
+  cell $and $and$ls180.v:2598$332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2613$357_Y
-    connect \B $or$ls180.v:2613$363_Y
-    connect \Y $and$ls180.v:2613$364_Y
+    connect \A $and$ls180.v:2598$325_Y
+    connect \B $or$ls180.v:2598$331_Y
+    connect \Y $and$ls180.v:2598$332_Y
   end
-  attribute \src "ls180.v:2613.298-2613.445"
-  cell $and $and$ls180.v:2613$367
+  attribute \src "ls180.v:2598.298-2598.445"
+  cell $and $and$ls180.v:2598$335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2613$365_Y
-    connect \B $eq$ls180.v:2613$366_Y
-    connect \Y $and$ls180.v:2613$367_Y
+    connect \A $eq$ls180.v:2598$333_Y
+    connect \B $eq$ls180.v:2598$334_Y
+    connect \Y $and$ls180.v:2598$335_Y
   end
-  attribute \src "ls180.v:2613.33-2613.447"
-  cell $and $and$ls180.v:2613$369
+  attribute \src "ls180.v:2598.33-2598.447"
+  cell $and $and$ls180.v:2598$337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_valid
-    connect \B $or$ls180.v:2613$368_Y
-    connect \Y $and$ls180.v:2613$369_Y
+    connect \B $or$ls180.v:2598$336_Y
+    connect \Y $and$ls180.v:2598$337_Y
   end
-  attribute \src "ls180.v:2614.67-2614.133"
-  cell $and $and$ls180.v:2614$370
+  attribute \src "ls180.v:2599.67-2599.133"
+  cell $and $and$ls180.v:2599$338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -248976,65 +248492,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_cmd
     connect \B \sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:2614$370_Y
+    connect \Y $and$ls180.v:2599$338_Y
   end
-  attribute \src "ls180.v:2614.142-2614.216"
-  cell $and $and$ls180.v:2614$372
+  attribute \src "ls180.v:2599.142-2599.216"
+  cell $and $and$ls180.v:2599$340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_ras
-    connect \B $not$ls180.v:2614$371_Y
-    connect \Y $and$ls180.v:2614$372_Y
+    connect \B $not$ls180.v:2599$339_Y
+    connect \Y $and$ls180.v:2599$340_Y
   end
-  attribute \src "ls180.v:2614.141-2614.256"
-  cell $and $and$ls180.v:2614$374
+  attribute \src "ls180.v:2599.141-2599.256"
+  cell $and $and$ls180.v:2599$342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2614$372_Y
-    connect \B $not$ls180.v:2614$373_Y
-    connect \Y $and$ls180.v:2614$374_Y
+    connect \A $and$ls180.v:2599$340_Y
+    connect \B $not$ls180.v:2599$341_Y
+    connect \Y $and$ls180.v:2599$342_Y
   end
-  attribute \src "ls180.v:2614.66-2614.293"
-  cell $and $and$ls180.v:2614$377
+  attribute \src "ls180.v:2599.66-2599.293"
+  cell $and $and$ls180.v:2599$345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2614$370_Y
-    connect \B $or$ls180.v:2614$376_Y
-    connect \Y $and$ls180.v:2614$377_Y
+    connect \A $and$ls180.v:2599$338_Y
+    connect \B $or$ls180.v:2599$344_Y
+    connect \Y $and$ls180.v:2599$345_Y
   end
-  attribute \src "ls180.v:2614.298-2614.445"
-  cell $and $and$ls180.v:2614$380
+  attribute \src "ls180.v:2599.298-2599.445"
+  cell $and $and$ls180.v:2599$348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2614$378_Y
-    connect \B $eq$ls180.v:2614$379_Y
-    connect \Y $and$ls180.v:2614$380_Y
+    connect \A $eq$ls180.v:2599$346_Y
+    connect \B $eq$ls180.v:2599$347_Y
+    connect \Y $and$ls180.v:2599$348_Y
   end
-  attribute \src "ls180.v:2614.33-2614.447"
-  cell $and $and$ls180.v:2614$382
+  attribute \src "ls180.v:2599.33-2599.447"
+  cell $and $and$ls180.v:2599$350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_valid
-    connect \B $or$ls180.v:2614$381_Y
-    connect \Y $and$ls180.v:2614$382_Y
+    connect \B $or$ls180.v:2599$349_Y
+    connect \Y $and$ls180.v:2599$350_Y
   end
-  attribute \src "ls180.v:2615.67-2615.133"
-  cell $and $and$ls180.v:2615$383
+  attribute \src "ls180.v:2600.67-2600.133"
+  cell $and $and$ls180.v:2600$351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249042,65 +248558,65 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_cmd
     connect \B \sdram_choose_req_want_cmds
-    connect \Y $and$ls180.v:2615$383_Y
+    connect \Y $and$ls180.v:2600$351_Y
   end
-  attribute \src "ls180.v:2615.142-2615.216"
-  cell $and $and$ls180.v:2615$385
+  attribute \src "ls180.v:2600.142-2600.216"
+  cell $and $and$ls180.v:2600$353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_ras
-    connect \B $not$ls180.v:2615$384_Y
-    connect \Y $and$ls180.v:2615$385_Y
+    connect \B $not$ls180.v:2600$352_Y
+    connect \Y $and$ls180.v:2600$353_Y
   end
-  attribute \src "ls180.v:2615.141-2615.256"
-  cell $and $and$ls180.v:2615$387
+  attribute \src "ls180.v:2600.141-2600.256"
+  cell $and $and$ls180.v:2600$355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2615$385_Y
-    connect \B $not$ls180.v:2615$386_Y
-    connect \Y $and$ls180.v:2615$387_Y
+    connect \A $and$ls180.v:2600$353_Y
+    connect \B $not$ls180.v:2600$354_Y
+    connect \Y $and$ls180.v:2600$355_Y
   end
-  attribute \src "ls180.v:2615.66-2615.293"
-  cell $and $and$ls180.v:2615$390
+  attribute \src "ls180.v:2600.66-2600.293"
+  cell $and $and$ls180.v:2600$358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2615$383_Y
-    connect \B $or$ls180.v:2615$389_Y
-    connect \Y $and$ls180.v:2615$390_Y
+    connect \A $and$ls180.v:2600$351_Y
+    connect \B $or$ls180.v:2600$357_Y
+    connect \Y $and$ls180.v:2600$358_Y
   end
-  attribute \src "ls180.v:2615.298-2615.445"
-  cell $and $and$ls180.v:2615$393
+  attribute \src "ls180.v:2600.298-2600.445"
+  cell $and $and$ls180.v:2600$361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2615$391_Y
-    connect \B $eq$ls180.v:2615$392_Y
-    connect \Y $and$ls180.v:2615$393_Y
+    connect \A $eq$ls180.v:2600$359_Y
+    connect \B $eq$ls180.v:2600$360_Y
+    connect \Y $and$ls180.v:2600$361_Y
   end
-  attribute \src "ls180.v:2615.33-2615.447"
-  cell $and $and$ls180.v:2615$395
+  attribute \src "ls180.v:2600.33-2600.447"
+  cell $and $and$ls180.v:2600$363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_valid
-    connect \B $or$ls180.v:2615$394_Y
-    connect \Y $and$ls180.v:2615$395_Y
+    connect \B $or$ls180.v:2600$362_Y
+    connect \Y $and$ls180.v:2600$363_Y
   end
-  attribute \src "ls180.v:2644.8-2644.63"
-  cell $and $and$ls180.v:2644$400
+  attribute \src "ls180.v:2629.8-2629.63"
+  cell $and $and$ls180.v:2629$368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249108,21 +248624,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_valid
     connect \B \sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:2644$400_Y
+    connect \Y $and$ls180.v:2629$368_Y
   end
-  attribute \src "ls180.v:2644.7-2644.99"
-  cell $and $and$ls180.v:2644$402
+  attribute \src "ls180.v:2629.7-2629.99"
+  cell $and $and$ls180.v:2629$370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2644$400_Y
-    connect \B $eq$ls180.v:2644$401_Y
-    connect \Y $and$ls180.v:2644$402_Y
+    connect \A $and$ls180.v:2629$368_Y
+    connect \B $eq$ls180.v:2629$369_Y
+    connect \Y $and$ls180.v:2629$370_Y
   end
-  attribute \src "ls180.v:2647.8-2647.63"
-  cell $and $and$ls180.v:2647$403
+  attribute \src "ls180.v:2632.8-2632.63"
+  cell $and $and$ls180.v:2632$371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249130,21 +248646,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2647$403_Y
+    connect \Y $and$ls180.v:2632$371_Y
   end
-  attribute \src "ls180.v:2647.7-2647.99"
-  cell $and $and$ls180.v:2647$405
+  attribute \src "ls180.v:2632.7-2632.99"
+  cell $and $and$ls180.v:2632$373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2647$403_Y
-    connect \B $eq$ls180.v:2647$404_Y
-    connect \Y $and$ls180.v:2647$405_Y
+    connect \A $and$ls180.v:2632$371_Y
+    connect \B $eq$ls180.v:2632$372_Y
+    connect \Y $and$ls180.v:2632$373_Y
   end
-  attribute \src "ls180.v:2653.8-2653.63"
-  cell $and $and$ls180.v:2653$407
+  attribute \src "ls180.v:2638.8-2638.63"
+  cell $and $and$ls180.v:2638$375
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249152,21 +248668,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_valid
     connect \B \sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:2653$407_Y
+    connect \Y $and$ls180.v:2638$375_Y
   end
-  attribute \src "ls180.v:2653.7-2653.99"
-  cell $and $and$ls180.v:2653$409
+  attribute \src "ls180.v:2638.7-2638.99"
+  cell $and $and$ls180.v:2638$377
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2653$407_Y
-    connect \B $eq$ls180.v:2653$408_Y
-    connect \Y $and$ls180.v:2653$409_Y
+    connect \A $and$ls180.v:2638$375_Y
+    connect \B $eq$ls180.v:2638$376_Y
+    connect \Y $and$ls180.v:2638$377_Y
   end
-  attribute \src "ls180.v:2656.8-2656.63"
-  cell $and $and$ls180.v:2656$410
+  attribute \src "ls180.v:2641.8-2641.63"
+  cell $and $and$ls180.v:2641$378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249174,21 +248690,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2656$410_Y
+    connect \Y $and$ls180.v:2641$378_Y
   end
-  attribute \src "ls180.v:2656.7-2656.99"
-  cell $and $and$ls180.v:2656$412
+  attribute \src "ls180.v:2641.7-2641.99"
+  cell $and $and$ls180.v:2641$380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2656$410_Y
-    connect \B $eq$ls180.v:2656$411_Y
-    connect \Y $and$ls180.v:2656$412_Y
+    connect \A $and$ls180.v:2641$378_Y
+    connect \B $eq$ls180.v:2641$379_Y
+    connect \Y $and$ls180.v:2641$380_Y
   end
-  attribute \src "ls180.v:2662.8-2662.63"
-  cell $and $and$ls180.v:2662$414
+  attribute \src "ls180.v:2647.8-2647.63"
+  cell $and $and$ls180.v:2647$382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249196,21 +248712,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_valid
     connect \B \sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:2662$414_Y
+    connect \Y $and$ls180.v:2647$382_Y
   end
-  attribute \src "ls180.v:2662.7-2662.99"
-  cell $and $and$ls180.v:2662$416
+  attribute \src "ls180.v:2647.7-2647.99"
+  cell $and $and$ls180.v:2647$384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2662$414_Y
-    connect \B $eq$ls180.v:2662$415_Y
-    connect \Y $and$ls180.v:2662$416_Y
+    connect \A $and$ls180.v:2647$382_Y
+    connect \B $eq$ls180.v:2647$383_Y
+    connect \Y $and$ls180.v:2647$384_Y
   end
-  attribute \src "ls180.v:2665.8-2665.63"
-  cell $and $and$ls180.v:2665$417
+  attribute \src "ls180.v:2650.8-2650.63"
+  cell $and $and$ls180.v:2650$385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249218,21 +248734,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2665$417_Y
+    connect \Y $and$ls180.v:2650$385_Y
   end
-  attribute \src "ls180.v:2665.7-2665.99"
-  cell $and $and$ls180.v:2665$419
+  attribute \src "ls180.v:2650.7-2650.99"
+  cell $and $and$ls180.v:2650$387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2665$417_Y
-    connect \B $eq$ls180.v:2665$418_Y
-    connect \Y $and$ls180.v:2665$419_Y
+    connect \A $and$ls180.v:2650$385_Y
+    connect \B $eq$ls180.v:2650$386_Y
+    connect \Y $and$ls180.v:2650$387_Y
   end
-  attribute \src "ls180.v:2671.8-2671.63"
-  cell $and $and$ls180.v:2671$421
+  attribute \src "ls180.v:2656.8-2656.63"
+  cell $and $and$ls180.v:2656$389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249240,21 +248756,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_valid
     connect \B \sdram_choose_cmd_cmd_ready
-    connect \Y $and$ls180.v:2671$421_Y
+    connect \Y $and$ls180.v:2656$389_Y
   end
-  attribute \src "ls180.v:2671.7-2671.99"
-  cell $and $and$ls180.v:2671$423
+  attribute \src "ls180.v:2656.7-2656.99"
+  cell $and $and$ls180.v:2656$391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2671$421_Y
-    connect \B $eq$ls180.v:2671$422_Y
-    connect \Y $and$ls180.v:2671$423_Y
+    connect \A $and$ls180.v:2656$389_Y
+    connect \B $eq$ls180.v:2656$390_Y
+    connect \Y $and$ls180.v:2656$391_Y
   end
-  attribute \src "ls180.v:2674.8-2674.63"
-  cell $and $and$ls180.v:2674$424
+  attribute \src "ls180.v:2659.8-2659.63"
+  cell $and $and$ls180.v:2659$392
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249262,615 +248778,615 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:2674$424_Y
+    connect \Y $and$ls180.v:2659$392_Y
   end
-  attribute \src "ls180.v:2674.7-2674.99"
-  cell $and $and$ls180.v:2674$426
+  attribute \src "ls180.v:2659.7-2659.99"
+  cell $and $and$ls180.v:2659$394
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2674$424_Y
-    connect \B $eq$ls180.v:2674$425_Y
-    connect \Y $and$ls180.v:2674$426_Y
+    connect \A $and$ls180.v:2659$392_Y
+    connect \B $eq$ls180.v:2659$393_Y
+    connect \Y $and$ls180.v:2659$394_Y
   end
-  attribute \src "ls180.v:2699.61-2699.131"
-  cell $and $and$ls180.v:2699$431
+  attribute \src "ls180.v:2684.61-2684.131"
+  cell $and $and$ls180.v:2684$399
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:2699$430_Y
-    connect \Y $and$ls180.v:2699$431_Y
+    connect \B $not$ls180.v:2684$398_Y
+    connect \Y $and$ls180.v:2684$399_Y
   end
-  attribute \src "ls180.v:2699.60-2699.169"
-  cell $and $and$ls180.v:2699$433
+  attribute \src "ls180.v:2684.60-2684.169"
+  cell $and $and$ls180.v:2684$401
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2699$431_Y
-    connect \B $not$ls180.v:2699$432_Y
-    connect \Y $and$ls180.v:2699$433_Y
+    connect \A $and$ls180.v:2684$399_Y
+    connect \B $not$ls180.v:2684$400_Y
+    connect \Y $and$ls180.v:2684$401_Y
   end
-  attribute \src "ls180.v:2699.36-2699.192"
-  cell $and $and$ls180.v:2699$436
+  attribute \src "ls180.v:2684.36-2684.192"
+  cell $and $and$ls180.v:2684$404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_cas_allowed
-    connect \B $or$ls180.v:2699$435_Y
-    connect \Y $and$ls180.v:2699$436_Y
+    connect \B $or$ls180.v:2684$403_Y
+    connect \Y $and$ls180.v:2684$404_Y
   end
-  attribute \src "ls180.v:2737.61-2737.131"
-  cell $and $and$ls180.v:2737$440
+  attribute \src "ls180.v:2722.61-2722.131"
+  cell $and $and$ls180.v:2722$408
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_ras
-    connect \B $not$ls180.v:2737$439_Y
-    connect \Y $and$ls180.v:2737$440_Y
+    connect \B $not$ls180.v:2722$407_Y
+    connect \Y $and$ls180.v:2722$408_Y
   end
-  attribute \src "ls180.v:2737.60-2737.169"
-  cell $and $and$ls180.v:2737$442
+  attribute \src "ls180.v:2722.60-2722.169"
+  cell $and $and$ls180.v:2722$410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2737$440_Y
-    connect \B $not$ls180.v:2737$441_Y
-    connect \Y $and$ls180.v:2737$442_Y
+    connect \A $and$ls180.v:2722$408_Y
+    connect \B $not$ls180.v:2722$409_Y
+    connect \Y $and$ls180.v:2722$410_Y
   end
-  attribute \src "ls180.v:2737.36-2737.192"
-  cell $and $and$ls180.v:2737$445
+  attribute \src "ls180.v:2722.36-2722.192"
+  cell $and $and$ls180.v:2722$413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_cas_allowed
-    connect \B $or$ls180.v:2737$444_Y
-    connect \Y $and$ls180.v:2737$445_Y
+    connect \B $or$ls180.v:2722$412_Y
+    connect \Y $and$ls180.v:2722$413_Y
   end
-  attribute \src "ls180.v:2755.115-2755.184"
-  cell $and $and$ls180.v:2755$450
+  attribute \src "ls180.v:2740.115-2740.184"
+  cell $and $and$ls180.v:2740$418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2755$449_Y
-    connect \Y $and$ls180.v:2755$450_Y
+    connect \B $eq$ls180.v:2740$417_Y
+    connect \Y $and$ls180.v:2740$418_Y
   end
-  attribute \src "ls180.v:2755.190-2755.259"
-  cell $and $and$ls180.v:2755$453
+  attribute \src "ls180.v:2740.190-2740.259"
+  cell $and $and$ls180.v:2740$421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2755$452_Y
-    connect \Y $and$ls180.v:2755$453_Y
+    connect \B $eq$ls180.v:2740$420_Y
+    connect \Y $and$ls180.v:2740$421_Y
   end
-  attribute \src "ls180.v:2755.265-2755.334"
-  cell $and $and$ls180.v:2755$456
+  attribute \src "ls180.v:2740.265-2740.334"
+  cell $and $and$ls180.v:2740$424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2755$455_Y
-    connect \Y $and$ls180.v:2755$456_Y
+    connect \B $eq$ls180.v:2740$423_Y
+    connect \Y $and$ls180.v:2740$424_Y
   end
-  attribute \src "ls180.v:2755.46-2755.337"
-  cell $and $and$ls180.v:2755$459
+  attribute \src "ls180.v:2740.46-2740.337"
+  cell $and $and$ls180.v:2740$427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2755$448_Y
-    connect \B $not$ls180.v:2755$458_Y
-    connect \Y $and$ls180.v:2755$459_Y
+    connect \A $eq$ls180.v:2740$416_Y
+    connect \B $not$ls180.v:2740$426_Y
+    connect \Y $and$ls180.v:2740$427_Y
   end
-  attribute \src "ls180.v:2755.45-2755.355"
-  cell $and $and$ls180.v:2755$460
+  attribute \src "ls180.v:2740.45-2740.355"
+  cell $and $and$ls180.v:2740$428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2755$459_Y
+    connect \A $and$ls180.v:2740$427_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:2755$460_Y
+    connect \Y $and$ls180.v:2740$428_Y
   end
-  attribute \src "ls180.v:2756.39-2756.101"
-  cell $and $and$ls180.v:2756$463
+  attribute \src "ls180.v:2741.39-2741.101"
+  cell $and $and$ls180.v:2741$431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2756$461_Y
-    connect \B $not$ls180.v:2756$462_Y
-    connect \Y $and$ls180.v:2756$463_Y
+    connect \A $not$ls180.v:2741$429_Y
+    connect \B $not$ls180.v:2741$430_Y
+    connect \Y $and$ls180.v:2741$431_Y
   end
-  attribute \src "ls180.v:2760.115-2760.184"
-  cell $and $and$ls180.v:2760$466
+  attribute \src "ls180.v:2745.115-2745.184"
+  cell $and $and$ls180.v:2745$434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2760$465_Y
-    connect \Y $and$ls180.v:2760$466_Y
+    connect \B $eq$ls180.v:2745$433_Y
+    connect \Y $and$ls180.v:2745$434_Y
   end
-  attribute \src "ls180.v:2760.190-2760.259"
-  cell $and $and$ls180.v:2760$469
+  attribute \src "ls180.v:2745.190-2745.259"
+  cell $and $and$ls180.v:2745$437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2760$468_Y
-    connect \Y $and$ls180.v:2760$469_Y
+    connect \B $eq$ls180.v:2745$436_Y
+    connect \Y $and$ls180.v:2745$437_Y
   end
-  attribute \src "ls180.v:2760.265-2760.334"
-  cell $and $and$ls180.v:2760$472
+  attribute \src "ls180.v:2745.265-2745.334"
+  cell $and $and$ls180.v:2745$440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2760$471_Y
-    connect \Y $and$ls180.v:2760$472_Y
+    connect \B $eq$ls180.v:2745$439_Y
+    connect \Y $and$ls180.v:2745$440_Y
   end
-  attribute \src "ls180.v:2760.46-2760.337"
-  cell $and $and$ls180.v:2760$475
+  attribute \src "ls180.v:2745.46-2745.337"
+  cell $and $and$ls180.v:2745$443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2760$464_Y
-    connect \B $not$ls180.v:2760$474_Y
-    connect \Y $and$ls180.v:2760$475_Y
+    connect \A $eq$ls180.v:2745$432_Y
+    connect \B $not$ls180.v:2745$442_Y
+    connect \Y $and$ls180.v:2745$443_Y
   end
-  attribute \src "ls180.v:2760.45-2760.355"
-  cell $and $and$ls180.v:2760$476
+  attribute \src "ls180.v:2745.45-2745.355"
+  cell $and $and$ls180.v:2745$444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2760$475_Y
+    connect \A $and$ls180.v:2745$443_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:2760$476_Y
+    connect \Y $and$ls180.v:2745$444_Y
   end
-  attribute \src "ls180.v:2761.39-2761.101"
-  cell $and $and$ls180.v:2761$479
+  attribute \src "ls180.v:2746.39-2746.101"
+  cell $and $and$ls180.v:2746$447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2761$477_Y
-    connect \B $not$ls180.v:2761$478_Y
-    connect \Y $and$ls180.v:2761$479_Y
+    connect \A $not$ls180.v:2746$445_Y
+    connect \B $not$ls180.v:2746$446_Y
+    connect \Y $and$ls180.v:2746$447_Y
   end
-  attribute \src "ls180.v:2765.115-2765.184"
-  cell $and $and$ls180.v:2765$482
+  attribute \src "ls180.v:2750.115-2750.184"
+  cell $and $and$ls180.v:2750$450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2765$481_Y
-    connect \Y $and$ls180.v:2765$482_Y
+    connect \B $eq$ls180.v:2750$449_Y
+    connect \Y $and$ls180.v:2750$450_Y
   end
-  attribute \src "ls180.v:2765.190-2765.259"
-  cell $and $and$ls180.v:2765$485
+  attribute \src "ls180.v:2750.190-2750.259"
+  cell $and $and$ls180.v:2750$453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2765$484_Y
-    connect \Y $and$ls180.v:2765$485_Y
+    connect \B $eq$ls180.v:2750$452_Y
+    connect \Y $and$ls180.v:2750$453_Y
   end
-  attribute \src "ls180.v:2765.265-2765.334"
-  cell $and $and$ls180.v:2765$488
+  attribute \src "ls180.v:2750.265-2750.334"
+  cell $and $and$ls180.v:2750$456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2765$487_Y
-    connect \Y $and$ls180.v:2765$488_Y
+    connect \B $eq$ls180.v:2750$455_Y
+    connect \Y $and$ls180.v:2750$456_Y
   end
-  attribute \src "ls180.v:2765.46-2765.337"
-  cell $and $and$ls180.v:2765$491
+  attribute \src "ls180.v:2750.46-2750.337"
+  cell $and $and$ls180.v:2750$459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2765$480_Y
-    connect \B $not$ls180.v:2765$490_Y
-    connect \Y $and$ls180.v:2765$491_Y
+    connect \A $eq$ls180.v:2750$448_Y
+    connect \B $not$ls180.v:2750$458_Y
+    connect \Y $and$ls180.v:2750$459_Y
   end
-  attribute \src "ls180.v:2765.45-2765.355"
-  cell $and $and$ls180.v:2765$492
+  attribute \src "ls180.v:2750.45-2750.355"
+  cell $and $and$ls180.v:2750$460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2765$491_Y
+    connect \A $and$ls180.v:2750$459_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:2765$492_Y
+    connect \Y $and$ls180.v:2750$460_Y
   end
-  attribute \src "ls180.v:2766.39-2766.101"
-  cell $and $and$ls180.v:2766$495
+  attribute \src "ls180.v:2751.39-2751.101"
+  cell $and $and$ls180.v:2751$463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2766$493_Y
-    connect \B $not$ls180.v:2766$494_Y
-    connect \Y $and$ls180.v:2766$495_Y
+    connect \A $not$ls180.v:2751$461_Y
+    connect \B $not$ls180.v:2751$462_Y
+    connect \Y $and$ls180.v:2751$463_Y
   end
-  attribute \src "ls180.v:2770.115-2770.184"
-  cell $and $and$ls180.v:2770$498
+  attribute \src "ls180.v:2755.115-2755.184"
+  cell $and $and$ls180.v:2755$466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2770$497_Y
-    connect \Y $and$ls180.v:2770$498_Y
+    connect \B $eq$ls180.v:2755$465_Y
+    connect \Y $and$ls180.v:2755$466_Y
   end
-  attribute \src "ls180.v:2770.190-2770.259"
-  cell $and $and$ls180.v:2770$501
+  attribute \src "ls180.v:2755.190-2755.259"
+  cell $and $and$ls180.v:2755$469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2770$500_Y
-    connect \Y $and$ls180.v:2770$501_Y
+    connect \B $eq$ls180.v:2755$468_Y
+    connect \Y $and$ls180.v:2755$469_Y
   end
-  attribute \src "ls180.v:2770.265-2770.334"
-  cell $and $and$ls180.v:2770$504
+  attribute \src "ls180.v:2755.265-2755.334"
+  cell $and $and$ls180.v:2755$472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2770$503_Y
-    connect \Y $and$ls180.v:2770$504_Y
+    connect \B $eq$ls180.v:2755$471_Y
+    connect \Y $and$ls180.v:2755$472_Y
   end
-  attribute \src "ls180.v:2770.46-2770.337"
-  cell $and $and$ls180.v:2770$507
+  attribute \src "ls180.v:2755.46-2755.337"
+  cell $and $and$ls180.v:2755$475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2770$496_Y
-    connect \B $not$ls180.v:2770$506_Y
-    connect \Y $and$ls180.v:2770$507_Y
+    connect \A $eq$ls180.v:2755$464_Y
+    connect \B $not$ls180.v:2755$474_Y
+    connect \Y $and$ls180.v:2755$475_Y
   end
-  attribute \src "ls180.v:2770.45-2770.355"
-  cell $and $and$ls180.v:2770$508
+  attribute \src "ls180.v:2755.45-2755.355"
+  cell $and $and$ls180.v:2755$476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2770$507_Y
+    connect \A $and$ls180.v:2755$475_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:2770$508_Y
+    connect \Y $and$ls180.v:2755$476_Y
   end
-  attribute \src "ls180.v:2771.39-2771.101"
-  cell $and $and$ls180.v:2771$511
+  attribute \src "ls180.v:2756.39-2756.101"
+  cell $and $and$ls180.v:2756$479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2771$509_Y
-    connect \B $not$ls180.v:2771$510_Y
-    connect \Y $and$ls180.v:2771$511_Y
+    connect \A $not$ls180.v:2756$477_Y
+    connect \B $not$ls180.v:2756$478_Y
+    connect \Y $and$ls180.v:2756$479_Y
   end
-  attribute \src "ls180.v:2775.151-2775.220"
-  cell $and $and$ls180.v:2775$515
+  attribute \src "ls180.v:2760.151-2760.220"
+  cell $and $and$ls180.v:2760$483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2775$514_Y
-    connect \Y $and$ls180.v:2775$515_Y
+    connect \B $eq$ls180.v:2760$482_Y
+    connect \Y $and$ls180.v:2760$483_Y
   end
-  attribute \src "ls180.v:2775.226-2775.295"
-  cell $and $and$ls180.v:2775$518
+  attribute \src "ls180.v:2760.226-2760.295"
+  cell $and $and$ls180.v:2760$486
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2775$517_Y
-    connect \Y $and$ls180.v:2775$518_Y
+    connect \B $eq$ls180.v:2760$485_Y
+    connect \Y $and$ls180.v:2760$486_Y
   end
-  attribute \src "ls180.v:2775.301-2775.370"
-  cell $and $and$ls180.v:2775$521
+  attribute \src "ls180.v:2760.301-2760.370"
+  cell $and $and$ls180.v:2760$489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2775$520_Y
-    connect \Y $and$ls180.v:2775$521_Y
+    connect \B $eq$ls180.v:2760$488_Y
+    connect \Y $and$ls180.v:2760$489_Y
   end
-  attribute \src "ls180.v:2775.82-2775.373"
-  cell $and $and$ls180.v:2775$524
+  attribute \src "ls180.v:2760.82-2760.373"
+  cell $and $and$ls180.v:2760$492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$513_Y
-    connect \B $not$ls180.v:2775$523_Y
-    connect \Y $and$ls180.v:2775$524_Y
+    connect \A $eq$ls180.v:2760$481_Y
+    connect \B $not$ls180.v:2760$491_Y
+    connect \Y $and$ls180.v:2760$492_Y
   end
-  attribute \src "ls180.v:2775.38-2775.374"
-  cell $and $and$ls180.v:2775$525
+  attribute \src "ls180.v:2760.38-2760.374"
+  cell $and $and$ls180.v:2760$493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$512_Y
-    connect \B $and$ls180.v:2775$524_Y
-    connect \Y $and$ls180.v:2775$525_Y
+    connect \A $eq$ls180.v:2760$480_Y
+    connect \B $and$ls180.v:2760$492_Y
+    connect \Y $and$ls180.v:2760$493_Y
   end
-  attribute \src "ls180.v:2775.37-2775.405"
-  cell $and $and$ls180.v:2775$526
+  attribute \src "ls180.v:2760.37-2760.405"
+  cell $and $and$ls180.v:2760$494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2775$525_Y
+    connect \A $and$ls180.v:2760$493_Y
     connect \B \sdram_interface_bank0_ready
-    connect \Y $and$ls180.v:2775$526_Y
+    connect \Y $and$ls180.v:2760$494_Y
   end
-  attribute \src "ls180.v:2775.525-2775.594"
-  cell $and $and$ls180.v:2775$531
+  attribute \src "ls180.v:2760.525-2760.594"
+  cell $and $and$ls180.v:2760$499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2775$530_Y
-    connect \Y $and$ls180.v:2775$531_Y
+    connect \B $eq$ls180.v:2760$498_Y
+    connect \Y $and$ls180.v:2760$499_Y
   end
-  attribute \src "ls180.v:2775.600-2775.669"
-  cell $and $and$ls180.v:2775$534
+  attribute \src "ls180.v:2760.600-2760.669"
+  cell $and $and$ls180.v:2760$502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2775$533_Y
-    connect \Y $and$ls180.v:2775$534_Y
+    connect \B $eq$ls180.v:2760$501_Y
+    connect \Y $and$ls180.v:2760$502_Y
   end
-  attribute \src "ls180.v:2775.675-2775.744"
-  cell $and $and$ls180.v:2775$537
+  attribute \src "ls180.v:2760.675-2760.744"
+  cell $and $and$ls180.v:2760$505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2775$536_Y
-    connect \Y $and$ls180.v:2775$537_Y
+    connect \B $eq$ls180.v:2760$504_Y
+    connect \Y $and$ls180.v:2760$505_Y
   end
-  attribute \src "ls180.v:2775.456-2775.747"
-  cell $and $and$ls180.v:2775$540
+  attribute \src "ls180.v:2760.456-2760.747"
+  cell $and $and$ls180.v:2760$508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$529_Y
-    connect \B $not$ls180.v:2775$539_Y
-    connect \Y $and$ls180.v:2775$540_Y
+    connect \A $eq$ls180.v:2760$497_Y
+    connect \B $not$ls180.v:2760$507_Y
+    connect \Y $and$ls180.v:2760$508_Y
   end
-  attribute \src "ls180.v:2775.412-2775.748"
-  cell $and $and$ls180.v:2775$541
+  attribute \src "ls180.v:2760.412-2760.748"
+  cell $and $and$ls180.v:2760$509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$528_Y
-    connect \B $and$ls180.v:2775$540_Y
-    connect \Y $and$ls180.v:2775$541_Y
+    connect \A $eq$ls180.v:2760$496_Y
+    connect \B $and$ls180.v:2760$508_Y
+    connect \Y $and$ls180.v:2760$509_Y
   end
-  attribute \src "ls180.v:2775.411-2775.779"
-  cell $and $and$ls180.v:2775$542
+  attribute \src "ls180.v:2760.411-2760.779"
+  cell $and $and$ls180.v:2760$510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2775$541_Y
+    connect \A $and$ls180.v:2760$509_Y
     connect \B \sdram_interface_bank1_ready
-    connect \Y $and$ls180.v:2775$542_Y
+    connect \Y $and$ls180.v:2760$510_Y
   end
-  attribute \src "ls180.v:2775.899-2775.968"
-  cell $and $and$ls180.v:2775$547
+  attribute \src "ls180.v:2760.899-2760.968"
+  cell $and $and$ls180.v:2760$515
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2775$546_Y
-    connect \Y $and$ls180.v:2775$547_Y
+    connect \B $eq$ls180.v:2760$514_Y
+    connect \Y $and$ls180.v:2760$515_Y
   end
-  attribute \src "ls180.v:2775.974-2775.1043"
-  cell $and $and$ls180.v:2775$550
+  attribute \src "ls180.v:2760.974-2760.1043"
+  cell $and $and$ls180.v:2760$518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2775$549_Y
-    connect \Y $and$ls180.v:2775$550_Y
+    connect \B $eq$ls180.v:2760$517_Y
+    connect \Y $and$ls180.v:2760$518_Y
   end
-  attribute \src "ls180.v:2775.1049-2775.1118"
-  cell $and $and$ls180.v:2775$553
+  attribute \src "ls180.v:2760.1049-2760.1118"
+  cell $and $and$ls180.v:2760$521
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:2775$552_Y
-    connect \Y $and$ls180.v:2775$553_Y
+    connect \B $eq$ls180.v:2760$520_Y
+    connect \Y $and$ls180.v:2760$521_Y
   end
-  attribute \src "ls180.v:2775.830-2775.1121"
-  cell $and $and$ls180.v:2775$556
+  attribute \src "ls180.v:2760.830-2760.1121"
+  cell $and $and$ls180.v:2760$524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$545_Y
-    connect \B $not$ls180.v:2775$555_Y
-    connect \Y $and$ls180.v:2775$556_Y
+    connect \A $eq$ls180.v:2760$513_Y
+    connect \B $not$ls180.v:2760$523_Y
+    connect \Y $and$ls180.v:2760$524_Y
   end
-  attribute \src "ls180.v:2775.786-2775.1122"
-  cell $and $and$ls180.v:2775$557
+  attribute \src "ls180.v:2760.786-2760.1122"
+  cell $and $and$ls180.v:2760$525
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$544_Y
-    connect \B $and$ls180.v:2775$556_Y
-    connect \Y $and$ls180.v:2775$557_Y
+    connect \A $eq$ls180.v:2760$512_Y
+    connect \B $and$ls180.v:2760$524_Y
+    connect \Y $and$ls180.v:2760$525_Y
   end
-  attribute \src "ls180.v:2775.785-2775.1153"
-  cell $and $and$ls180.v:2775$558
+  attribute \src "ls180.v:2760.785-2760.1153"
+  cell $and $and$ls180.v:2760$526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2775$557_Y
+    connect \A $and$ls180.v:2760$525_Y
     connect \B \sdram_interface_bank2_ready
-    connect \Y $and$ls180.v:2775$558_Y
+    connect \Y $and$ls180.v:2760$526_Y
   end
-  attribute \src "ls180.v:2775.1273-2775.1342"
-  cell $and $and$ls180.v:2775$563
+  attribute \src "ls180.v:2760.1273-2760.1342"
+  cell $and $and$ls180.v:2760$531
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:2775$562_Y
-    connect \Y $and$ls180.v:2775$563_Y
+    connect \B $eq$ls180.v:2760$530_Y
+    connect \Y $and$ls180.v:2760$531_Y
   end
-  attribute \src "ls180.v:2775.1348-2775.1417"
-  cell $and $and$ls180.v:2775$566
+  attribute \src "ls180.v:2760.1348-2760.1417"
+  cell $and $and$ls180.v:2760$534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:2775$565_Y
-    connect \Y $and$ls180.v:2775$566_Y
+    connect \B $eq$ls180.v:2760$533_Y
+    connect \Y $and$ls180.v:2760$534_Y
   end
-  attribute \src "ls180.v:2775.1423-2775.1492"
-  cell $and $and$ls180.v:2775$569
+  attribute \src "ls180.v:2760.1423-2760.1492"
+  cell $and $and$ls180.v:2760$537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:2775$568_Y
-    connect \Y $and$ls180.v:2775$569_Y
+    connect \B $eq$ls180.v:2760$536_Y
+    connect \Y $and$ls180.v:2760$537_Y
   end
-  attribute \src "ls180.v:2775.1204-2775.1495"
-  cell $and $and$ls180.v:2775$572
+  attribute \src "ls180.v:2760.1204-2760.1495"
+  cell $and $and$ls180.v:2760$540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$561_Y
-    connect \B $not$ls180.v:2775$571_Y
-    connect \Y $and$ls180.v:2775$572_Y
+    connect \A $eq$ls180.v:2760$529_Y
+    connect \B $not$ls180.v:2760$539_Y
+    connect \Y $and$ls180.v:2760$540_Y
   end
-  attribute \src "ls180.v:2775.1160-2775.1496"
-  cell $and $and$ls180.v:2775$573
+  attribute \src "ls180.v:2760.1160-2760.1496"
+  cell $and $and$ls180.v:2760$541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:2775$560_Y
-    connect \B $and$ls180.v:2775$572_Y
-    connect \Y $and$ls180.v:2775$573_Y
+    connect \A $eq$ls180.v:2760$528_Y
+    connect \B $and$ls180.v:2760$540_Y
+    connect \Y $and$ls180.v:2760$541_Y
   end
-  attribute \src "ls180.v:2775.1159-2775.1527"
-  cell $and $and$ls180.v:2775$574
+  attribute \src "ls180.v:2760.1159-2760.1527"
+  cell $and $and$ls180.v:2760$542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2775$573_Y
+    connect \A $and$ls180.v:2760$541_Y
     connect \B \sdram_interface_bank3_ready
-    connect \Y $and$ls180.v:2775$574_Y
+    connect \Y $and$ls180.v:2760$542_Y
   end
-  attribute \src "ls180.v:2833.9-2833.36"
-  cell $and $and$ls180.v:2833$580
+  attribute \src "ls180.v:2818.9-2818.36"
+  cell $and $and$ls180.v:2818$548
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249878,10 +249394,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \wb_sdram_stb
     connect \B \wb_sdram_cyc
-    connect \Y $and$ls180.v:2833$580_Y
+    connect \Y $and$ls180.v:2818$548_Y
   end
-  attribute \src "ls180.v:2851.9-2851.36"
-  cell $and $and$ls180.v:2851$587
+  attribute \src "ls180.v:2836.9-2836.36"
+  cell $and $and$ls180.v:2836$555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249889,10 +249405,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \wb_sdram_stb
     connect \B \wb_sdram_cyc
-    connect \Y $and$ls180.v:2851$587_Y
+    connect \Y $and$ls180.v:2836$555_Y
   end
-  attribute \src "ls180.v:2864.27-2864.60"
-  cell $and $and$ls180.v:2864$591
+  attribute \src "ls180.v:2849.27-2849.60"
+  cell $and $and$ls180.v:2849$559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249900,54 +249416,54 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_cyc
     connect \B \litedram_wb_stb
-    connect \Y $and$ls180.v:2864$591_Y
+    connect \Y $and$ls180.v:2849$559_Y
   end
-  attribute \src "ls180.v:2864.26-2864.79"
-  cell $and $and$ls180.v:2864$593
+  attribute \src "ls180.v:2849.26-2849.79"
+  cell $and $and$ls180.v:2849$561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2864$591_Y
-    connect \B $not$ls180.v:2864$592_Y
-    connect \Y $and$ls180.v:2864$593_Y
+    connect \A $and$ls180.v:2849$559_Y
+    connect \B $not$ls180.v:2849$560_Y
+    connect \Y $and$ls180.v:2849$561_Y
   end
-  attribute \src "ls180.v:2865.29-2865.82"
-  cell $and $and$ls180.v:2865$595
+  attribute \src "ls180.v:2850.29-2850.82"
+  cell $and $and$ls180.v:2850$563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2865$594_Y
+    connect \A $or$ls180.v:2850$562_Y
     connect \B \port_cmd_payload_we
-    connect \Y $and$ls180.v:2865$595_Y
+    connect \Y $and$ls180.v:2850$563_Y
   end
-  attribute \src "ls180.v:2865.28-2865.103"
-  cell $and $and$ls180.v:2865$597
+  attribute \src "ls180.v:2850.28-2850.103"
+  cell $and $and$ls180.v:2850$565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2865$595_Y
-    connect \B $not$ls180.v:2865$596_Y
-    connect \Y $and$ls180.v:2865$597_Y
+    connect \A $and$ls180.v:2850$563_Y
+    connect \B $not$ls180.v:2850$564_Y
+    connect \Y $and$ls180.v:2850$565_Y
   end
-  attribute \src "ls180.v:2866.28-2866.84"
-  cell $and $and$ls180.v:2866$600
+  attribute \src "ls180.v:2851.28-2851.84"
+  cell $and $and$ls180.v:2851$568
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2866$598_Y
-    connect \B $not$ls180.v:2866$599_Y
-    connect \Y $and$ls180.v:2866$600_Y
+    connect \A $or$ls180.v:2851$566_Y
+    connect \B $not$ls180.v:2851$567_Y
+    connect \Y $and$ls180.v:2851$568_Y
   end
-  attribute \src "ls180.v:2867.39-2867.65"
-  cell $and $and$ls180.v:2867$601
+  attribute \src "ls180.v:2852.39-2852.65"
+  cell $and $and$ls180.v:2852$569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249955,32 +249471,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_we
     connect \B \ack_wdata
-    connect \Y $and$ls180.v:2867$601_Y
+    connect \Y $and$ls180.v:2852$569_Y
   end
-  attribute \src "ls180.v:2867.70-2867.99"
-  cell $and $and$ls180.v:2867$603
+  attribute \src "ls180.v:2852.70-2852.99"
+  cell $and $and$ls180.v:2852$571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2867$602_Y
+    connect \A $not$ls180.v:2852$570_Y
     connect \B \ack_rdata
-    connect \Y $and$ls180.v:2867$603_Y
+    connect \Y $and$ls180.v:2852$571_Y
   end
-  attribute \src "ls180.v:2867.27-2867.101"
-  cell $and $and$ls180.v:2867$605
+  attribute \src "ls180.v:2852.27-2852.101"
+  cell $and $and$ls180.v:2852$573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ack_cmd
-    connect \B $or$ls180.v:2867$604_Y
-    connect \Y $and$ls180.v:2867$605_Y
+    connect \B $or$ls180.v:2852$572_Y
+    connect \Y $and$ls180.v:2852$573_Y
   end
-  attribute \src "ls180.v:2868.20-2868.51"
-  cell $and $and$ls180.v:2868$606
+  attribute \src "ls180.v:2853.20-2853.51"
+  cell $and $and$ls180.v:2853$574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249988,10 +249504,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_valid
     connect \B \port_cmd_ready
-    connect \Y $and$ls180.v:2868$606_Y
+    connect \Y $and$ls180.v:2853$574_Y
   end
-  attribute \src "ls180.v:2869.22-2869.57"
-  cell $and $and$ls180.v:2869$608
+  attribute \src "ls180.v:2854.22-2854.57"
+  cell $and $and$ls180.v:2854$576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -249999,10 +249515,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_wdata_valid
     connect \B \port_wdata_ready
-    connect \Y $and$ls180.v:2869$608_Y
+    connect \Y $and$ls180.v:2854$576_Y
   end
-  attribute \src "ls180.v:2870.21-2870.56"
-  cell $and $and$ls180.v:2870$610
+  attribute \src "ls180.v:2855.21-2855.56"
+  cell $and $and$ls180.v:2855$578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250010,10 +249526,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_rdata_valid
     connect \B \port_rdata_ready
-    connect \Y $and$ls180.v:2870$610_Y
+    connect \Y $and$ls180.v:2855$578_Y
   end
-  attribute \src "ls180.v:2899.44-2899.58"
-  cell $and $and$ls180.v:2899$616
+  attribute \src "ls180.v:2884.44-2884.58"
+  cell $and $and$ls180.v:2884$584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250021,10 +249537,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A 1'0
     connect \B \rxtx_we
-    connect \Y $and$ls180.v:2899$616_Y
+    connect \Y $and$ls180.v:2884$584_Y
   end
-  attribute \src "ls180.v:2903.7-2903.58"
-  cell $and $and$ls180.v:2903$620
+  attribute \src "ls180.v:2888.7-2888.58"
+  cell $and $and$ls180.v:2888$588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250032,10 +249548,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \eventmanager_pending_re
     connect \B \eventmanager_pending_r [0]
-    connect \Y $and$ls180.v:2903$620_Y
+    connect \Y $and$ls180.v:2888$588_Y
   end
-  attribute \src "ls180.v:2914.7-2914.58"
-  cell $and $and$ls180.v:2914$623
+  attribute \src "ls180.v:2899.7-2899.58"
+  cell $and $and$ls180.v:2899$591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250043,10 +249559,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \eventmanager_pending_re
     connect \B \eventmanager_pending_r [1]
-    connect \Y $and$ls180.v:2914$623_Y
+    connect \Y $and$ls180.v:2899$591_Y
   end
-  attribute \src "ls180.v:2923.16-2923.67"
-  cell $and $and$ls180.v:2923$625
+  attribute \src "ls180.v:2908.16-2908.67"
+  cell $and $and$ls180.v:2908$593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250054,10 +249570,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \eventmanager_pending_w [0]
     connect \B \eventmanager_storage [0]
-    connect \Y $and$ls180.v:2923$625_Y
+    connect \Y $and$ls180.v:2908$593_Y
   end
-  attribute \src "ls180.v:2923.72-2923.123"
-  cell $and $and$ls180.v:2923$626
+  attribute \src "ls180.v:2908.72-2908.123"
+  cell $and $and$ls180.v:2908$594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250065,32 +249581,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \eventmanager_pending_w [1]
     connect \B \eventmanager_storage [1]
-    connect \Y $and$ls180.v:2923$626_Y
+    connect \Y $and$ls180.v:2908$594_Y
   end
-  attribute \src "ls180.v:2938.31-2938.93"
-  cell $and $and$ls180.v:2938$630
+  attribute \src "ls180.v:2923.31-2923.93"
+  cell $and $and$ls180.v:2923$598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_readable
-    connect \B $or$ls180.v:2938$629_Y
-    connect \Y $and$ls180.v:2938$630_Y
+    connect \B $or$ls180.v:2923$597_Y
+    connect \Y $and$ls180.v:2923$598_Y
   end
-  attribute \src "ls180.v:2949.29-2949.96"
-  cell $and $and$ls180.v:2949$635
+  attribute \src "ls180.v:2934.29-2934.96"
+  cell $and $and$ls180.v:2934$603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_we
-    connect \B $or$ls180.v:2949$634_Y
-    connect \Y $and$ls180.v:2949$635_Y
+    connect \B $or$ls180.v:2934$602_Y
+    connect \Y $and$ls180.v:2934$603_Y
   end
-  attribute \src "ls180.v:2950.27-2950.74"
-  cell $and $and$ls180.v:2950$636
+  attribute \src "ls180.v:2935.27-2935.74"
+  cell $and $and$ls180.v:2935$604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250098,32 +249614,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_readable
     connect \B \tx_fifo_syncfifo_re
-    connect \Y $and$ls180.v:2950$636_Y
+    connect \Y $and$ls180.v:2935$604_Y
   end
-  attribute \src "ls180.v:2968.31-2968.93"
-  cell $and $and$ls180.v:2968$641
+  attribute \src "ls180.v:2953.31-2953.93"
+  cell $and $and$ls180.v:2953$609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_readable
-    connect \B $or$ls180.v:2968$640_Y
-    connect \Y $and$ls180.v:2968$641_Y
+    connect \B $or$ls180.v:2953$608_Y
+    connect \Y $and$ls180.v:2953$609_Y
   end
-  attribute \src "ls180.v:2979.29-2979.96"
-  cell $and $and$ls180.v:2979$646
+  attribute \src "ls180.v:2964.29-2964.96"
+  cell $and $and$ls180.v:2964$614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_we
-    connect \B $or$ls180.v:2979$645_Y
-    connect \Y $and$ls180.v:2979$646_Y
+    connect \B $or$ls180.v:2964$613_Y
+    connect \Y $and$ls180.v:2964$614_Y
   end
-  attribute \src "ls180.v:2980.27-2980.74"
-  cell $and $and$ls180.v:2980$647
+  attribute \src "ls180.v:2965.27-2965.74"
+  cell $and $and$ls180.v:2965$615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250131,10 +249647,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_readable
     connect \B \rx_fifo_syncfifo_re
-    connect \Y $and$ls180.v:2980$647_Y
+    connect \Y $and$ls180.v:2965$615_Y
   end
-  attribute \src "ls180.v:3077.9-3077.84"
-  cell $and $and$ls180.v:3077$655
+  attribute \src "ls180.v:3062.9-3062.84"
+  cell $and $and$ls180.v:3062$623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250142,87 +249658,87 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_libresocsim_wishbone_cyc
     connect \B \libresocsim_libresocsim_wishbone_stb
-    connect \Y $and$ls180.v:3077$655_Y
+    connect \Y $and$ls180.v:3062$623_Y
   end
-  attribute \src "ls180.v:3080.60-3080.144"
-  cell $and $and$ls180.v:3080$657
+  attribute \src "ls180.v:3065.60-3065.144"
+  cell $and $and$ls180.v:3065$625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_libresocsim_wishbone_we
-    connect \B $ne$ls180.v:3080$656_Y
-    connect \Y $and$ls180.v:3080$657_Y
+    connect \B $ne$ls180.v:3065$624_Y
+    connect \Y $and$ls180.v:3065$625_Y
   end
-  attribute \src "ls180.v:3098.41-3098.93"
-  cell $and $and$ls180.v:3098$659
+  attribute \src "ls180.v:3083.58-3083.110"
+  cell $and $and$ls180.v:3083$627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_ack
-    connect \B $eq$ls180.v:3098$658_Y
-    connect \Y $and$ls180.v:3098$659_Y
+    connect \B $eq$ls180.v:3083$626_Y
+    connect \Y $and$ls180.v:3083$627_Y
   end
-  attribute \src "ls180.v:3099.41-3099.93"
-  cell $and $and$ls180.v:3099$661
+  attribute \src "ls180.v:3084.58-3084.110"
+  cell $and $and$ls180.v:3084$629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_ack
-    connect \B $eq$ls180.v:3099$660_Y
-    connect \Y $and$ls180.v:3099$661_Y
+    connect \B $eq$ls180.v:3084$628_Y
+    connect \Y $and$ls180.v:3084$629_Y
   end
-  attribute \src "ls180.v:3100.44-3100.96"
-  cell $and $and$ls180.v:3100$663
+  attribute \src "ls180.v:3085.58-3085.110"
+  cell $and $and$ls180.v:3085$631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_ack
-    connect \B $eq$ls180.v:3100$662_Y
-    connect \Y $and$ls180.v:3100$663_Y
+    connect \B $eq$ls180.v:3085$630_Y
+    connect \Y $and$ls180.v:3085$631_Y
   end
-  attribute \src "ls180.v:3101.41-3101.93"
-  cell $and $and$ls180.v:3101$665
+  attribute \src "ls180.v:3086.58-3086.110"
+  cell $and $and$ls180.v:3086$633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_err
-    connect \B $eq$ls180.v:3101$664_Y
-    connect \Y $and$ls180.v:3101$665_Y
+    connect \B $eq$ls180.v:3086$632_Y
+    connect \Y $and$ls180.v:3086$633_Y
   end
-  attribute \src "ls180.v:3102.41-3102.93"
-  cell $and $and$ls180.v:3102$667
+  attribute \src "ls180.v:3087.58-3087.110"
+  cell $and $and$ls180.v:3087$635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_err
-    connect \B $eq$ls180.v:3102$666_Y
-    connect \Y $and$ls180.v:3102$667_Y
+    connect \B $eq$ls180.v:3087$634_Y
+    connect \Y $and$ls180.v:3087$635_Y
   end
-  attribute \src "ls180.v:3103.44-3103.96"
-  cell $and $and$ls180.v:3103$669
+  attribute \src "ls180.v:3088.58-3088.110"
+  cell $and $and$ls180.v:3088$637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_err
-    connect \B $eq$ls180.v:3103$668_Y
-    connect \Y $and$ls180.v:3103$669_Y
+    connect \B $eq$ls180.v:3088$636_Y
+    connect \Y $and$ls180.v:3088$637_Y
   end
-  attribute \src "ls180.v:3156.35-3156.84"
-  cell $and $and$ls180.v:3156$677
+  attribute \src "ls180.v:3141.35-3141.84"
+  cell $and $and$ls180.v:3141$645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250230,10 +249746,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [0]
-    connect \Y $and$ls180.v:3156$677_Y
+    connect \Y $and$ls180.v:3141$645_Y
   end
-  attribute \src "ls180.v:3157.31-3157.80"
-  cell $and $and$ls180.v:3157$678
+  attribute \src "ls180.v:3142.31-3142.80"
+  cell $and $and$ls180.v:3142$646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250241,10 +249757,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [1]
-    connect \Y $and$ls180.v:3157$678_Y
+    connect \Y $and$ls180.v:3142$646_Y
   end
-  attribute \src "ls180.v:3158.46-3158.95"
-  cell $and $and$ls180.v:3158$679
+  attribute \src "ls180.v:3143.45-3143.94"
+  cell $and $and$ls180.v:3143$647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250252,10 +249768,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [2]
-    connect \Y $and$ls180.v:3158$679_Y
+    connect \Y $and$ls180.v:3143$647_Y
   end
-  attribute \src "ls180.v:3159.46-3159.95"
-  cell $and $and$ls180.v:3159$680
+  attribute \src "ls180.v:3144.45-3144.94"
+  cell $and $and$ls180.v:3144$648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250263,10 +249779,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [3]
-    connect \Y $and$ls180.v:3159$680_Y
+    connect \Y $and$ls180.v:3144$648_Y
   end
-  attribute \src "ls180.v:3160.49-3160.98"
-  cell $and $and$ls180.v:3160$681
+  attribute \src "ls180.v:3145.24-3145.73"
+  cell $and $and$ls180.v:3145$649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250274,10 +249790,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [4]
-    connect \Y $and$ls180.v:3160$681_Y
+    connect \Y $and$ls180.v:3145$649_Y
   end
-  attribute \src "ls180.v:3161.59-3161.108"
-  cell $and $and$ls180.v:3161$682
+  attribute \src "ls180.v:3146.48-3146.97"
+  cell $and $and$ls180.v:3146$650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250285,10 +249801,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_cyc
     connect \B \libresocsim_slave_sel [5]
-    connect \Y $and$ls180.v:3161$682_Y
+    connect \Y $and$ls180.v:3146$650_Y
   end
-  attribute \src "ls180.v:3163.29-3163.76"
-  cell $and $and$ls180.v:3163$688
+  attribute \src "ls180.v:3148.29-3148.76"
+  cell $and $and$ls180.v:3148$656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250296,87 +249812,87 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_stb
     connect \B \libresocsim_shared_cyc
-    connect \Y $and$ls180.v:3163$688_Y
+    connect \Y $and$ls180.v:3148$656_Y
   end
-  attribute \src "ls180.v:3163.28-3163.105"
-  cell $and $and$ls180.v:3163$690
+  attribute \src "ls180.v:3148.28-3148.105"
+  cell $and $and$ls180.v:3148$658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3163$688_Y
-    connect \B $not$ls180.v:3163$689_Y
-    connect \Y $and$ls180.v:3163$690_Y
+    connect \A $and$ls180.v:3148$656_Y
+    connect \B $not$ls180.v:3148$657_Y
+    connect \Y $and$ls180.v:3148$658_Y
   end
-  attribute \src "ls180.v:3169.36-3169.96"
-  cell $and $and$ls180.v:3169$697
+  attribute \src "ls180.v:3154.36-3154.96"
+  cell $and $and$ls180.v:3154$665
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] }
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] }
     connect \B \libresocsim_ram_bus_dat_r
-    connect \Y $and$ls180.v:3169$697_Y
+    connect \Y $and$ls180.v:3154$665_Y
   end
-  attribute \src "ls180.v:3169.101-3169.157"
-  cell $and $and$ls180.v:3169$698
+  attribute \src "ls180.v:3154.101-3154.157"
+  cell $and $and$ls180.v:3154$666
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] }
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] }
     connect \B \ram_bus_ram_bus_dat_r
-    connect \Y $and$ls180.v:3169$698_Y
+    connect \Y $and$ls180.v:3154$666_Y
   end
-  attribute \src "ls180.v:3169.163-3169.234"
-  cell $and $and$ls180.v:3169$700
+  attribute \src "ls180.v:3154.163-3154.233"
+  cell $and $and$ls180.v:3154$668
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] }
-    connect \B \interface0_converted_interface_dat_r
-    connect \Y $and$ls180.v:3169$700_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] }
+    connect \B \libresocsim_libresoc_xics_icp_dat_r
+    connect \Y $and$ls180.v:3154$668_Y
   end
-  attribute \src "ls180.v:3169.240-3169.311"
-  cell $and $and$ls180.v:3169$702
+  attribute \src "ls180.v:3154.239-3154.309"
+  cell $and $and$ls180.v:3154$670
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] }
-    connect \B \interface1_converted_interface_dat_r
-    connect \Y $and$ls180.v:3169$702_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] }
+    connect \B \libresocsim_libresoc_xics_ics_dat_r
+    connect \Y $and$ls180.v:3154$670_Y
   end
-  attribute \src "ls180.v:3169.317-3169.391"
-  cell $and $and$ls180.v:3169$704
+  attribute \src "ls180.v:3154.315-3154.364"
+  cell $and $and$ls180.v:3154$672
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] }
-    connect \B \socbushandler_converted_interface_dat_r
-    connect \Y $and$ls180.v:3169$704_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] }
+    connect \B \wb_sdram_dat_r
+    connect \Y $and$ls180.v:3154$672_Y
   end
-  attribute \src "ls180.v:3169.397-3169.481"
-  cell $and $and$ls180.v:3169$706
+  attribute \src "ls180.v:3154.370-3154.443"
+  cell $and $and$ls180.v:3154$674
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] }
-    connect \B \libresocsim_libresocsim_converted_interface_dat_r
-    connect \Y $and$ls180.v:3169$706_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A { \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] }
+    connect \B \libresocsim_libresocsim_wishbone_dat_r
+    connect \Y $and$ls180.v:3154$674_Y
   end
-  attribute \src "ls180.v:3179.43-3179.104"
-  cell $and $and$ls180.v:3179$710
+  attribute \src "ls180.v:3164.43-3164.104"
+  cell $and $and$ls180.v:3164$678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250384,43 +249900,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3179$710_Y
+    connect \Y $and$ls180.v:3164$678_Y
   end
-  attribute \src "ls180.v:3179.42-3179.158"
-  cell $and $and$ls180.v:3179$712
+  attribute \src "ls180.v:3164.42-3164.158"
+  cell $and $and$ls180.v:3164$680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3179$710_Y
-    connect \B $eq$ls180.v:3179$711_Y
-    connect \Y $and$ls180.v:3179$712_Y
+    connect \A $and$ls180.v:3164$678_Y
+    connect \B $eq$ls180.v:3164$679_Y
+    connect \Y $and$ls180.v:3164$680_Y
   end
-  attribute \src "ls180.v:3180.43-3180.107"
-  cell $and $and$ls180.v:3180$714
+  attribute \src "ls180.v:3165.43-3165.107"
+  cell $and $and$ls180.v:3165$682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3180$713_Y
-    connect \Y $and$ls180.v:3180$714_Y
+    connect \B $not$ls180.v:3165$681_Y
+    connect \Y $and$ls180.v:3165$682_Y
   end
-  attribute \src "ls180.v:3180.42-3180.161"
-  cell $and $and$ls180.v:3180$716
+  attribute \src "ls180.v:3165.42-3165.161"
+  cell $and $and$ls180.v:3165$684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3180$714_Y
-    connect \B $eq$ls180.v:3180$715_Y
-    connect \Y $and$ls180.v:3180$716_Y
+    connect \A $and$ls180.v:3165$682_Y
+    connect \B $eq$ls180.v:3165$683_Y
+    connect \Y $and$ls180.v:3165$684_Y
   end
-  attribute \src "ls180.v:3182.45-3182.106"
-  cell $and $and$ls180.v:3182$717
+  attribute \src "ls180.v:3167.45-3167.106"
+  cell $and $and$ls180.v:3167$685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250428,43 +249944,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3182$717_Y
+    connect \Y $and$ls180.v:3167$685_Y
   end
-  attribute \src "ls180.v:3182.44-3182.160"
-  cell $and $and$ls180.v:3182$719
+  attribute \src "ls180.v:3167.44-3167.160"
+  cell $and $and$ls180.v:3167$687
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3182$717_Y
-    connect \B $eq$ls180.v:3182$718_Y
-    connect \Y $and$ls180.v:3182$719_Y
+    connect \A $and$ls180.v:3167$685_Y
+    connect \B $eq$ls180.v:3167$686_Y
+    connect \Y $and$ls180.v:3167$687_Y
   end
-  attribute \src "ls180.v:3183.45-3183.109"
-  cell $and $and$ls180.v:3183$721
+  attribute \src "ls180.v:3168.45-3168.109"
+  cell $and $and$ls180.v:3168$689
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3183$720_Y
-    connect \Y $and$ls180.v:3183$721_Y
+    connect \B $not$ls180.v:3168$688_Y
+    connect \Y $and$ls180.v:3168$689_Y
   end
-  attribute \src "ls180.v:3183.44-3183.163"
-  cell $and $and$ls180.v:3183$723
+  attribute \src "ls180.v:3168.44-3168.163"
+  cell $and $and$ls180.v:3168$691
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3183$721_Y
-    connect \B $eq$ls180.v:3183$722_Y
-    connect \Y $and$ls180.v:3183$723_Y
+    connect \A $and$ls180.v:3168$689_Y
+    connect \B $eq$ls180.v:3168$690_Y
+    connect \Y $and$ls180.v:3168$691_Y
   end
-  attribute \src "ls180.v:3185.45-3185.106"
-  cell $and $and$ls180.v:3185$724
+  attribute \src "ls180.v:3170.45-3170.106"
+  cell $and $and$ls180.v:3170$692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250472,43 +249988,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3185$724_Y
+    connect \Y $and$ls180.v:3170$692_Y
   end
-  attribute \src "ls180.v:3185.44-3185.160"
-  cell $and $and$ls180.v:3185$726
+  attribute \src "ls180.v:3170.44-3170.160"
+  cell $and $and$ls180.v:3170$694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3185$724_Y
-    connect \B $eq$ls180.v:3185$725_Y
-    connect \Y $and$ls180.v:3185$726_Y
+    connect \A $and$ls180.v:3170$692_Y
+    connect \B $eq$ls180.v:3170$693_Y
+    connect \Y $and$ls180.v:3170$694_Y
   end
-  attribute \src "ls180.v:3186.45-3186.109"
-  cell $and $and$ls180.v:3186$728
+  attribute \src "ls180.v:3171.45-3171.109"
+  cell $and $and$ls180.v:3171$696
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3186$727_Y
-    connect \Y $and$ls180.v:3186$728_Y
+    connect \B $not$ls180.v:3171$695_Y
+    connect \Y $and$ls180.v:3171$696_Y
   end
-  attribute \src "ls180.v:3186.44-3186.163"
-  cell $and $and$ls180.v:3186$730
+  attribute \src "ls180.v:3171.44-3171.163"
+  cell $and $and$ls180.v:3171$698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3186$728_Y
-    connect \B $eq$ls180.v:3186$729_Y
-    connect \Y $and$ls180.v:3186$730_Y
+    connect \A $and$ls180.v:3171$696_Y
+    connect \B $eq$ls180.v:3171$697_Y
+    connect \Y $and$ls180.v:3171$698_Y
   end
-  attribute \src "ls180.v:3188.45-3188.106"
-  cell $and $and$ls180.v:3188$731
+  attribute \src "ls180.v:3173.45-3173.106"
+  cell $and $and$ls180.v:3173$699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250516,43 +250032,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3188$731_Y
+    connect \Y $and$ls180.v:3173$699_Y
   end
-  attribute \src "ls180.v:3188.44-3188.160"
-  cell $and $and$ls180.v:3188$733
+  attribute \src "ls180.v:3173.44-3173.160"
+  cell $and $and$ls180.v:3173$701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3188$731_Y
-    connect \B $eq$ls180.v:3188$732_Y
-    connect \Y $and$ls180.v:3188$733_Y
+    connect \A $and$ls180.v:3173$699_Y
+    connect \B $eq$ls180.v:3173$700_Y
+    connect \Y $and$ls180.v:3173$701_Y
   end
-  attribute \src "ls180.v:3189.45-3189.109"
-  cell $and $and$ls180.v:3189$735
+  attribute \src "ls180.v:3174.45-3174.109"
+  cell $and $and$ls180.v:3174$703
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3189$734_Y
-    connect \Y $and$ls180.v:3189$735_Y
+    connect \B $not$ls180.v:3174$702_Y
+    connect \Y $and$ls180.v:3174$703_Y
   end
-  attribute \src "ls180.v:3189.44-3189.163"
-  cell $and $and$ls180.v:3189$737
+  attribute \src "ls180.v:3174.44-3174.163"
+  cell $and $and$ls180.v:3174$705
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3189$735_Y
-    connect \B $eq$ls180.v:3189$736_Y
-    connect \Y $and$ls180.v:3189$737_Y
+    connect \A $and$ls180.v:3174$703_Y
+    connect \B $eq$ls180.v:3174$704_Y
+    connect \Y $and$ls180.v:3174$705_Y
   end
-  attribute \src "ls180.v:3191.45-3191.106"
-  cell $and $and$ls180.v:3191$738
+  attribute \src "ls180.v:3176.45-3176.106"
+  cell $and $and$ls180.v:3176$706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250560,43 +250076,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3191$738_Y
+    connect \Y $and$ls180.v:3176$706_Y
   end
-  attribute \src "ls180.v:3191.44-3191.160"
-  cell $and $and$ls180.v:3191$740
+  attribute \src "ls180.v:3176.44-3176.160"
+  cell $and $and$ls180.v:3176$708
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3191$738_Y
-    connect \B $eq$ls180.v:3191$739_Y
-    connect \Y $and$ls180.v:3191$740_Y
+    connect \A $and$ls180.v:3176$706_Y
+    connect \B $eq$ls180.v:3176$707_Y
+    connect \Y $and$ls180.v:3176$708_Y
   end
-  attribute \src "ls180.v:3192.45-3192.109"
-  cell $and $and$ls180.v:3192$742
+  attribute \src "ls180.v:3177.45-3177.109"
+  cell $and $and$ls180.v:3177$710
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3192$741_Y
-    connect \Y $and$ls180.v:3192$742_Y
+    connect \B $not$ls180.v:3177$709_Y
+    connect \Y $and$ls180.v:3177$710_Y
   end
-  attribute \src "ls180.v:3192.44-3192.163"
-  cell $and $and$ls180.v:3192$744
+  attribute \src "ls180.v:3177.44-3177.163"
+  cell $and $and$ls180.v:3177$712
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3192$742_Y
-    connect \B $eq$ls180.v:3192$743_Y
-    connect \Y $and$ls180.v:3192$744_Y
+    connect \A $and$ls180.v:3177$710_Y
+    connect \B $eq$ls180.v:3177$711_Y
+    connect \Y $and$ls180.v:3177$712_Y
   end
-  attribute \src "ls180.v:3194.48-3194.109"
-  cell $and $and$ls180.v:3194$745
+  attribute \src "ls180.v:3179.48-3179.109"
+  cell $and $and$ls180.v:3179$713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250604,43 +250120,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3194$745_Y
+    connect \Y $and$ls180.v:3179$713_Y
   end
-  attribute \src "ls180.v:3194.47-3194.163"
-  cell $and $and$ls180.v:3194$747
+  attribute \src "ls180.v:3179.47-3179.163"
+  cell $and $and$ls180.v:3179$715
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3194$745_Y
-    connect \B $eq$ls180.v:3194$746_Y
-    connect \Y $and$ls180.v:3194$747_Y
+    connect \A $and$ls180.v:3179$713_Y
+    connect \B $eq$ls180.v:3179$714_Y
+    connect \Y $and$ls180.v:3179$715_Y
   end
-  attribute \src "ls180.v:3195.48-3195.112"
-  cell $and $and$ls180.v:3195$749
+  attribute \src "ls180.v:3180.48-3180.112"
+  cell $and $and$ls180.v:3180$717
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3195$748_Y
-    connect \Y $and$ls180.v:3195$749_Y
+    connect \B $not$ls180.v:3180$716_Y
+    connect \Y $and$ls180.v:3180$717_Y
   end
-  attribute \src "ls180.v:3195.47-3195.166"
-  cell $and $and$ls180.v:3195$751
+  attribute \src "ls180.v:3180.47-3180.166"
+  cell $and $and$ls180.v:3180$719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3195$749_Y
-    connect \B $eq$ls180.v:3195$750_Y
-    connect \Y $and$ls180.v:3195$751_Y
+    connect \A $and$ls180.v:3180$717_Y
+    connect \B $eq$ls180.v:3180$718_Y
+    connect \Y $and$ls180.v:3180$719_Y
   end
-  attribute \src "ls180.v:3197.48-3197.109"
-  cell $and $and$ls180.v:3197$752
+  attribute \src "ls180.v:3182.48-3182.109"
+  cell $and $and$ls180.v:3182$720
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250648,43 +250164,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3197$752_Y
+    connect \Y $and$ls180.v:3182$720_Y
   end
-  attribute \src "ls180.v:3197.47-3197.163"
-  cell $and $and$ls180.v:3197$754
+  attribute \src "ls180.v:3182.47-3182.163"
+  cell $and $and$ls180.v:3182$722
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3197$752_Y
-    connect \B $eq$ls180.v:3197$753_Y
-    connect \Y $and$ls180.v:3197$754_Y
+    connect \A $and$ls180.v:3182$720_Y
+    connect \B $eq$ls180.v:3182$721_Y
+    connect \Y $and$ls180.v:3182$722_Y
   end
-  attribute \src "ls180.v:3198.48-3198.112"
-  cell $and $and$ls180.v:3198$756
+  attribute \src "ls180.v:3183.48-3183.112"
+  cell $and $and$ls180.v:3183$724
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3198$755_Y
-    connect \Y $and$ls180.v:3198$756_Y
+    connect \B $not$ls180.v:3183$723_Y
+    connect \Y $and$ls180.v:3183$724_Y
   end
-  attribute \src "ls180.v:3198.47-3198.166"
-  cell $and $and$ls180.v:3198$758
+  attribute \src "ls180.v:3183.47-3183.166"
+  cell $and $and$ls180.v:3183$726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3198$756_Y
-    connect \B $eq$ls180.v:3198$757_Y
-    connect \Y $and$ls180.v:3198$758_Y
+    connect \A $and$ls180.v:3183$724_Y
+    connect \B $eq$ls180.v:3183$725_Y
+    connect \Y $and$ls180.v:3183$726_Y
   end
-  attribute \src "ls180.v:3200.48-3200.109"
-  cell $and $and$ls180.v:3200$759
+  attribute \src "ls180.v:3185.48-3185.109"
+  cell $and $and$ls180.v:3185$727
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250692,43 +250208,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3200$759_Y
+    connect \Y $and$ls180.v:3185$727_Y
   end
-  attribute \src "ls180.v:3200.47-3200.163"
-  cell $and $and$ls180.v:3200$761
+  attribute \src "ls180.v:3185.47-3185.163"
+  cell $and $and$ls180.v:3185$729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3200$759_Y
-    connect \B $eq$ls180.v:3200$760_Y
-    connect \Y $and$ls180.v:3200$761_Y
+    connect \A $and$ls180.v:3185$727_Y
+    connect \B $eq$ls180.v:3185$728_Y
+    connect \Y $and$ls180.v:3185$729_Y
   end
-  attribute \src "ls180.v:3201.48-3201.112"
-  cell $and $and$ls180.v:3201$763
+  attribute \src "ls180.v:3186.48-3186.112"
+  cell $and $and$ls180.v:3186$731
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3201$762_Y
-    connect \Y $and$ls180.v:3201$763_Y
+    connect \B $not$ls180.v:3186$730_Y
+    connect \Y $and$ls180.v:3186$731_Y
   end
-  attribute \src "ls180.v:3201.47-3201.166"
-  cell $and $and$ls180.v:3201$765
+  attribute \src "ls180.v:3186.47-3186.166"
+  cell $and $and$ls180.v:3186$733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3201$763_Y
-    connect \B $eq$ls180.v:3201$764_Y
-    connect \Y $and$ls180.v:3201$765_Y
+    connect \A $and$ls180.v:3186$731_Y
+    connect \B $eq$ls180.v:3186$732_Y
+    connect \Y $and$ls180.v:3186$733_Y
   end
-  attribute \src "ls180.v:3203.48-3203.109"
-  cell $and $and$ls180.v:3203$766
+  attribute \src "ls180.v:3188.48-3188.109"
+  cell $and $and$ls180.v:3188$734
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250736,43 +250252,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
     connect \B \libresocsim_interface0_bank_bus_we
-    connect \Y $and$ls180.v:3203$766_Y
+    connect \Y $and$ls180.v:3188$734_Y
   end
-  attribute \src "ls180.v:3203.47-3203.163"
-  cell $and $and$ls180.v:3203$768
+  attribute \src "ls180.v:3188.47-3188.163"
+  cell $and $and$ls180.v:3188$736
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3203$766_Y
-    connect \B $eq$ls180.v:3203$767_Y
-    connect \Y $and$ls180.v:3203$768_Y
+    connect \A $and$ls180.v:3188$734_Y
+    connect \B $eq$ls180.v:3188$735_Y
+    connect \Y $and$ls180.v:3188$736_Y
   end
-  attribute \src "ls180.v:3204.48-3204.112"
-  cell $and $and$ls180.v:3204$770
+  attribute \src "ls180.v:3189.48-3189.112"
+  cell $and $and$ls180.v:3189$738
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank0_sel
-    connect \B $not$ls180.v:3204$769_Y
-    connect \Y $and$ls180.v:3204$770_Y
+    connect \B $not$ls180.v:3189$737_Y
+    connect \Y $and$ls180.v:3189$738_Y
   end
-  attribute \src "ls180.v:3204.47-3204.166"
-  cell $and $and$ls180.v:3204$772
+  attribute \src "ls180.v:3189.47-3189.166"
+  cell $and $and$ls180.v:3189$740
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3204$770_Y
-    connect \B $eq$ls180.v:3204$771_Y
-    connect \Y $and$ls180.v:3204$772_Y
+    connect \A $and$ls180.v:3189$738_Y
+    connect \B $eq$ls180.v:3189$739_Y
+    connect \Y $and$ls180.v:3189$740_Y
   end
-  attribute \src "ls180.v:3217.40-3217.101"
-  cell $and $and$ls180.v:3217$774
+  attribute \src "ls180.v:3202.40-3202.101"
+  cell $and $and$ls180.v:3202$742
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250780,43 +250296,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
     connect \B \libresocsim_interface1_bank_bus_we
-    connect \Y $and$ls180.v:3217$774_Y
+    connect \Y $and$ls180.v:3202$742_Y
   end
-  attribute \src "ls180.v:3217.39-3217.155"
-  cell $and $and$ls180.v:3217$776
+  attribute \src "ls180.v:3202.39-3202.155"
+  cell $and $and$ls180.v:3202$744
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3217$774_Y
-    connect \B $eq$ls180.v:3217$775_Y
-    connect \Y $and$ls180.v:3217$776_Y
+    connect \A $and$ls180.v:3202$742_Y
+    connect \B $eq$ls180.v:3202$743_Y
+    connect \Y $and$ls180.v:3202$744_Y
   end
-  attribute \src "ls180.v:3218.40-3218.104"
-  cell $and $and$ls180.v:3218$778
+  attribute \src "ls180.v:3203.40-3203.104"
+  cell $and $and$ls180.v:3203$746
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
-    connect \B $not$ls180.v:3218$777_Y
-    connect \Y $and$ls180.v:3218$778_Y
+    connect \B $not$ls180.v:3203$745_Y
+    connect \Y $and$ls180.v:3203$746_Y
   end
-  attribute \src "ls180.v:3218.39-3218.158"
-  cell $and $and$ls180.v:3218$780
+  attribute \src "ls180.v:3203.39-3203.158"
+  cell $and $and$ls180.v:3203$748
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3218$778_Y
-    connect \B $eq$ls180.v:3218$779_Y
-    connect \Y $and$ls180.v:3218$780_Y
+    connect \A $and$ls180.v:3203$746_Y
+    connect \B $eq$ls180.v:3203$747_Y
+    connect \Y $and$ls180.v:3203$748_Y
   end
-  attribute \src "ls180.v:3220.39-3220.100"
-  cell $and $and$ls180.v:3220$781
+  attribute \src "ls180.v:3205.39-3205.100"
+  cell $and $and$ls180.v:3205$749
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250824,43 +250340,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
     connect \B \libresocsim_interface1_bank_bus_we
-    connect \Y $and$ls180.v:3220$781_Y
+    connect \Y $and$ls180.v:3205$749_Y
   end
-  attribute \src "ls180.v:3220.38-3220.154"
-  cell $and $and$ls180.v:3220$783
+  attribute \src "ls180.v:3205.38-3205.154"
+  cell $and $and$ls180.v:3205$751
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3220$781_Y
-    connect \B $eq$ls180.v:3220$782_Y
-    connect \Y $and$ls180.v:3220$783_Y
+    connect \A $and$ls180.v:3205$749_Y
+    connect \B $eq$ls180.v:3205$750_Y
+    connect \Y $and$ls180.v:3205$751_Y
   end
-  attribute \src "ls180.v:3221.39-3221.103"
-  cell $and $and$ls180.v:3221$785
+  attribute \src "ls180.v:3206.39-3206.103"
+  cell $and $and$ls180.v:3206$753
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
-    connect \B $not$ls180.v:3221$784_Y
-    connect \Y $and$ls180.v:3221$785_Y
+    connect \B $not$ls180.v:3206$752_Y
+    connect \Y $and$ls180.v:3206$753_Y
   end
-  attribute \src "ls180.v:3221.38-3221.157"
-  cell $and $and$ls180.v:3221$787
+  attribute \src "ls180.v:3206.38-3206.157"
+  cell $and $and$ls180.v:3206$755
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3221$785_Y
-    connect \B $eq$ls180.v:3221$786_Y
-    connect \Y $and$ls180.v:3221$787_Y
+    connect \A $and$ls180.v:3206$753_Y
+    connect \B $eq$ls180.v:3206$754_Y
+    connect \Y $and$ls180.v:3206$755_Y
   end
-  attribute \src "ls180.v:3223.41-3223.102"
-  cell $and $and$ls180.v:3223$788
+  attribute \src "ls180.v:3208.41-3208.102"
+  cell $and $and$ls180.v:3208$756
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250868,43 +250384,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
     connect \B \libresocsim_interface1_bank_bus_we
-    connect \Y $and$ls180.v:3223$788_Y
+    connect \Y $and$ls180.v:3208$756_Y
   end
-  attribute \src "ls180.v:3223.40-3223.156"
-  cell $and $and$ls180.v:3223$790
+  attribute \src "ls180.v:3208.40-3208.156"
+  cell $and $and$ls180.v:3208$758
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3223$788_Y
-    connect \B $eq$ls180.v:3223$789_Y
-    connect \Y $and$ls180.v:3223$790_Y
+    connect \A $and$ls180.v:3208$756_Y
+    connect \B $eq$ls180.v:3208$757_Y
+    connect \Y $and$ls180.v:3208$758_Y
   end
-  attribute \src "ls180.v:3224.41-3224.105"
-  cell $and $and$ls180.v:3224$792
+  attribute \src "ls180.v:3209.41-3209.105"
+  cell $and $and$ls180.v:3209$760
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank1_sel
-    connect \B $not$ls180.v:3224$791_Y
-    connect \Y $and$ls180.v:3224$792_Y
+    connect \B $not$ls180.v:3209$759_Y
+    connect \Y $and$ls180.v:3209$760_Y
   end
-  attribute \src "ls180.v:3224.40-3224.159"
-  cell $and $and$ls180.v:3224$794
+  attribute \src "ls180.v:3209.40-3209.159"
+  cell $and $and$ls180.v:3209$762
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3224$792_Y
-    connect \B $eq$ls180.v:3224$793_Y
-    connect \Y $and$ls180.v:3224$794_Y
+    connect \A $and$ls180.v:3209$760_Y
+    connect \B $eq$ls180.v:3209$761_Y
+    connect \Y $and$ls180.v:3209$762_Y
   end
-  attribute \src "ls180.v:3231.40-3231.101"
-  cell $and $and$ls180.v:3231$796
+  attribute \src "ls180.v:3216.40-3216.101"
+  cell $and $and$ls180.v:3216$764
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250912,43 +250428,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
     connect \B \libresocsim_interface2_bank_bus_we
-    connect \Y $and$ls180.v:3231$796_Y
+    connect \Y $and$ls180.v:3216$764_Y
   end
-  attribute \src "ls180.v:3231.39-3231.155"
-  cell $and $and$ls180.v:3231$798
+  attribute \src "ls180.v:3216.39-3216.155"
+  cell $and $and$ls180.v:3216$766
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3231$796_Y
-    connect \B $eq$ls180.v:3231$797_Y
-    connect \Y $and$ls180.v:3231$798_Y
+    connect \A $and$ls180.v:3216$764_Y
+    connect \B $eq$ls180.v:3216$765_Y
+    connect \Y $and$ls180.v:3216$766_Y
   end
-  attribute \src "ls180.v:3232.40-3232.104"
-  cell $and $and$ls180.v:3232$800
+  attribute \src "ls180.v:3217.40-3217.104"
+  cell $and $and$ls180.v:3217$768
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
-    connect \B $not$ls180.v:3232$799_Y
-    connect \Y $and$ls180.v:3232$800_Y
+    connect \B $not$ls180.v:3217$767_Y
+    connect \Y $and$ls180.v:3217$768_Y
   end
-  attribute \src "ls180.v:3232.39-3232.158"
-  cell $and $and$ls180.v:3232$802
+  attribute \src "ls180.v:3217.39-3217.158"
+  cell $and $and$ls180.v:3217$770
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3232$800_Y
-    connect \B $eq$ls180.v:3232$801_Y
-    connect \Y $and$ls180.v:3232$802_Y
+    connect \A $and$ls180.v:3217$768_Y
+    connect \B $eq$ls180.v:3217$769_Y
+    connect \Y $and$ls180.v:3217$770_Y
   end
-  attribute \src "ls180.v:3234.39-3234.100"
-  cell $and $and$ls180.v:3234$803
+  attribute \src "ls180.v:3219.39-3219.100"
+  cell $and $and$ls180.v:3219$771
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -250956,43 +250472,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
     connect \B \libresocsim_interface2_bank_bus_we
-    connect \Y $and$ls180.v:3234$803_Y
+    connect \Y $and$ls180.v:3219$771_Y
   end
-  attribute \src "ls180.v:3234.38-3234.154"
-  cell $and $and$ls180.v:3234$805
+  attribute \src "ls180.v:3219.38-3219.154"
+  cell $and $and$ls180.v:3219$773
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3234$803_Y
-    connect \B $eq$ls180.v:3234$804_Y
-    connect \Y $and$ls180.v:3234$805_Y
+    connect \A $and$ls180.v:3219$771_Y
+    connect \B $eq$ls180.v:3219$772_Y
+    connect \Y $and$ls180.v:3219$773_Y
   end
-  attribute \src "ls180.v:3235.39-3235.103"
-  cell $and $and$ls180.v:3235$807
+  attribute \src "ls180.v:3220.39-3220.103"
+  cell $and $and$ls180.v:3220$775
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
-    connect \B $not$ls180.v:3235$806_Y
-    connect \Y $and$ls180.v:3235$807_Y
+    connect \B $not$ls180.v:3220$774_Y
+    connect \Y $and$ls180.v:3220$775_Y
   end
-  attribute \src "ls180.v:3235.38-3235.157"
-  cell $and $and$ls180.v:3235$809
+  attribute \src "ls180.v:3220.38-3220.157"
+  cell $and $and$ls180.v:3220$777
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3235$807_Y
-    connect \B $eq$ls180.v:3235$808_Y
-    connect \Y $and$ls180.v:3235$809_Y
+    connect \A $and$ls180.v:3220$775_Y
+    connect \B $eq$ls180.v:3220$776_Y
+    connect \Y $and$ls180.v:3220$777_Y
   end
-  attribute \src "ls180.v:3237.41-3237.102"
-  cell $and $and$ls180.v:3237$810
+  attribute \src "ls180.v:3222.41-3222.102"
+  cell $and $and$ls180.v:3222$778
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251000,43 +250516,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
     connect \B \libresocsim_interface2_bank_bus_we
-    connect \Y $and$ls180.v:3237$810_Y
+    connect \Y $and$ls180.v:3222$778_Y
   end
-  attribute \src "ls180.v:3237.40-3237.156"
-  cell $and $and$ls180.v:3237$812
+  attribute \src "ls180.v:3222.40-3222.156"
+  cell $and $and$ls180.v:3222$780
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3237$810_Y
-    connect \B $eq$ls180.v:3237$811_Y
-    connect \Y $and$ls180.v:3237$812_Y
+    connect \A $and$ls180.v:3222$778_Y
+    connect \B $eq$ls180.v:3222$779_Y
+    connect \Y $and$ls180.v:3222$780_Y
   end
-  attribute \src "ls180.v:3238.41-3238.105"
-  cell $and $and$ls180.v:3238$814
+  attribute \src "ls180.v:3223.41-3223.105"
+  cell $and $and$ls180.v:3223$782
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank2_sel
-    connect \B $not$ls180.v:3238$813_Y
-    connect \Y $and$ls180.v:3238$814_Y
+    connect \B $not$ls180.v:3223$781_Y
+    connect \Y $and$ls180.v:3223$782_Y
   end
-  attribute \src "ls180.v:3238.40-3238.159"
-  cell $and $and$ls180.v:3238$816
+  attribute \src "ls180.v:3223.40-3223.159"
+  cell $and $and$ls180.v:3223$784
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3238$814_Y
-    connect \B $eq$ls180.v:3238$815_Y
-    connect \Y $and$ls180.v:3238$816_Y
+    connect \A $and$ls180.v:3223$782_Y
+    connect \B $eq$ls180.v:3223$783_Y
+    connect \Y $and$ls180.v:3223$784_Y
   end
-  attribute \src "ls180.v:3245.39-3245.100"
-  cell $and $and$ls180.v:3245$818
+  attribute \src "ls180.v:3230.39-3230.100"
+  cell $and $and$ls180.v:3230$786
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251044,43 +250560,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank3_sel
     connect \B \libresocsim_interface3_bank_bus_we
-    connect \Y $and$ls180.v:3245$818_Y
+    connect \Y $and$ls180.v:3230$786_Y
   end
-  attribute \src "ls180.v:3245.38-3245.152"
-  cell $and $and$ls180.v:3245$820
+  attribute \src "ls180.v:3230.38-3230.152"
+  cell $and $and$ls180.v:3230$788
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3245$818_Y
-    connect \B $eq$ls180.v:3245$819_Y
-    connect \Y $and$ls180.v:3245$820_Y
+    connect \A $and$ls180.v:3230$786_Y
+    connect \B $eq$ls180.v:3230$787_Y
+    connect \Y $and$ls180.v:3230$788_Y
   end
-  attribute \src "ls180.v:3246.39-3246.103"
-  cell $and $and$ls180.v:3246$822
+  attribute \src "ls180.v:3231.39-3231.103"
+  cell $and $and$ls180.v:3231$790
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank3_sel
-    connect \B $not$ls180.v:3246$821_Y
-    connect \Y $and$ls180.v:3246$822_Y
+    connect \B $not$ls180.v:3231$789_Y
+    connect \Y $and$ls180.v:3231$790_Y
   end
-  attribute \src "ls180.v:3246.38-3246.155"
-  cell $and $and$ls180.v:3246$824
+  attribute \src "ls180.v:3231.38-3231.155"
+  cell $and $and$ls180.v:3231$792
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3246$822_Y
-    connect \B $eq$ls180.v:3246$823_Y
-    connect \Y $and$ls180.v:3246$824_Y
+    connect \A $and$ls180.v:3231$790_Y
+    connect \B $eq$ls180.v:3231$791_Y
+    connect \Y $and$ls180.v:3231$792_Y
   end
-  attribute \src "ls180.v:3248.38-3248.99"
-  cell $and $and$ls180.v:3248$825
+  attribute \src "ls180.v:3233.38-3233.99"
+  cell $and $and$ls180.v:3233$793
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251088,43 +250604,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank3_sel
     connect \B \libresocsim_interface3_bank_bus_we
-    connect \Y $and$ls180.v:3248$825_Y
+    connect \Y $and$ls180.v:3233$793_Y
   end
-  attribute \src "ls180.v:3248.37-3248.151"
-  cell $and $and$ls180.v:3248$827
+  attribute \src "ls180.v:3233.37-3233.151"
+  cell $and $and$ls180.v:3233$795
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3248$825_Y
-    connect \B $eq$ls180.v:3248$826_Y
-    connect \Y $and$ls180.v:3248$827_Y
+    connect \A $and$ls180.v:3233$793_Y
+    connect \B $eq$ls180.v:3233$794_Y
+    connect \Y $and$ls180.v:3233$795_Y
   end
-  attribute \src "ls180.v:3249.38-3249.102"
-  cell $and $and$ls180.v:3249$829
+  attribute \src "ls180.v:3234.38-3234.102"
+  cell $and $and$ls180.v:3234$797
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank3_sel
-    connect \B $not$ls180.v:3249$828_Y
-    connect \Y $and$ls180.v:3249$829_Y
+    connect \B $not$ls180.v:3234$796_Y
+    connect \Y $and$ls180.v:3234$797_Y
   end
-  attribute \src "ls180.v:3249.37-3249.154"
-  cell $and $and$ls180.v:3249$831
+  attribute \src "ls180.v:3234.37-3234.154"
+  cell $and $and$ls180.v:3234$799
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3249$829_Y
-    connect \B $eq$ls180.v:3249$830_Y
-    connect \Y $and$ls180.v:3249$831_Y
+    connect \A $and$ls180.v:3234$797_Y
+    connect \B $eq$ls180.v:3234$798_Y
+    connect \Y $and$ls180.v:3234$799_Y
   end
-  attribute \src "ls180.v:3259.50-3259.111"
-  cell $and $and$ls180.v:3259$833
+  attribute \src "ls180.v:3244.50-3244.111"
+  cell $and $and$ls180.v:3244$801
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251132,43 +250648,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3259$833_Y
+    connect \Y $and$ls180.v:3244$801_Y
   end
-  attribute \src "ls180.v:3259.49-3259.165"
-  cell $and $and$ls180.v:3259$835
+  attribute \src "ls180.v:3244.49-3244.165"
+  cell $and $and$ls180.v:3244$803
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3259$833_Y
-    connect \B $eq$ls180.v:3259$834_Y
-    connect \Y $and$ls180.v:3259$835_Y
+    connect \A $and$ls180.v:3244$801_Y
+    connect \B $eq$ls180.v:3244$802_Y
+    connect \Y $and$ls180.v:3244$803_Y
   end
-  attribute \src "ls180.v:3260.50-3260.114"
-  cell $and $and$ls180.v:3260$837
+  attribute \src "ls180.v:3245.50-3245.114"
+  cell $and $and$ls180.v:3245$805
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3260$836_Y
-    connect \Y $and$ls180.v:3260$837_Y
+    connect \B $not$ls180.v:3245$804_Y
+    connect \Y $and$ls180.v:3245$805_Y
   end
-  attribute \src "ls180.v:3260.49-3260.168"
-  cell $and $and$ls180.v:3260$839
+  attribute \src "ls180.v:3245.49-3245.168"
+  cell $and $and$ls180.v:3245$807
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3260$837_Y
-    connect \B $eq$ls180.v:3260$838_Y
-    connect \Y $and$ls180.v:3260$839_Y
+    connect \A $and$ls180.v:3245$805_Y
+    connect \B $eq$ls180.v:3245$806_Y
+    connect \Y $and$ls180.v:3245$807_Y
   end
-  attribute \src "ls180.v:3262.54-3262.115"
-  cell $and $and$ls180.v:3262$840
+  attribute \src "ls180.v:3247.54-3247.115"
+  cell $and $and$ls180.v:3247$808
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251176,43 +250692,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3262$840_Y
+    connect \Y $and$ls180.v:3247$808_Y
   end
-  attribute \src "ls180.v:3262.53-3262.169"
-  cell $and $and$ls180.v:3262$842
+  attribute \src "ls180.v:3247.53-3247.169"
+  cell $and $and$ls180.v:3247$810
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3262$840_Y
-    connect \B $eq$ls180.v:3262$841_Y
-    connect \Y $and$ls180.v:3262$842_Y
+    connect \A $and$ls180.v:3247$808_Y
+    connect \B $eq$ls180.v:3247$809_Y
+    connect \Y $and$ls180.v:3247$810_Y
   end
-  attribute \src "ls180.v:3263.54-3263.118"
-  cell $and $and$ls180.v:3263$844
+  attribute \src "ls180.v:3248.54-3248.118"
+  cell $and $and$ls180.v:3248$812
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3263$843_Y
-    connect \Y $and$ls180.v:3263$844_Y
+    connect \B $not$ls180.v:3248$811_Y
+    connect \Y $and$ls180.v:3248$812_Y
   end
-  attribute \src "ls180.v:3263.53-3263.172"
-  cell $and $and$ls180.v:3263$846
+  attribute \src "ls180.v:3248.53-3248.172"
+  cell $and $and$ls180.v:3248$814
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3263$844_Y
-    connect \B $eq$ls180.v:3263$845_Y
-    connect \Y $and$ls180.v:3263$846_Y
+    connect \A $and$ls180.v:3248$812_Y
+    connect \B $eq$ls180.v:3248$813_Y
+    connect \Y $and$ls180.v:3248$814_Y
   end
-  attribute \src "ls180.v:3265.35-3265.96"
-  cell $and $and$ls180.v:3265$847
+  attribute \src "ls180.v:3250.35-3250.96"
+  cell $and $and$ls180.v:3250$815
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251220,43 +250736,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3265$847_Y
+    connect \Y $and$ls180.v:3250$815_Y
   end
-  attribute \src "ls180.v:3265.34-3265.150"
-  cell $and $and$ls180.v:3265$849
+  attribute \src "ls180.v:3250.34-3250.150"
+  cell $and $and$ls180.v:3250$817
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3265$847_Y
-    connect \B $eq$ls180.v:3265$848_Y
-    connect \Y $and$ls180.v:3265$849_Y
+    connect \A $and$ls180.v:3250$815_Y
+    connect \B $eq$ls180.v:3250$816_Y
+    connect \Y $and$ls180.v:3250$817_Y
   end
-  attribute \src "ls180.v:3266.35-3266.99"
-  cell $and $and$ls180.v:3266$851
+  attribute \src "ls180.v:3251.35-3251.99"
+  cell $and $and$ls180.v:3251$819
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3266$850_Y
-    connect \Y $and$ls180.v:3266$851_Y
+    connect \B $not$ls180.v:3251$818_Y
+    connect \Y $and$ls180.v:3251$819_Y
   end
-  attribute \src "ls180.v:3266.34-3266.153"
-  cell $and $and$ls180.v:3266$853
+  attribute \src "ls180.v:3251.34-3251.153"
+  cell $and $and$ls180.v:3251$821
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3266$851_Y
-    connect \B $eq$ls180.v:3266$852_Y
-    connect \Y $and$ls180.v:3266$853_Y
+    connect \A $and$ls180.v:3251$819_Y
+    connect \B $eq$ls180.v:3251$820_Y
+    connect \Y $and$ls180.v:3251$821_Y
   end
-  attribute \src "ls180.v:3268.54-3268.115"
-  cell $and $and$ls180.v:3268$854
+  attribute \src "ls180.v:3253.54-3253.115"
+  cell $and $and$ls180.v:3253$822
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251264,43 +250780,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3268$854_Y
+    connect \Y $and$ls180.v:3253$822_Y
   end
-  attribute \src "ls180.v:3268.53-3268.169"
-  cell $and $and$ls180.v:3268$856
+  attribute \src "ls180.v:3253.53-3253.169"
+  cell $and $and$ls180.v:3253$824
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3268$854_Y
-    connect \B $eq$ls180.v:3268$855_Y
-    connect \Y $and$ls180.v:3268$856_Y
+    connect \A $and$ls180.v:3253$822_Y
+    connect \B $eq$ls180.v:3253$823_Y
+    connect \Y $and$ls180.v:3253$824_Y
   end
-  attribute \src "ls180.v:3269.54-3269.118"
-  cell $and $and$ls180.v:3269$858
+  attribute \src "ls180.v:3254.54-3254.118"
+  cell $and $and$ls180.v:3254$826
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3269$857_Y
-    connect \Y $and$ls180.v:3269$858_Y
+    connect \B $not$ls180.v:3254$825_Y
+    connect \Y $and$ls180.v:3254$826_Y
   end
-  attribute \src "ls180.v:3269.53-3269.172"
-  cell $and $and$ls180.v:3269$860
+  attribute \src "ls180.v:3254.53-3254.172"
+  cell $and $and$ls180.v:3254$828
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3269$858_Y
-    connect \B $eq$ls180.v:3269$859_Y
-    connect \Y $and$ls180.v:3269$860_Y
+    connect \A $and$ls180.v:3254$826_Y
+    connect \B $eq$ls180.v:3254$827_Y
+    connect \Y $and$ls180.v:3254$828_Y
   end
-  attribute \src "ls180.v:3271.54-3271.115"
-  cell $and $and$ls180.v:3271$861
+  attribute \src "ls180.v:3256.54-3256.115"
+  cell $and $and$ls180.v:3256$829
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251308,43 +250824,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3271$861_Y
+    connect \Y $and$ls180.v:3256$829_Y
   end
-  attribute \src "ls180.v:3271.53-3271.169"
-  cell $and $and$ls180.v:3271$863
+  attribute \src "ls180.v:3256.53-3256.169"
+  cell $and $and$ls180.v:3256$831
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3271$861_Y
-    connect \B $eq$ls180.v:3271$862_Y
-    connect \Y $and$ls180.v:3271$863_Y
+    connect \A $and$ls180.v:3256$829_Y
+    connect \B $eq$ls180.v:3256$830_Y
+    connect \Y $and$ls180.v:3256$831_Y
   end
-  attribute \src "ls180.v:3272.54-3272.118"
-  cell $and $and$ls180.v:3272$865
+  attribute \src "ls180.v:3257.54-3257.118"
+  cell $and $and$ls180.v:3257$833
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3272$864_Y
-    connect \Y $and$ls180.v:3272$865_Y
+    connect \B $not$ls180.v:3257$832_Y
+    connect \Y $and$ls180.v:3257$833_Y
   end
-  attribute \src "ls180.v:3272.53-3272.172"
-  cell $and $and$ls180.v:3272$867
+  attribute \src "ls180.v:3257.53-3257.172"
+  cell $and $and$ls180.v:3257$835
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3272$865_Y
-    connect \B $eq$ls180.v:3272$866_Y
-    connect \Y $and$ls180.v:3272$867_Y
+    connect \A $and$ls180.v:3257$833_Y
+    connect \B $eq$ls180.v:3257$834_Y
+    connect \Y $and$ls180.v:3257$835_Y
   end
-  attribute \src "ls180.v:3274.55-3274.116"
-  cell $and $and$ls180.v:3274$868
+  attribute \src "ls180.v:3259.55-3259.116"
+  cell $and $and$ls180.v:3259$836
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251352,43 +250868,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3274$868_Y
+    connect \Y $and$ls180.v:3259$836_Y
   end
-  attribute \src "ls180.v:3274.54-3274.170"
-  cell $and $and$ls180.v:3274$870
+  attribute \src "ls180.v:3259.54-3259.170"
+  cell $and $and$ls180.v:3259$838
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3274$868_Y
-    connect \B $eq$ls180.v:3274$869_Y
-    connect \Y $and$ls180.v:3274$870_Y
+    connect \A $and$ls180.v:3259$836_Y
+    connect \B $eq$ls180.v:3259$837_Y
+    connect \Y $and$ls180.v:3259$838_Y
   end
-  attribute \src "ls180.v:3275.55-3275.119"
-  cell $and $and$ls180.v:3275$872
+  attribute \src "ls180.v:3260.55-3260.119"
+  cell $and $and$ls180.v:3260$840
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3275$871_Y
-    connect \Y $and$ls180.v:3275$872_Y
+    connect \B $not$ls180.v:3260$839_Y
+    connect \Y $and$ls180.v:3260$840_Y
   end
-  attribute \src "ls180.v:3275.54-3275.173"
-  cell $and $and$ls180.v:3275$874
+  attribute \src "ls180.v:3260.54-3260.173"
+  cell $and $and$ls180.v:3260$842
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3275$872_Y
-    connect \B $eq$ls180.v:3275$873_Y
-    connect \Y $and$ls180.v:3275$874_Y
+    connect \A $and$ls180.v:3260$840_Y
+    connect \B $eq$ls180.v:3260$841_Y
+    connect \Y $and$ls180.v:3260$842_Y
   end
-  attribute \src "ls180.v:3277.53-3277.114"
-  cell $and $and$ls180.v:3277$875
+  attribute \src "ls180.v:3262.53-3262.114"
+  cell $and $and$ls180.v:3262$843
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251396,43 +250912,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3277$875_Y
+    connect \Y $and$ls180.v:3262$843_Y
   end
-  attribute \src "ls180.v:3277.52-3277.168"
-  cell $and $and$ls180.v:3277$877
+  attribute \src "ls180.v:3262.52-3262.168"
+  cell $and $and$ls180.v:3262$845
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3277$875_Y
-    connect \B $eq$ls180.v:3277$876_Y
-    connect \Y $and$ls180.v:3277$877_Y
+    connect \A $and$ls180.v:3262$843_Y
+    connect \B $eq$ls180.v:3262$844_Y
+    connect \Y $and$ls180.v:3262$845_Y
   end
-  attribute \src "ls180.v:3278.53-3278.117"
-  cell $and $and$ls180.v:3278$879
+  attribute \src "ls180.v:3263.53-3263.117"
+  cell $and $and$ls180.v:3263$847
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3278$878_Y
-    connect \Y $and$ls180.v:3278$879_Y
+    connect \B $not$ls180.v:3263$846_Y
+    connect \Y $and$ls180.v:3263$847_Y
   end
-  attribute \src "ls180.v:3278.52-3278.171"
-  cell $and $and$ls180.v:3278$881
+  attribute \src "ls180.v:3263.52-3263.171"
+  cell $and $and$ls180.v:3263$849
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3278$879_Y
-    connect \B $eq$ls180.v:3278$880_Y
-    connect \Y $and$ls180.v:3278$881_Y
+    connect \A $and$ls180.v:3263$847_Y
+    connect \B $eq$ls180.v:3263$848_Y
+    connect \Y $and$ls180.v:3263$849_Y
   end
-  attribute \src "ls180.v:3280.53-3280.114"
-  cell $and $and$ls180.v:3280$882
+  attribute \src "ls180.v:3265.53-3265.114"
+  cell $and $and$ls180.v:3265$850
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251440,43 +250956,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3280$882_Y
+    connect \Y $and$ls180.v:3265$850_Y
   end
-  attribute \src "ls180.v:3280.52-3280.168"
-  cell $and $and$ls180.v:3280$884
+  attribute \src "ls180.v:3265.52-3265.168"
+  cell $and $and$ls180.v:3265$852
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3280$882_Y
-    connect \B $eq$ls180.v:3280$883_Y
-    connect \Y $and$ls180.v:3280$884_Y
+    connect \A $and$ls180.v:3265$850_Y
+    connect \B $eq$ls180.v:3265$851_Y
+    connect \Y $and$ls180.v:3265$852_Y
   end
-  attribute \src "ls180.v:3281.53-3281.117"
-  cell $and $and$ls180.v:3281$886
+  attribute \src "ls180.v:3266.53-3266.117"
+  cell $and $and$ls180.v:3266$854
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3281$885_Y
-    connect \Y $and$ls180.v:3281$886_Y
+    connect \B $not$ls180.v:3266$853_Y
+    connect \Y $and$ls180.v:3266$854_Y
   end
-  attribute \src "ls180.v:3281.52-3281.171"
-  cell $and $and$ls180.v:3281$888
+  attribute \src "ls180.v:3266.52-3266.171"
+  cell $and $and$ls180.v:3266$856
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3281$886_Y
-    connect \B $eq$ls180.v:3281$887_Y
-    connect \Y $and$ls180.v:3281$888_Y
+    connect \A $and$ls180.v:3266$854_Y
+    connect \B $eq$ls180.v:3266$855_Y
+    connect \Y $and$ls180.v:3266$856_Y
   end
-  attribute \src "ls180.v:3283.53-3283.114"
-  cell $and $and$ls180.v:3283$889
+  attribute \src "ls180.v:3268.53-3268.114"
+  cell $and $and$ls180.v:3268$857
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251484,43 +251000,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3283$889_Y
+    connect \Y $and$ls180.v:3268$857_Y
   end
-  attribute \src "ls180.v:3283.52-3283.168"
-  cell $and $and$ls180.v:3283$891
+  attribute \src "ls180.v:3268.52-3268.168"
+  cell $and $and$ls180.v:3268$859
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3283$889_Y
-    connect \B $eq$ls180.v:3283$890_Y
-    connect \Y $and$ls180.v:3283$891_Y
+    connect \A $and$ls180.v:3268$857_Y
+    connect \B $eq$ls180.v:3268$858_Y
+    connect \Y $and$ls180.v:3268$859_Y
   end
-  attribute \src "ls180.v:3284.53-3284.117"
-  cell $and $and$ls180.v:3284$893
+  attribute \src "ls180.v:3269.53-3269.117"
+  cell $and $and$ls180.v:3269$861
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3284$892_Y
-    connect \Y $and$ls180.v:3284$893_Y
+    connect \B $not$ls180.v:3269$860_Y
+    connect \Y $and$ls180.v:3269$861_Y
   end
-  attribute \src "ls180.v:3284.52-3284.171"
-  cell $and $and$ls180.v:3284$895
+  attribute \src "ls180.v:3269.52-3269.171"
+  cell $and $and$ls180.v:3269$863
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3284$893_Y
-    connect \B $eq$ls180.v:3284$894_Y
-    connect \Y $and$ls180.v:3284$895_Y
+    connect \A $and$ls180.v:3269$861_Y
+    connect \B $eq$ls180.v:3269$862_Y
+    connect \Y $and$ls180.v:3269$863_Y
   end
-  attribute \src "ls180.v:3286.53-3286.114"
-  cell $and $and$ls180.v:3286$896
+  attribute \src "ls180.v:3271.53-3271.114"
+  cell $and $and$ls180.v:3271$864
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251528,43 +251044,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
     connect \B \libresocsim_interface4_bank_bus_we
-    connect \Y $and$ls180.v:3286$896_Y
+    connect \Y $and$ls180.v:3271$864_Y
   end
-  attribute \src "ls180.v:3286.52-3286.168"
-  cell $and $and$ls180.v:3286$898
+  attribute \src "ls180.v:3271.52-3271.168"
+  cell $and $and$ls180.v:3271$866
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3286$896_Y
-    connect \B $eq$ls180.v:3286$897_Y
-    connect \Y $and$ls180.v:3286$898_Y
+    connect \A $and$ls180.v:3271$864_Y
+    connect \B $eq$ls180.v:3271$865_Y
+    connect \Y $and$ls180.v:3271$866_Y
   end
-  attribute \src "ls180.v:3287.53-3287.117"
-  cell $and $and$ls180.v:3287$900
+  attribute \src "ls180.v:3272.53-3272.117"
+  cell $and $and$ls180.v:3272$868
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank4_sel
-    connect \B $not$ls180.v:3287$899_Y
-    connect \Y $and$ls180.v:3287$900_Y
+    connect \B $not$ls180.v:3272$867_Y
+    connect \Y $and$ls180.v:3272$868_Y
   end
-  attribute \src "ls180.v:3287.52-3287.171"
-  cell $and $and$ls180.v:3287$902
+  attribute \src "ls180.v:3272.52-3272.171"
+  cell $and $and$ls180.v:3272$870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3287$900_Y
-    connect \B $eq$ls180.v:3287$901_Y
-    connect \Y $and$ls180.v:3287$902_Y
+    connect \A $and$ls180.v:3272$868_Y
+    connect \B $eq$ls180.v:3272$869_Y
+    connect \Y $and$ls180.v:3272$870_Y
   end
-  attribute \src "ls180.v:3304.42-3304.103"
-  cell $and $and$ls180.v:3304$904
+  attribute \src "ls180.v:3289.42-3289.103"
+  cell $and $and$ls180.v:3289$872
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251572,43 +251088,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3304$904_Y
+    connect \Y $and$ls180.v:3289$872_Y
   end
-  attribute \src "ls180.v:3304.41-3304.157"
-  cell $and $and$ls180.v:3304$906
+  attribute \src "ls180.v:3289.41-3289.157"
+  cell $and $and$ls180.v:3289$874
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3304$904_Y
-    connect \B $eq$ls180.v:3304$905_Y
-    connect \Y $and$ls180.v:3304$906_Y
+    connect \A $and$ls180.v:3289$872_Y
+    connect \B $eq$ls180.v:3289$873_Y
+    connect \Y $and$ls180.v:3289$874_Y
   end
-  attribute \src "ls180.v:3305.42-3305.106"
-  cell $and $and$ls180.v:3305$908
+  attribute \src "ls180.v:3290.42-3290.106"
+  cell $and $and$ls180.v:3290$876
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3305$907_Y
-    connect \Y $and$ls180.v:3305$908_Y
+    connect \B $not$ls180.v:3290$875_Y
+    connect \Y $and$ls180.v:3290$876_Y
   end
-  attribute \src "ls180.v:3305.41-3305.160"
-  cell $and $and$ls180.v:3305$910
+  attribute \src "ls180.v:3290.41-3290.160"
+  cell $and $and$ls180.v:3290$878
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3305$908_Y
-    connect \B $eq$ls180.v:3305$909_Y
-    connect \Y $and$ls180.v:3305$910_Y
+    connect \A $and$ls180.v:3290$876_Y
+    connect \B $eq$ls180.v:3290$877_Y
+    connect \Y $and$ls180.v:3290$878_Y
   end
-  attribute \src "ls180.v:3307.42-3307.103"
-  cell $and $and$ls180.v:3307$911
+  attribute \src "ls180.v:3292.42-3292.103"
+  cell $and $and$ls180.v:3292$879
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251616,43 +251132,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3307$911_Y
+    connect \Y $and$ls180.v:3292$879_Y
   end
-  attribute \src "ls180.v:3307.41-3307.157"
-  cell $and $and$ls180.v:3307$913
+  attribute \src "ls180.v:3292.41-3292.157"
+  cell $and $and$ls180.v:3292$881
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3307$911_Y
-    connect \B $eq$ls180.v:3307$912_Y
-    connect \Y $and$ls180.v:3307$913_Y
+    connect \A $and$ls180.v:3292$879_Y
+    connect \B $eq$ls180.v:3292$880_Y
+    connect \Y $and$ls180.v:3292$881_Y
   end
-  attribute \src "ls180.v:3308.42-3308.106"
-  cell $and $and$ls180.v:3308$915
+  attribute \src "ls180.v:3293.42-3293.106"
+  cell $and $and$ls180.v:3293$883
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3308$914_Y
-    connect \Y $and$ls180.v:3308$915_Y
+    connect \B $not$ls180.v:3293$882_Y
+    connect \Y $and$ls180.v:3293$883_Y
   end
-  attribute \src "ls180.v:3308.41-3308.160"
-  cell $and $and$ls180.v:3308$917
+  attribute \src "ls180.v:3293.41-3293.160"
+  cell $and $and$ls180.v:3293$885
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3308$915_Y
-    connect \B $eq$ls180.v:3308$916_Y
-    connect \Y $and$ls180.v:3308$917_Y
+    connect \A $and$ls180.v:3293$883_Y
+    connect \B $eq$ls180.v:3293$884_Y
+    connect \Y $and$ls180.v:3293$885_Y
   end
-  attribute \src "ls180.v:3310.42-3310.103"
-  cell $and $and$ls180.v:3310$918
+  attribute \src "ls180.v:3295.42-3295.103"
+  cell $and $and$ls180.v:3295$886
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251660,43 +251176,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3310$918_Y
+    connect \Y $and$ls180.v:3295$886_Y
   end
-  attribute \src "ls180.v:3310.41-3310.157"
-  cell $and $and$ls180.v:3310$920
+  attribute \src "ls180.v:3295.41-3295.157"
+  cell $and $and$ls180.v:3295$888
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3310$918_Y
-    connect \B $eq$ls180.v:3310$919_Y
-    connect \Y $and$ls180.v:3310$920_Y
+    connect \A $and$ls180.v:3295$886_Y
+    connect \B $eq$ls180.v:3295$887_Y
+    connect \Y $and$ls180.v:3295$888_Y
   end
-  attribute \src "ls180.v:3311.42-3311.106"
-  cell $and $and$ls180.v:3311$922
+  attribute \src "ls180.v:3296.42-3296.106"
+  cell $and $and$ls180.v:3296$890
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3311$921_Y
-    connect \Y $and$ls180.v:3311$922_Y
+    connect \B $not$ls180.v:3296$889_Y
+    connect \Y $and$ls180.v:3296$890_Y
   end
-  attribute \src "ls180.v:3311.41-3311.160"
-  cell $and $and$ls180.v:3311$924
+  attribute \src "ls180.v:3296.41-3296.160"
+  cell $and $and$ls180.v:3296$892
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3311$922_Y
-    connect \B $eq$ls180.v:3311$923_Y
-    connect \Y $and$ls180.v:3311$924_Y
+    connect \A $and$ls180.v:3296$890_Y
+    connect \B $eq$ls180.v:3296$891_Y
+    connect \Y $and$ls180.v:3296$892_Y
   end
-  attribute \src "ls180.v:3313.42-3313.103"
-  cell $and $and$ls180.v:3313$925
+  attribute \src "ls180.v:3298.42-3298.103"
+  cell $and $and$ls180.v:3298$893
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251704,43 +251220,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3313$925_Y
+    connect \Y $and$ls180.v:3298$893_Y
   end
-  attribute \src "ls180.v:3313.41-3313.157"
-  cell $and $and$ls180.v:3313$927
+  attribute \src "ls180.v:3298.41-3298.157"
+  cell $and $and$ls180.v:3298$895
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3313$925_Y
-    connect \B $eq$ls180.v:3313$926_Y
-    connect \Y $and$ls180.v:3313$927_Y
+    connect \A $and$ls180.v:3298$893_Y
+    connect \B $eq$ls180.v:3298$894_Y
+    connect \Y $and$ls180.v:3298$895_Y
   end
-  attribute \src "ls180.v:3314.42-3314.106"
-  cell $and $and$ls180.v:3314$929
+  attribute \src "ls180.v:3299.42-3299.106"
+  cell $and $and$ls180.v:3299$897
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3314$928_Y
-    connect \Y $and$ls180.v:3314$929_Y
+    connect \B $not$ls180.v:3299$896_Y
+    connect \Y $and$ls180.v:3299$897_Y
   end
-  attribute \src "ls180.v:3314.41-3314.160"
-  cell $and $and$ls180.v:3314$931
+  attribute \src "ls180.v:3299.41-3299.160"
+  cell $and $and$ls180.v:3299$899
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3314$929_Y
-    connect \B $eq$ls180.v:3314$930_Y
-    connect \Y $and$ls180.v:3314$931_Y
+    connect \A $and$ls180.v:3299$897_Y
+    connect \B $eq$ls180.v:3299$898_Y
+    connect \Y $and$ls180.v:3299$899_Y
   end
-  attribute \src "ls180.v:3316.44-3316.105"
-  cell $and $and$ls180.v:3316$932
+  attribute \src "ls180.v:3301.44-3301.105"
+  cell $and $and$ls180.v:3301$900
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251748,43 +251264,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3316$932_Y
+    connect \Y $and$ls180.v:3301$900_Y
   end
-  attribute \src "ls180.v:3316.43-3316.159"
-  cell $and $and$ls180.v:3316$934
+  attribute \src "ls180.v:3301.43-3301.159"
+  cell $and $and$ls180.v:3301$902
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3316$932_Y
-    connect \B $eq$ls180.v:3316$933_Y
-    connect \Y $and$ls180.v:3316$934_Y
+    connect \A $and$ls180.v:3301$900_Y
+    connect \B $eq$ls180.v:3301$901_Y
+    connect \Y $and$ls180.v:3301$902_Y
   end
-  attribute \src "ls180.v:3317.44-3317.108"
-  cell $and $and$ls180.v:3317$936
+  attribute \src "ls180.v:3302.44-3302.108"
+  cell $and $and$ls180.v:3302$904
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3317$935_Y
-    connect \Y $and$ls180.v:3317$936_Y
+    connect \B $not$ls180.v:3302$903_Y
+    connect \Y $and$ls180.v:3302$904_Y
   end
-  attribute \src "ls180.v:3317.43-3317.162"
-  cell $and $and$ls180.v:3317$938
+  attribute \src "ls180.v:3302.43-3302.162"
+  cell $and $and$ls180.v:3302$906
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3317$936_Y
-    connect \B $eq$ls180.v:3317$937_Y
-    connect \Y $and$ls180.v:3317$938_Y
+    connect \A $and$ls180.v:3302$904_Y
+    connect \B $eq$ls180.v:3302$905_Y
+    connect \Y $and$ls180.v:3302$906_Y
   end
-  attribute \src "ls180.v:3319.44-3319.105"
-  cell $and $and$ls180.v:3319$939
+  attribute \src "ls180.v:3304.44-3304.105"
+  cell $and $and$ls180.v:3304$907
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251792,43 +251308,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3319$939_Y
+    connect \Y $and$ls180.v:3304$907_Y
   end
-  attribute \src "ls180.v:3319.43-3319.159"
-  cell $and $and$ls180.v:3319$941
+  attribute \src "ls180.v:3304.43-3304.159"
+  cell $and $and$ls180.v:3304$909
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3319$939_Y
-    connect \B $eq$ls180.v:3319$940_Y
-    connect \Y $and$ls180.v:3319$941_Y
+    connect \A $and$ls180.v:3304$907_Y
+    connect \B $eq$ls180.v:3304$908_Y
+    connect \Y $and$ls180.v:3304$909_Y
   end
-  attribute \src "ls180.v:3320.44-3320.108"
-  cell $and $and$ls180.v:3320$943
+  attribute \src "ls180.v:3305.44-3305.108"
+  cell $and $and$ls180.v:3305$911
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3320$942_Y
-    connect \Y $and$ls180.v:3320$943_Y
+    connect \B $not$ls180.v:3305$910_Y
+    connect \Y $and$ls180.v:3305$911_Y
   end
-  attribute \src "ls180.v:3320.43-3320.162"
-  cell $and $and$ls180.v:3320$945
+  attribute \src "ls180.v:3305.43-3305.162"
+  cell $and $and$ls180.v:3305$913
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3320$943_Y
-    connect \B $eq$ls180.v:3320$944_Y
-    connect \Y $and$ls180.v:3320$945_Y
+    connect \A $and$ls180.v:3305$911_Y
+    connect \B $eq$ls180.v:3305$912_Y
+    connect \Y $and$ls180.v:3305$913_Y
   end
-  attribute \src "ls180.v:3322.44-3322.105"
-  cell $and $and$ls180.v:3322$946
+  attribute \src "ls180.v:3307.44-3307.105"
+  cell $and $and$ls180.v:3307$914
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251836,43 +251352,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3322$946_Y
+    connect \Y $and$ls180.v:3307$914_Y
   end
-  attribute \src "ls180.v:3322.43-3322.159"
-  cell $and $and$ls180.v:3322$948
+  attribute \src "ls180.v:3307.43-3307.159"
+  cell $and $and$ls180.v:3307$916
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3322$946_Y
-    connect \B $eq$ls180.v:3322$947_Y
-    connect \Y $and$ls180.v:3322$948_Y
+    connect \A $and$ls180.v:3307$914_Y
+    connect \B $eq$ls180.v:3307$915_Y
+    connect \Y $and$ls180.v:3307$916_Y
   end
-  attribute \src "ls180.v:3323.44-3323.108"
-  cell $and $and$ls180.v:3323$950
+  attribute \src "ls180.v:3308.44-3308.108"
+  cell $and $and$ls180.v:3308$918
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3323$949_Y
-    connect \Y $and$ls180.v:3323$950_Y
+    connect \B $not$ls180.v:3308$917_Y
+    connect \Y $and$ls180.v:3308$918_Y
   end
-  attribute \src "ls180.v:3323.43-3323.162"
-  cell $and $and$ls180.v:3323$952
+  attribute \src "ls180.v:3308.43-3308.162"
+  cell $and $and$ls180.v:3308$920
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3323$950_Y
-    connect \B $eq$ls180.v:3323$951_Y
-    connect \Y $and$ls180.v:3323$952_Y
+    connect \A $and$ls180.v:3308$918_Y
+    connect \B $eq$ls180.v:3308$919_Y
+    connect \Y $and$ls180.v:3308$920_Y
   end
-  attribute \src "ls180.v:3325.44-3325.105"
-  cell $and $and$ls180.v:3325$953
+  attribute \src "ls180.v:3310.44-3310.105"
+  cell $and $and$ls180.v:3310$921
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251880,43 +251396,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3325$953_Y
+    connect \Y $and$ls180.v:3310$921_Y
   end
-  attribute \src "ls180.v:3325.43-3325.159"
-  cell $and $and$ls180.v:3325$955
+  attribute \src "ls180.v:3310.43-3310.159"
+  cell $and $and$ls180.v:3310$923
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3325$953_Y
-    connect \B $eq$ls180.v:3325$954_Y
-    connect \Y $and$ls180.v:3325$955_Y
+    connect \A $and$ls180.v:3310$921_Y
+    connect \B $eq$ls180.v:3310$922_Y
+    connect \Y $and$ls180.v:3310$923_Y
   end
-  attribute \src "ls180.v:3326.44-3326.108"
-  cell $and $and$ls180.v:3326$957
+  attribute \src "ls180.v:3311.44-3311.108"
+  cell $and $and$ls180.v:3311$925
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3326$956_Y
-    connect \Y $and$ls180.v:3326$957_Y
+    connect \B $not$ls180.v:3311$924_Y
+    connect \Y $and$ls180.v:3311$925_Y
   end
-  attribute \src "ls180.v:3326.43-3326.162"
-  cell $and $and$ls180.v:3326$959
+  attribute \src "ls180.v:3311.43-3311.162"
+  cell $and $and$ls180.v:3311$927
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3326$957_Y
-    connect \B $eq$ls180.v:3326$958_Y
-    connect \Y $and$ls180.v:3326$959_Y
+    connect \A $and$ls180.v:3311$925_Y
+    connect \B $eq$ls180.v:3311$926_Y
+    connect \Y $and$ls180.v:3311$927_Y
   end
-  attribute \src "ls180.v:3328.40-3328.101"
-  cell $and $and$ls180.v:3328$960
+  attribute \src "ls180.v:3313.40-3313.101"
+  cell $and $and$ls180.v:3313$928
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251924,43 +251440,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3328$960_Y
+    connect \Y $and$ls180.v:3313$928_Y
   end
-  attribute \src "ls180.v:3328.39-3328.155"
-  cell $and $and$ls180.v:3328$962
+  attribute \src "ls180.v:3313.39-3313.155"
+  cell $and $and$ls180.v:3313$930
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3328$960_Y
-    connect \B $eq$ls180.v:3328$961_Y
-    connect \Y $and$ls180.v:3328$962_Y
+    connect \A $and$ls180.v:3313$928_Y
+    connect \B $eq$ls180.v:3313$929_Y
+    connect \Y $and$ls180.v:3313$930_Y
   end
-  attribute \src "ls180.v:3329.40-3329.104"
-  cell $and $and$ls180.v:3329$964
+  attribute \src "ls180.v:3314.40-3314.104"
+  cell $and $and$ls180.v:3314$932
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3329$963_Y
-    connect \Y $and$ls180.v:3329$964_Y
+    connect \B $not$ls180.v:3314$931_Y
+    connect \Y $and$ls180.v:3314$932_Y
   end
-  attribute \src "ls180.v:3329.39-3329.158"
-  cell $and $and$ls180.v:3329$966
+  attribute \src "ls180.v:3314.39-3314.158"
+  cell $and $and$ls180.v:3314$934
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3329$964_Y
-    connect \B $eq$ls180.v:3329$965_Y
-    connect \Y $and$ls180.v:3329$966_Y
+    connect \A $and$ls180.v:3314$932_Y
+    connect \B $eq$ls180.v:3314$933_Y
+    connect \Y $and$ls180.v:3314$934_Y
   end
-  attribute \src "ls180.v:3331.50-3331.111"
-  cell $and $and$ls180.v:3331$967
+  attribute \src "ls180.v:3316.50-3316.111"
+  cell $and $and$ls180.v:3316$935
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -251968,43 +251484,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3331$967_Y
+    connect \Y $and$ls180.v:3316$935_Y
   end
-  attribute \src "ls180.v:3331.49-3331.165"
-  cell $and $and$ls180.v:3331$969
+  attribute \src "ls180.v:3316.49-3316.165"
+  cell $and $and$ls180.v:3316$937
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3331$967_Y
-    connect \B $eq$ls180.v:3331$968_Y
-    connect \Y $and$ls180.v:3331$969_Y
+    connect \A $and$ls180.v:3316$935_Y
+    connect \B $eq$ls180.v:3316$936_Y
+    connect \Y $and$ls180.v:3316$937_Y
   end
-  attribute \src "ls180.v:3332.50-3332.114"
-  cell $and $and$ls180.v:3332$971
+  attribute \src "ls180.v:3317.50-3317.114"
+  cell $and $and$ls180.v:3317$939
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3332$970_Y
-    connect \Y $and$ls180.v:3332$971_Y
+    connect \B $not$ls180.v:3317$938_Y
+    connect \Y $and$ls180.v:3317$939_Y
   end
-  attribute \src "ls180.v:3332.49-3332.168"
-  cell $and $and$ls180.v:3332$973
+  attribute \src "ls180.v:3317.49-3317.168"
+  cell $and $and$ls180.v:3317$941
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3332$971_Y
-    connect \B $eq$ls180.v:3332$972_Y
-    connect \Y $and$ls180.v:3332$973_Y
+    connect \A $and$ls180.v:3317$939_Y
+    connect \B $eq$ls180.v:3317$940_Y
+    connect \Y $and$ls180.v:3317$941_Y
   end
-  attribute \src "ls180.v:3334.43-3334.104"
-  cell $and $and$ls180.v:3334$974
+  attribute \src "ls180.v:3319.43-3319.104"
+  cell $and $and$ls180.v:3319$942
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252012,43 +251528,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3334$974_Y
+    connect \Y $and$ls180.v:3319$942_Y
   end
-  attribute \src "ls180.v:3334.42-3334.159"
-  cell $and $and$ls180.v:3334$976
+  attribute \src "ls180.v:3319.42-3319.159"
+  cell $and $and$ls180.v:3319$944
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3334$974_Y
-    connect \B $eq$ls180.v:3334$975_Y
-    connect \Y $and$ls180.v:3334$976_Y
+    connect \A $and$ls180.v:3319$942_Y
+    connect \B $eq$ls180.v:3319$943_Y
+    connect \Y $and$ls180.v:3319$944_Y
   end
-  attribute \src "ls180.v:3335.43-3335.107"
-  cell $and $and$ls180.v:3335$978
+  attribute \src "ls180.v:3320.43-3320.107"
+  cell $and $and$ls180.v:3320$946
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3335$977_Y
-    connect \Y $and$ls180.v:3335$978_Y
+    connect \B $not$ls180.v:3320$945_Y
+    connect \Y $and$ls180.v:3320$946_Y
   end
-  attribute \src "ls180.v:3335.42-3335.162"
-  cell $and $and$ls180.v:3335$980
+  attribute \src "ls180.v:3320.42-3320.162"
+  cell $and $and$ls180.v:3320$948
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3335$978_Y
-    connect \B $eq$ls180.v:3335$979_Y
-    connect \Y $and$ls180.v:3335$980_Y
+    connect \A $and$ls180.v:3320$946_Y
+    connect \B $eq$ls180.v:3320$947_Y
+    connect \Y $and$ls180.v:3320$948_Y
   end
-  attribute \src "ls180.v:3337.43-3337.104"
-  cell $and $and$ls180.v:3337$981
+  attribute \src "ls180.v:3322.43-3322.104"
+  cell $and $and$ls180.v:3322$949
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252056,43 +251572,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3337$981_Y
+    connect \Y $and$ls180.v:3322$949_Y
   end
-  attribute \src "ls180.v:3337.42-3337.159"
-  cell $and $and$ls180.v:3337$983
+  attribute \src "ls180.v:3322.42-3322.159"
+  cell $and $and$ls180.v:3322$951
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3337$981_Y
-    connect \B $eq$ls180.v:3337$982_Y
-    connect \Y $and$ls180.v:3337$983_Y
+    connect \A $and$ls180.v:3322$949_Y
+    connect \B $eq$ls180.v:3322$950_Y
+    connect \Y $and$ls180.v:3322$951_Y
   end
-  attribute \src "ls180.v:3338.43-3338.107"
-  cell $and $and$ls180.v:3338$985
+  attribute \src "ls180.v:3323.43-3323.107"
+  cell $and $and$ls180.v:3323$953
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3338$984_Y
-    connect \Y $and$ls180.v:3338$985_Y
+    connect \B $not$ls180.v:3323$952_Y
+    connect \Y $and$ls180.v:3323$953_Y
   end
-  attribute \src "ls180.v:3338.42-3338.162"
-  cell $and $and$ls180.v:3338$987
+  attribute \src "ls180.v:3323.42-3323.162"
+  cell $and $and$ls180.v:3323$955
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3338$985_Y
-    connect \B $eq$ls180.v:3338$986_Y
-    connect \Y $and$ls180.v:3338$987_Y
+    connect \A $and$ls180.v:3323$953_Y
+    connect \B $eq$ls180.v:3323$954_Y
+    connect \Y $and$ls180.v:3323$955_Y
   end
-  attribute \src "ls180.v:3340.43-3340.104"
-  cell $and $and$ls180.v:3340$988
+  attribute \src "ls180.v:3325.43-3325.104"
+  cell $and $and$ls180.v:3325$956
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252100,43 +251616,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3340$988_Y
+    connect \Y $and$ls180.v:3325$956_Y
   end
-  attribute \src "ls180.v:3340.42-3340.159"
-  cell $and $and$ls180.v:3340$990
+  attribute \src "ls180.v:3325.42-3325.159"
+  cell $and $and$ls180.v:3325$958
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3340$988_Y
-    connect \B $eq$ls180.v:3340$989_Y
-    connect \Y $and$ls180.v:3340$990_Y
+    connect \A $and$ls180.v:3325$956_Y
+    connect \B $eq$ls180.v:3325$957_Y
+    connect \Y $and$ls180.v:3325$958_Y
   end
-  attribute \src "ls180.v:3341.43-3341.107"
-  cell $and $and$ls180.v:3341$992
+  attribute \src "ls180.v:3326.43-3326.107"
+  cell $and $and$ls180.v:3326$960
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3341$991_Y
-    connect \Y $and$ls180.v:3341$992_Y
+    connect \B $not$ls180.v:3326$959_Y
+    connect \Y $and$ls180.v:3326$960_Y
   end
-  attribute \src "ls180.v:3341.42-3341.162"
-  cell $and $and$ls180.v:3341$994
+  attribute \src "ls180.v:3326.42-3326.162"
+  cell $and $and$ls180.v:3326$962
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3341$992_Y
-    connect \B $eq$ls180.v:3341$993_Y
-    connect \Y $and$ls180.v:3341$994_Y
+    connect \A $and$ls180.v:3326$960_Y
+    connect \B $eq$ls180.v:3326$961_Y
+    connect \Y $and$ls180.v:3326$962_Y
   end
-  attribute \src "ls180.v:3343.43-3343.104"
-  cell $and $and$ls180.v:3343$995
+  attribute \src "ls180.v:3328.43-3328.104"
+  cell $and $and$ls180.v:3328$963
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252144,43 +251660,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3343$995_Y
+    connect \Y $and$ls180.v:3328$963_Y
   end
-  attribute \src "ls180.v:3343.42-3343.159"
-  cell $and $and$ls180.v:3343$997
+  attribute \src "ls180.v:3328.42-3328.159"
+  cell $and $and$ls180.v:3328$965
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3343$995_Y
-    connect \B $eq$ls180.v:3343$996_Y
-    connect \Y $and$ls180.v:3343$997_Y
+    connect \A $and$ls180.v:3328$963_Y
+    connect \B $eq$ls180.v:3328$964_Y
+    connect \Y $and$ls180.v:3328$965_Y
   end
-  attribute \src "ls180.v:3344.42-3344.162"
-  cell $and $and$ls180.v:3344$1001
+  attribute \src "ls180.v:3329.43-3329.107"
+  cell $and $and$ls180.v:3329$967
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3344$999_Y
-    connect \B $eq$ls180.v:3344$1000_Y
-    connect \Y $and$ls180.v:3344$1001_Y
+    connect \A \libresocsim_csrbank5_sel
+    connect \B $not$ls180.v:3329$966_Y
+    connect \Y $and$ls180.v:3329$967_Y
   end
-  attribute \src "ls180.v:3344.43-3344.107"
-  cell $and $and$ls180.v:3344$999
+  attribute \src "ls180.v:3329.42-3329.162"
+  cell $and $and$ls180.v:3329$969
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3344$998_Y
-    connect \Y $and$ls180.v:3344$999_Y
+    connect \A $and$ls180.v:3329$967_Y
+    connect \B $eq$ls180.v:3329$968_Y
+    connect \Y $and$ls180.v:3329$969_Y
   end
-  attribute \src "ls180.v:3346.47-3346.108"
-  cell $and $and$ls180.v:3346$1002
+  attribute \src "ls180.v:3331.47-3331.108"
+  cell $and $and$ls180.v:3331$970
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252188,43 +251704,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3346$1002_Y
+    connect \Y $and$ls180.v:3331$970_Y
   end
-  attribute \src "ls180.v:3346.46-3346.163"
-  cell $and $and$ls180.v:3346$1004
+  attribute \src "ls180.v:3331.46-3331.163"
+  cell $and $and$ls180.v:3331$972
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3346$1002_Y
-    connect \B $eq$ls180.v:3346$1003_Y
-    connect \Y $and$ls180.v:3346$1004_Y
+    connect \A $and$ls180.v:3331$970_Y
+    connect \B $eq$ls180.v:3331$971_Y
+    connect \Y $and$ls180.v:3331$972_Y
   end
-  attribute \src "ls180.v:3347.47-3347.111"
-  cell $and $and$ls180.v:3347$1006
+  attribute \src "ls180.v:3332.47-3332.111"
+  cell $and $and$ls180.v:3332$974
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3347$1005_Y
-    connect \Y $and$ls180.v:3347$1006_Y
+    connect \B $not$ls180.v:3332$973_Y
+    connect \Y $and$ls180.v:3332$974_Y
   end
-  attribute \src "ls180.v:3347.46-3347.166"
-  cell $and $and$ls180.v:3347$1008
+  attribute \src "ls180.v:3332.46-3332.166"
+  cell $and $and$ls180.v:3332$976
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3347$1006_Y
-    connect \B $eq$ls180.v:3347$1007_Y
-    connect \Y $and$ls180.v:3347$1008_Y
+    connect \A $and$ls180.v:3332$974_Y
+    connect \B $eq$ls180.v:3332$975_Y
+    connect \Y $and$ls180.v:3332$976_Y
   end
-  attribute \src "ls180.v:3349.48-3349.109"
-  cell $and $and$ls180.v:3349$1009
+  attribute \src "ls180.v:3334.48-3334.109"
+  cell $and $and$ls180.v:3334$977
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252232,43 +251748,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3349$1009_Y
+    connect \Y $and$ls180.v:3334$977_Y
   end
-  attribute \src "ls180.v:3349.47-3349.164"
-  cell $and $and$ls180.v:3349$1011
+  attribute \src "ls180.v:3334.47-3334.164"
+  cell $and $and$ls180.v:3334$979
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3349$1009_Y
-    connect \B $eq$ls180.v:3349$1010_Y
-    connect \Y $and$ls180.v:3349$1011_Y
+    connect \A $and$ls180.v:3334$977_Y
+    connect \B $eq$ls180.v:3334$978_Y
+    connect \Y $and$ls180.v:3334$979_Y
   end
-  attribute \src "ls180.v:3350.48-3350.112"
-  cell $and $and$ls180.v:3350$1013
+  attribute \src "ls180.v:3335.48-3335.112"
+  cell $and $and$ls180.v:3335$981
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3350$1012_Y
-    connect \Y $and$ls180.v:3350$1013_Y
+    connect \B $not$ls180.v:3335$980_Y
+    connect \Y $and$ls180.v:3335$981_Y
   end
-  attribute \src "ls180.v:3350.47-3350.167"
-  cell $and $and$ls180.v:3350$1015
+  attribute \src "ls180.v:3335.47-3335.167"
+  cell $and $and$ls180.v:3335$983
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3350$1013_Y
-    connect \B $eq$ls180.v:3350$1014_Y
-    connect \Y $and$ls180.v:3350$1015_Y
+    connect \A $and$ls180.v:3335$981_Y
+    connect \B $eq$ls180.v:3335$982_Y
+    connect \Y $and$ls180.v:3335$983_Y
   end
-  attribute \src "ls180.v:3352.47-3352.108"
-  cell $and $and$ls180.v:3352$1016
+  attribute \src "ls180.v:3337.47-3337.108"
+  cell $and $and$ls180.v:3337$984
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252276,43 +251792,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
     connect \B \libresocsim_interface5_bank_bus_we
-    connect \Y $and$ls180.v:3352$1016_Y
+    connect \Y $and$ls180.v:3337$984_Y
   end
-  attribute \src "ls180.v:3352.46-3352.163"
-  cell $and $and$ls180.v:3352$1018
+  attribute \src "ls180.v:3337.46-3337.163"
+  cell $and $and$ls180.v:3337$986
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3352$1016_Y
-    connect \B $eq$ls180.v:3352$1017_Y
-    connect \Y $and$ls180.v:3352$1018_Y
+    connect \A $and$ls180.v:3337$984_Y
+    connect \B $eq$ls180.v:3337$985_Y
+    connect \Y $and$ls180.v:3337$986_Y
   end
-  attribute \src "ls180.v:3353.47-3353.111"
-  cell $and $and$ls180.v:3353$1020
+  attribute \src "ls180.v:3338.47-3338.111"
+  cell $and $and$ls180.v:3338$988
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank5_sel
-    connect \B $not$ls180.v:3353$1019_Y
-    connect \Y $and$ls180.v:3353$1020_Y
+    connect \B $not$ls180.v:3338$987_Y
+    connect \Y $and$ls180.v:3338$988_Y
   end
-  attribute \src "ls180.v:3353.46-3353.166"
-  cell $and $and$ls180.v:3353$1022
+  attribute \src "ls180.v:3338.46-3338.166"
+  cell $and $and$ls180.v:3338$990
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3353$1020_Y
-    connect \B $eq$ls180.v:3353$1021_Y
-    connect \Y $and$ls180.v:3353$1022_Y
+    connect \A $and$ls180.v:3338$988_Y
+    connect \B $eq$ls180.v:3338$989_Y
+    connect \Y $and$ls180.v:3338$990_Y
   end
-  attribute \src "ls180.v:3372.20-3372.81"
-  cell $and $and$ls180.v:3372$1024
+  attribute \src "ls180.v:3357.20-3357.81"
+  cell $and $and$ls180.v:3357$992
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252320,87 +251836,87 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3372$1024_Y
+    connect \Y $and$ls180.v:3357$992_Y
   end
-  attribute \src "ls180.v:3372.19-3372.135"
-  cell $and $and$ls180.v:3372$1026
+  attribute \src "ls180.v:3357.19-3357.135"
+  cell $and $and$ls180.v:3357$994
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3372$1024_Y
-    connect \B $eq$ls180.v:3372$1025_Y
-    connect \Y $and$ls180.v:3372$1026_Y
+    connect \A $and$ls180.v:3357$992_Y
+    connect \B $eq$ls180.v:3357$993_Y
+    connect \Y $and$ls180.v:3357$994_Y
   end
-  attribute \src "ls180.v:3373.20-3373.84"
-  cell $and $and$ls180.v:3373$1028
+  attribute \src "ls180.v:3358.20-3358.84"
+  cell $and $and$ls180.v:3358$996
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3373$1027_Y
-    connect \Y $and$ls180.v:3373$1028_Y
+    connect \B $not$ls180.v:3358$995_Y
+    connect \Y $and$ls180.v:3358$996_Y
   end
-  attribute \src "ls180.v:3373.19-3373.138"
-  cell $and $and$ls180.v:3373$1030
+  attribute \src "ls180.v:3358.19-3358.138"
+  cell $and $and$ls180.v:3358$998
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3373$1028_Y
-    connect \B $eq$ls180.v:3373$1029_Y
-    connect \Y $and$ls180.v:3373$1030_Y
+    connect \A $and$ls180.v:3358$996_Y
+    connect \B $eq$ls180.v:3358$997_Y
+    connect \Y $and$ls180.v:3358$998_Y
   end
-  attribute \src "ls180.v:3375.43-3375.104"
-  cell $and $and$ls180.v:3375$1031
+  attribute \src "ls180.v:3360.42-3360.158"
+  cell $and $and$ls180.v:3360$1001
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_csrbank6_sel
-    connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3375$1031_Y
+    connect \A $and$ls180.v:3360$999_Y
+    connect \B $eq$ls180.v:3360$1000_Y
+    connect \Y $and$ls180.v:3360$1001_Y
   end
-  attribute \src "ls180.v:3375.42-3375.158"
-  cell $and $and$ls180.v:3375$1033
+  attribute \src "ls180.v:3360.43-3360.104"
+  cell $and $and$ls180.v:3360$999
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3375$1031_Y
-    connect \B $eq$ls180.v:3375$1032_Y
-    connect \Y $and$ls180.v:3375$1033_Y
+    connect \A \libresocsim_csrbank6_sel
+    connect \B \libresocsim_interface6_bank_bus_we
+    connect \Y $and$ls180.v:3360$999_Y
   end
-  attribute \src "ls180.v:3376.43-3376.107"
-  cell $and $and$ls180.v:3376$1035
+  attribute \src "ls180.v:3361.43-3361.107"
+  cell $and $and$ls180.v:3361$1003
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3376$1034_Y
-    connect \Y $and$ls180.v:3376$1035_Y
+    connect \B $not$ls180.v:3361$1002_Y
+    connect \Y $and$ls180.v:3361$1003_Y
   end
-  attribute \src "ls180.v:3376.42-3376.161"
-  cell $and $and$ls180.v:3376$1037
+  attribute \src "ls180.v:3361.42-3361.161"
+  cell $and $and$ls180.v:3361$1005
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3376$1035_Y
-    connect \B $eq$ls180.v:3376$1036_Y
-    connect \Y $and$ls180.v:3376$1037_Y
+    connect \A $and$ls180.v:3361$1003_Y
+    connect \B $eq$ls180.v:3361$1004_Y
+    connect \Y $and$ls180.v:3361$1005_Y
   end
-  attribute \src "ls180.v:3378.44-3378.105"
-  cell $and $and$ls180.v:3378$1038
+  attribute \src "ls180.v:3363.44-3363.105"
+  cell $and $and$ls180.v:3363$1006
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252408,43 +251924,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3378$1038_Y
+    connect \Y $and$ls180.v:3363$1006_Y
   end
-  attribute \src "ls180.v:3378.43-3378.159"
-  cell $and $and$ls180.v:3378$1040
+  attribute \src "ls180.v:3363.43-3363.159"
+  cell $and $and$ls180.v:3363$1008
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3378$1038_Y
-    connect \B $eq$ls180.v:3378$1039_Y
-    connect \Y $and$ls180.v:3378$1040_Y
+    connect \A $and$ls180.v:3363$1006_Y
+    connect \B $eq$ls180.v:3363$1007_Y
+    connect \Y $and$ls180.v:3363$1008_Y
   end
-  attribute \src "ls180.v:3379.44-3379.108"
-  cell $and $and$ls180.v:3379$1042
+  attribute \src "ls180.v:3364.44-3364.108"
+  cell $and $and$ls180.v:3364$1010
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3379$1041_Y
-    connect \Y $and$ls180.v:3379$1042_Y
+    connect \B $not$ls180.v:3364$1009_Y
+    connect \Y $and$ls180.v:3364$1010_Y
   end
-  attribute \src "ls180.v:3379.43-3379.162"
-  cell $and $and$ls180.v:3379$1044
+  attribute \src "ls180.v:3364.43-3364.162"
+  cell $and $and$ls180.v:3364$1012
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3379$1042_Y
-    connect \B $eq$ls180.v:3379$1043_Y
-    connect \Y $and$ls180.v:3379$1044_Y
+    connect \A $and$ls180.v:3364$1010_Y
+    connect \B $eq$ls180.v:3364$1011_Y
+    connect \Y $and$ls180.v:3364$1012_Y
   end
-  attribute \src "ls180.v:3381.35-3381.96"
-  cell $and $and$ls180.v:3381$1045
+  attribute \src "ls180.v:3366.35-3366.96"
+  cell $and $and$ls180.v:3366$1013
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252452,43 +251968,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3381$1045_Y
+    connect \Y $and$ls180.v:3366$1013_Y
   end
-  attribute \src "ls180.v:3381.34-3381.150"
-  cell $and $and$ls180.v:3381$1047
+  attribute \src "ls180.v:3366.34-3366.150"
+  cell $and $and$ls180.v:3366$1015
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3381$1045_Y
-    connect \B $eq$ls180.v:3381$1046_Y
-    connect \Y $and$ls180.v:3381$1047_Y
+    connect \A $and$ls180.v:3366$1013_Y
+    connect \B $eq$ls180.v:3366$1014_Y
+    connect \Y $and$ls180.v:3366$1015_Y
   end
-  attribute \src "ls180.v:3382.35-3382.99"
-  cell $and $and$ls180.v:3382$1049
+  attribute \src "ls180.v:3367.35-3367.99"
+  cell $and $and$ls180.v:3367$1017
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3382$1048_Y
-    connect \Y $and$ls180.v:3382$1049_Y
+    connect \B $not$ls180.v:3367$1016_Y
+    connect \Y $and$ls180.v:3367$1017_Y
   end
-  attribute \src "ls180.v:3382.34-3382.153"
-  cell $and $and$ls180.v:3382$1051
+  attribute \src "ls180.v:3367.34-3367.153"
+  cell $and $and$ls180.v:3367$1019
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3382$1049_Y
-    connect \B $eq$ls180.v:3382$1050_Y
-    connect \Y $and$ls180.v:3382$1051_Y
+    connect \A $and$ls180.v:3367$1017_Y
+    connect \B $eq$ls180.v:3367$1018_Y
+    connect \Y $and$ls180.v:3367$1019_Y
   end
-  attribute \src "ls180.v:3384.36-3384.97"
-  cell $and $and$ls180.v:3384$1052
+  attribute \src "ls180.v:3369.36-3369.97"
+  cell $and $and$ls180.v:3369$1020
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252496,43 +252012,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3384$1052_Y
+    connect \Y $and$ls180.v:3369$1020_Y
   end
-  attribute \src "ls180.v:3384.35-3384.151"
-  cell $and $and$ls180.v:3384$1054
+  attribute \src "ls180.v:3369.35-3369.151"
+  cell $and $and$ls180.v:3369$1022
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3384$1052_Y
-    connect \B $eq$ls180.v:3384$1053_Y
-    connect \Y $and$ls180.v:3384$1054_Y
+    connect \A $and$ls180.v:3369$1020_Y
+    connect \B $eq$ls180.v:3369$1021_Y
+    connect \Y $and$ls180.v:3369$1022_Y
   end
-  attribute \src "ls180.v:3385.36-3385.100"
-  cell $and $and$ls180.v:3385$1056
+  attribute \src "ls180.v:3370.36-3370.100"
+  cell $and $and$ls180.v:3370$1024
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3385$1055_Y
-    connect \Y $and$ls180.v:3385$1056_Y
+    connect \B $not$ls180.v:3370$1023_Y
+    connect \Y $and$ls180.v:3370$1024_Y
   end
-  attribute \src "ls180.v:3385.35-3385.154"
-  cell $and $and$ls180.v:3385$1058
+  attribute \src "ls180.v:3370.35-3370.154"
+  cell $and $and$ls180.v:3370$1026
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3385$1056_Y
-    connect \B $eq$ls180.v:3385$1057_Y
-    connect \Y $and$ls180.v:3385$1058_Y
+    connect \A $and$ls180.v:3370$1024_Y
+    connect \B $eq$ls180.v:3370$1025_Y
+    connect \Y $and$ls180.v:3370$1026_Y
   end
-  attribute \src "ls180.v:3387.47-3387.108"
-  cell $and $and$ls180.v:3387$1059
+  attribute \src "ls180.v:3372.47-3372.108"
+  cell $and $and$ls180.v:3372$1027
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252540,43 +252056,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3387$1059_Y
+    connect \Y $and$ls180.v:3372$1027_Y
   end
-  attribute \src "ls180.v:3387.46-3387.162"
-  cell $and $and$ls180.v:3387$1061
+  attribute \src "ls180.v:3372.46-3372.162"
+  cell $and $and$ls180.v:3372$1029
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3387$1059_Y
-    connect \B $eq$ls180.v:3387$1060_Y
-    connect \Y $and$ls180.v:3387$1061_Y
+    connect \A $and$ls180.v:3372$1027_Y
+    connect \B $eq$ls180.v:3372$1028_Y
+    connect \Y $and$ls180.v:3372$1029_Y
   end
-  attribute \src "ls180.v:3388.47-3388.111"
-  cell $and $and$ls180.v:3388$1063
+  attribute \src "ls180.v:3373.47-3373.111"
+  cell $and $and$ls180.v:3373$1031
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3388$1062_Y
-    connect \Y $and$ls180.v:3388$1063_Y
+    connect \B $not$ls180.v:3373$1030_Y
+    connect \Y $and$ls180.v:3373$1031_Y
   end
-  attribute \src "ls180.v:3388.46-3388.165"
-  cell $and $and$ls180.v:3388$1065
+  attribute \src "ls180.v:3373.46-3373.165"
+  cell $and $and$ls180.v:3373$1033
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3388$1063_Y
-    connect \B $eq$ls180.v:3388$1064_Y
-    connect \Y $and$ls180.v:3388$1065_Y
+    connect \A $and$ls180.v:3373$1031_Y
+    connect \B $eq$ls180.v:3373$1032_Y
+    connect \Y $and$ls180.v:3373$1033_Y
   end
-  attribute \src "ls180.v:3390.44-3390.105"
-  cell $and $and$ls180.v:3390$1066
+  attribute \src "ls180.v:3375.44-3375.105"
+  cell $and $and$ls180.v:3375$1034
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252584,43 +252100,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3390$1066_Y
+    connect \Y $and$ls180.v:3375$1034_Y
   end
-  attribute \src "ls180.v:3390.43-3390.159"
-  cell $and $and$ls180.v:3390$1068
+  attribute \src "ls180.v:3375.43-3375.159"
+  cell $and $and$ls180.v:3375$1036
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3390$1066_Y
-    connect \B $eq$ls180.v:3390$1067_Y
-    connect \Y $and$ls180.v:3390$1068_Y
+    connect \A $and$ls180.v:3375$1034_Y
+    connect \B $eq$ls180.v:3375$1035_Y
+    connect \Y $and$ls180.v:3375$1036_Y
   end
-  attribute \src "ls180.v:3391.44-3391.108"
-  cell $and $and$ls180.v:3391$1070
+  attribute \src "ls180.v:3376.44-3376.108"
+  cell $and $and$ls180.v:3376$1038
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3391$1069_Y
-    connect \Y $and$ls180.v:3391$1070_Y
+    connect \B $not$ls180.v:3376$1037_Y
+    connect \Y $and$ls180.v:3376$1038_Y
   end
-  attribute \src "ls180.v:3391.43-3391.162"
-  cell $and $and$ls180.v:3391$1072
+  attribute \src "ls180.v:3376.43-3376.162"
+  cell $and $and$ls180.v:3376$1040
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3391$1070_Y
-    connect \B $eq$ls180.v:3391$1071_Y
-    connect \Y $and$ls180.v:3391$1072_Y
+    connect \A $and$ls180.v:3376$1038_Y
+    connect \B $eq$ls180.v:3376$1039_Y
+    connect \Y $and$ls180.v:3376$1040_Y
   end
-  attribute \src "ls180.v:3393.43-3393.104"
-  cell $and $and$ls180.v:3393$1073
+  attribute \src "ls180.v:3378.43-3378.104"
+  cell $and $and$ls180.v:3378$1041
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252628,43 +252144,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
     connect \B \libresocsim_interface6_bank_bus_we
-    connect \Y $and$ls180.v:3393$1073_Y
+    connect \Y $and$ls180.v:3378$1041_Y
   end
-  attribute \src "ls180.v:3393.42-3393.158"
-  cell $and $and$ls180.v:3393$1075
+  attribute \src "ls180.v:3378.42-3378.158"
+  cell $and $and$ls180.v:3378$1043
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3393$1073_Y
-    connect \B $eq$ls180.v:3393$1074_Y
-    connect \Y $and$ls180.v:3393$1075_Y
+    connect \A $and$ls180.v:3378$1041_Y
+    connect \B $eq$ls180.v:3378$1042_Y
+    connect \Y $and$ls180.v:3378$1043_Y
   end
-  attribute \src "ls180.v:3394.43-3394.107"
-  cell $and $and$ls180.v:3394$1077
+  attribute \src "ls180.v:3379.43-3379.107"
+  cell $and $and$ls180.v:3379$1045
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank6_sel
-    connect \B $not$ls180.v:3394$1076_Y
-    connect \Y $and$ls180.v:3394$1077_Y
+    connect \B $not$ls180.v:3379$1044_Y
+    connect \Y $and$ls180.v:3379$1045_Y
   end
-  attribute \src "ls180.v:3394.42-3394.161"
-  cell $and $and$ls180.v:3394$1079
+  attribute \src "ls180.v:3379.42-3379.161"
+  cell $and $and$ls180.v:3379$1047
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3394$1077_Y
-    connect \B $eq$ls180.v:3394$1078_Y
-    connect \Y $and$ls180.v:3394$1079_Y
+    connect \A $and$ls180.v:3379$1045_Y
+    connect \B $eq$ls180.v:3379$1046_Y
+    connect \Y $and$ls180.v:3379$1047_Y
   end
-  attribute \src "ls180.v:3406.49-3406.110"
-  cell $and $and$ls180.v:3406$1081
+  attribute \src "ls180.v:3391.49-3391.110"
+  cell $and $and$ls180.v:3391$1049
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252672,43 +252188,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
     connect \B \libresocsim_interface7_bank_bus_we
-    connect \Y $and$ls180.v:3406$1081_Y
+    connect \Y $and$ls180.v:3391$1049_Y
   end
-  attribute \src "ls180.v:3406.48-3406.164"
-  cell $and $and$ls180.v:3406$1083
+  attribute \src "ls180.v:3391.48-3391.164"
+  cell $and $and$ls180.v:3391$1051
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3406$1081_Y
-    connect \B $eq$ls180.v:3406$1082_Y
-    connect \Y $and$ls180.v:3406$1083_Y
+    connect \A $and$ls180.v:3391$1049_Y
+    connect \B $eq$ls180.v:3391$1050_Y
+    connect \Y $and$ls180.v:3391$1051_Y
   end
-  attribute \src "ls180.v:3407.49-3407.113"
-  cell $and $and$ls180.v:3407$1085
+  attribute \src "ls180.v:3392.49-3392.113"
+  cell $and $and$ls180.v:3392$1053
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
-    connect \B $not$ls180.v:3407$1084_Y
-    connect \Y $and$ls180.v:3407$1085_Y
+    connect \B $not$ls180.v:3392$1052_Y
+    connect \Y $and$ls180.v:3392$1053_Y
   end
-  attribute \src "ls180.v:3407.48-3407.167"
-  cell $and $and$ls180.v:3407$1087
+  attribute \src "ls180.v:3392.48-3392.167"
+  cell $and $and$ls180.v:3392$1055
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3407$1085_Y
-    connect \B $eq$ls180.v:3407$1086_Y
-    connect \Y $and$ls180.v:3407$1087_Y
+    connect \A $and$ls180.v:3392$1053_Y
+    connect \B $eq$ls180.v:3392$1054_Y
+    connect \Y $and$ls180.v:3392$1055_Y
   end
-  attribute \src "ls180.v:3409.49-3409.110"
-  cell $and $and$ls180.v:3409$1088
+  attribute \src "ls180.v:3394.49-3394.110"
+  cell $and $and$ls180.v:3394$1056
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252716,43 +252232,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
     connect \B \libresocsim_interface7_bank_bus_we
-    connect \Y $and$ls180.v:3409$1088_Y
+    connect \Y $and$ls180.v:3394$1056_Y
   end
-  attribute \src "ls180.v:3409.48-3409.164"
-  cell $and $and$ls180.v:3409$1090
+  attribute \src "ls180.v:3394.48-3394.164"
+  cell $and $and$ls180.v:3394$1058
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3409$1088_Y
-    connect \B $eq$ls180.v:3409$1089_Y
-    connect \Y $and$ls180.v:3409$1090_Y
+    connect \A $and$ls180.v:3394$1056_Y
+    connect \B $eq$ls180.v:3394$1057_Y
+    connect \Y $and$ls180.v:3394$1058_Y
   end
-  attribute \src "ls180.v:3410.49-3410.113"
-  cell $and $and$ls180.v:3410$1092
+  attribute \src "ls180.v:3395.49-3395.113"
+  cell $and $and$ls180.v:3395$1060
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
-    connect \B $not$ls180.v:3410$1091_Y
-    connect \Y $and$ls180.v:3410$1092_Y
+    connect \B $not$ls180.v:3395$1059_Y
+    connect \Y $and$ls180.v:3395$1060_Y
   end
-  attribute \src "ls180.v:3410.48-3410.167"
-  cell $and $and$ls180.v:3410$1094
+  attribute \src "ls180.v:3395.48-3395.167"
+  cell $and $and$ls180.v:3395$1062
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3410$1092_Y
-    connect \B $eq$ls180.v:3410$1093_Y
-    connect \Y $and$ls180.v:3410$1094_Y
+    connect \A $and$ls180.v:3395$1060_Y
+    connect \B $eq$ls180.v:3395$1061_Y
+    connect \Y $and$ls180.v:3395$1062_Y
   end
-  attribute \src "ls180.v:3412.49-3412.110"
-  cell $and $and$ls180.v:3412$1095
+  attribute \src "ls180.v:3397.49-3397.110"
+  cell $and $and$ls180.v:3397$1063
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252760,43 +252276,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
     connect \B \libresocsim_interface7_bank_bus_we
-    connect \Y $and$ls180.v:3412$1095_Y
+    connect \Y $and$ls180.v:3397$1063_Y
   end
-  attribute \src "ls180.v:3412.48-3412.164"
-  cell $and $and$ls180.v:3412$1097
+  attribute \src "ls180.v:3397.48-3397.164"
+  cell $and $and$ls180.v:3397$1065
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3412$1095_Y
-    connect \B $eq$ls180.v:3412$1096_Y
-    connect \Y $and$ls180.v:3412$1097_Y
+    connect \A $and$ls180.v:3397$1063_Y
+    connect \B $eq$ls180.v:3397$1064_Y
+    connect \Y $and$ls180.v:3397$1065_Y
   end
-  attribute \src "ls180.v:3413.49-3413.113"
-  cell $and $and$ls180.v:3413$1099
+  attribute \src "ls180.v:3398.49-3398.113"
+  cell $and $and$ls180.v:3398$1067
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
-    connect \B $not$ls180.v:3413$1098_Y
-    connect \Y $and$ls180.v:3413$1099_Y
+    connect \B $not$ls180.v:3398$1066_Y
+    connect \Y $and$ls180.v:3398$1067_Y
   end
-  attribute \src "ls180.v:3413.48-3413.167"
-  cell $and $and$ls180.v:3413$1101
+  attribute \src "ls180.v:3398.48-3398.167"
+  cell $and $and$ls180.v:3398$1069
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3413$1099_Y
-    connect \B $eq$ls180.v:3413$1100_Y
-    connect \Y $and$ls180.v:3413$1101_Y
+    connect \A $and$ls180.v:3398$1067_Y
+    connect \B $eq$ls180.v:3398$1068_Y
+    connect \Y $and$ls180.v:3398$1069_Y
   end
-  attribute \src "ls180.v:3415.49-3415.110"
-  cell $and $and$ls180.v:3415$1102
+  attribute \src "ls180.v:3400.49-3400.110"
+  cell $and $and$ls180.v:3400$1070
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -252804,263 +252320,263 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
     connect \B \libresocsim_interface7_bank_bus_we
-    connect \Y $and$ls180.v:3415$1102_Y
+    connect \Y $and$ls180.v:3400$1070_Y
   end
-  attribute \src "ls180.v:3415.48-3415.164"
-  cell $and $and$ls180.v:3415$1104
+  attribute \src "ls180.v:3400.48-3400.164"
+  cell $and $and$ls180.v:3400$1072
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3415$1102_Y
-    connect \B $eq$ls180.v:3415$1103_Y
-    connect \Y $and$ls180.v:3415$1104_Y
+    connect \A $and$ls180.v:3400$1070_Y
+    connect \B $eq$ls180.v:3400$1071_Y
+    connect \Y $and$ls180.v:3400$1072_Y
   end
-  attribute \src "ls180.v:3416.49-3416.113"
-  cell $and $and$ls180.v:3416$1106
+  attribute \src "ls180.v:3401.49-3401.113"
+  cell $and $and$ls180.v:3401$1074
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_csrbank7_sel
-    connect \B $not$ls180.v:3416$1105_Y
-    connect \Y $and$ls180.v:3416$1106_Y
+    connect \B $not$ls180.v:3401$1073_Y
+    connect \Y $and$ls180.v:3401$1074_Y
   end
-  attribute \src "ls180.v:3416.48-3416.167"
-  cell $and $and$ls180.v:3416$1108
+  attribute \src "ls180.v:3401.48-3401.167"
+  cell $and $and$ls180.v:3401$1076
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3416$1106_Y
-    connect \B $eq$ls180.v:3416$1107_Y
-    connect \Y $and$ls180.v:3416$1108_Y
+    connect \A $and$ls180.v:3401$1074_Y
+    connect \B $eq$ls180.v:3401$1075_Y
+    connect \Y $and$ls180.v:3401$1076_Y
   end
-  attribute \src "ls180.v:3776.96-3776.165"
-  cell $and $and$ls180.v:3776$1139
+  attribute \src "ls180.v:3761.96-3761.165"
+  cell $and $and$ls180.v:3761$1107
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3776$1138_Y
-    connect \Y $and$ls180.v:3776$1139_Y
+    connect \B $eq$ls180.v:3761$1106_Y
+    connect \Y $and$ls180.v:3761$1107_Y
   end
-  attribute \src "ls180.v:3776.171-3776.240"
-  cell $and $and$ls180.v:3776$1142
+  attribute \src "ls180.v:3761.171-3761.240"
+  cell $and $and$ls180.v:3761$1110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3776$1141_Y
-    connect \Y $and$ls180.v:3776$1142_Y
+    connect \B $eq$ls180.v:3761$1109_Y
+    connect \Y $and$ls180.v:3761$1110_Y
   end
-  attribute \src "ls180.v:3776.246-3776.315"
-  cell $and $and$ls180.v:3776$1145
+  attribute \src "ls180.v:3761.246-3761.315"
+  cell $and $and$ls180.v:3761$1113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3776$1144_Y
-    connect \Y $and$ls180.v:3776$1145_Y
+    connect \B $eq$ls180.v:3761$1112_Y
+    connect \Y $and$ls180.v:3761$1113_Y
   end
-  attribute \src "ls180.v:3776.27-3776.318"
-  cell $and $and$ls180.v:3776$1148
+  attribute \src "ls180.v:3761.27-3761.318"
+  cell $and $and$ls180.v:3761$1116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3776$1137_Y
-    connect \B $not$ls180.v:3776$1147_Y
-    connect \Y $and$ls180.v:3776$1148_Y
+    connect \A $eq$ls180.v:3761$1105_Y
+    connect \B $not$ls180.v:3761$1115_Y
+    connect \Y $and$ls180.v:3761$1116_Y
   end
-  attribute \src "ls180.v:3776.26-3776.336"
-  cell $and $and$ls180.v:3776$1149
+  attribute \src "ls180.v:3761.26-3761.336"
+  cell $and $and$ls180.v:3761$1117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3776$1148_Y
+    connect \A $and$ls180.v:3761$1116_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:3776$1149_Y
+    connect \Y $and$ls180.v:3761$1117_Y
   end
-  attribute \src "ls180.v:3800.96-3800.165"
-  cell $and $and$ls180.v:3800$1155
+  attribute \src "ls180.v:3785.96-3785.165"
+  cell $and $and$ls180.v:3785$1123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3800$1154_Y
-    connect \Y $and$ls180.v:3800$1155_Y
+    connect \B $eq$ls180.v:3785$1122_Y
+    connect \Y $and$ls180.v:3785$1123_Y
   end
-  attribute \src "ls180.v:3800.171-3800.240"
-  cell $and $and$ls180.v:3800$1158
+  attribute \src "ls180.v:3785.171-3785.240"
+  cell $and $and$ls180.v:3785$1126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3800$1157_Y
-    connect \Y $and$ls180.v:3800$1158_Y
+    connect \B $eq$ls180.v:3785$1125_Y
+    connect \Y $and$ls180.v:3785$1126_Y
   end
-  attribute \src "ls180.v:3800.246-3800.315"
-  cell $and $and$ls180.v:3800$1161
+  attribute \src "ls180.v:3785.246-3785.315"
+  cell $and $and$ls180.v:3785$1129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3800$1160_Y
-    connect \Y $and$ls180.v:3800$1161_Y
+    connect \B $eq$ls180.v:3785$1128_Y
+    connect \Y $and$ls180.v:3785$1129_Y
   end
-  attribute \src "ls180.v:3800.27-3800.318"
-  cell $and $and$ls180.v:3800$1164
+  attribute \src "ls180.v:3785.27-3785.318"
+  cell $and $and$ls180.v:3785$1132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3800$1153_Y
-    connect \B $not$ls180.v:3800$1163_Y
-    connect \Y $and$ls180.v:3800$1164_Y
+    connect \A $eq$ls180.v:3785$1121_Y
+    connect \B $not$ls180.v:3785$1131_Y
+    connect \Y $and$ls180.v:3785$1132_Y
   end
-  attribute \src "ls180.v:3800.26-3800.336"
-  cell $and $and$ls180.v:3800$1165
+  attribute \src "ls180.v:3785.26-3785.336"
+  cell $and $and$ls180.v:3785$1133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3800$1164_Y
+    connect \A $and$ls180.v:3785$1132_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:3800$1165_Y
+    connect \Y $and$ls180.v:3785$1133_Y
   end
-  attribute \src "ls180.v:3824.96-3824.165"
-  cell $and $and$ls180.v:3824$1171
+  attribute \src "ls180.v:3809.96-3809.165"
+  cell $and $and$ls180.v:3809$1139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3824$1170_Y
-    connect \Y $and$ls180.v:3824$1171_Y
+    connect \B $eq$ls180.v:3809$1138_Y
+    connect \Y $and$ls180.v:3809$1139_Y
   end
-  attribute \src "ls180.v:3824.171-3824.240"
-  cell $and $and$ls180.v:3824$1174
+  attribute \src "ls180.v:3809.171-3809.240"
+  cell $and $and$ls180.v:3809$1142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3824$1173_Y
-    connect \Y $and$ls180.v:3824$1174_Y
+    connect \B $eq$ls180.v:3809$1141_Y
+    connect \Y $and$ls180.v:3809$1142_Y
   end
-  attribute \src "ls180.v:3824.246-3824.315"
-  cell $and $and$ls180.v:3824$1177
+  attribute \src "ls180.v:3809.246-3809.315"
+  cell $and $and$ls180.v:3809$1145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \B $eq$ls180.v:3824$1176_Y
-    connect \Y $and$ls180.v:3824$1177_Y
+    connect \B $eq$ls180.v:3809$1144_Y
+    connect \Y $and$ls180.v:3809$1145_Y
   end
-  attribute \src "ls180.v:3824.27-3824.318"
-  cell $and $and$ls180.v:3824$1180
+  attribute \src "ls180.v:3809.27-3809.318"
+  cell $and $and$ls180.v:3809$1148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3824$1169_Y
-    connect \B $not$ls180.v:3824$1179_Y
-    connect \Y $and$ls180.v:3824$1180_Y
+    connect \A $eq$ls180.v:3809$1137_Y
+    connect \B $not$ls180.v:3809$1147_Y
+    connect \Y $and$ls180.v:3809$1148_Y
   end
-  attribute \src "ls180.v:3824.26-3824.336"
-  cell $and $and$ls180.v:3824$1181
+  attribute \src "ls180.v:3809.26-3809.336"
+  cell $and $and$ls180.v:3809$1149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3824$1180_Y
+    connect \A $and$ls180.v:3809$1148_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:3824$1181_Y
+    connect \Y $and$ls180.v:3809$1149_Y
   end
-  attribute \src "ls180.v:3848.96-3848.165"
-  cell $and $and$ls180.v:3848$1187
+  attribute \src "ls180.v:3833.96-3833.165"
+  cell $and $and$ls180.v:3833$1155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \B $eq$ls180.v:3848$1186_Y
-    connect \Y $and$ls180.v:3848$1187_Y
+    connect \B $eq$ls180.v:3833$1154_Y
+    connect \Y $and$ls180.v:3833$1155_Y
   end
-  attribute \src "ls180.v:3848.171-3848.240"
-  cell $and $and$ls180.v:3848$1190
+  attribute \src "ls180.v:3833.171-3833.240"
+  cell $and $and$ls180.v:3833$1158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \B $eq$ls180.v:3848$1189_Y
-    connect \Y $and$ls180.v:3848$1190_Y
+    connect \B $eq$ls180.v:3833$1157_Y
+    connect \Y $and$ls180.v:3833$1158_Y
   end
-  attribute \src "ls180.v:3848.246-3848.315"
-  cell $and $and$ls180.v:3848$1193
+  attribute \src "ls180.v:3833.246-3833.315"
+  cell $and $and$ls180.v:3833$1161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \B $eq$ls180.v:3848$1192_Y
-    connect \Y $and$ls180.v:3848$1193_Y
+    connect \B $eq$ls180.v:3833$1160_Y
+    connect \Y $and$ls180.v:3833$1161_Y
   end
-  attribute \src "ls180.v:3848.27-3848.318"
-  cell $and $and$ls180.v:3848$1196
+  attribute \src "ls180.v:3833.27-3833.318"
+  cell $and $and$ls180.v:3833$1164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:3848$1185_Y
-    connect \B $not$ls180.v:3848$1195_Y
-    connect \Y $and$ls180.v:3848$1196_Y
+    connect \A $eq$ls180.v:3833$1153_Y
+    connect \B $not$ls180.v:3833$1163_Y
+    connect \Y $and$ls180.v:3833$1164_Y
   end
-  attribute \src "ls180.v:3848.26-3848.336"
-  cell $and $and$ls180.v:3848$1197
+  attribute \src "ls180.v:3833.26-3833.336"
+  cell $and $and$ls180.v:3833$1165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:3848$1196_Y
+    connect \A $and$ls180.v:3833$1164_Y
     connect \B \port_cmd_valid
-    connect \Y $and$ls180.v:3848$1197_Y
+    connect \Y $and$ls180.v:3833$1165_Y
   end
-  attribute \src "ls180.v:4005.22-4005.77"
-  cell $and $and$ls180.v:4005$1209
+  attribute \src "ls180.v:3990.22-3990.77"
+  cell $and $and$ls180.v:3990$1177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253068,21 +252584,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4005$1209_Y
+    connect \Y $and$ls180.v:3990$1177_Y
   end
-  attribute \src "ls180.v:4005.21-4005.113"
-  cell $and $and$ls180.v:4005$1210
+  attribute \src "ls180.v:3990.21-3990.113"
+  cell $and $and$ls180.v:3990$1178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4005$1209_Y
+    connect \A $and$ls180.v:3990$1177_Y
     connect \B \sdram_choose_req_cmd_payload_cas
-    connect \Y $and$ls180.v:4005$1210_Y
+    connect \Y $and$ls180.v:3990$1178_Y
   end
-  attribute \src "ls180.v:4008.22-4008.77"
-  cell $and $and$ls180.v:4008$1211
+  attribute \src "ls180.v:3993.22-3993.77"
+  cell $and $and$ls180.v:3993$1179
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253090,21 +252606,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4008$1211_Y
+    connect \Y $and$ls180.v:3993$1179_Y
   end
-  attribute \src "ls180.v:4008.21-4008.113"
-  cell $and $and$ls180.v:4008$1212
+  attribute \src "ls180.v:3993.21-3993.113"
+  cell $and $and$ls180.v:3993$1180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4008$1211_Y
+    connect \A $and$ls180.v:3993$1179_Y
     connect \B \sdram_choose_req_cmd_payload_cas
-    connect \Y $and$ls180.v:4008$1212_Y
+    connect \Y $and$ls180.v:3993$1180_Y
   end
-  attribute \src "ls180.v:4011.22-4011.55"
-  cell $and $and$ls180.v:4011$1213
+  attribute \src "ls180.v:3996.22-3996.55"
+  cell $and $and$ls180.v:3996$1181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253112,21 +252628,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_cmd_valid
     connect \B \sdram_cmd_ready
-    connect \Y $and$ls180.v:4011$1213_Y
+    connect \Y $and$ls180.v:3996$1181_Y
   end
-  attribute \src "ls180.v:4011.21-4011.80"
-  cell $and $and$ls180.v:4011$1214
+  attribute \src "ls180.v:3996.21-3996.80"
+  cell $and $and$ls180.v:3996$1182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4011$1213_Y
+    connect \A $and$ls180.v:3996$1181_Y
     connect \B \sdram_cmd_payload_cas
-    connect \Y $and$ls180.v:4011$1214_Y
+    connect \Y $and$ls180.v:3996$1182_Y
   end
-  attribute \src "ls180.v:4022.22-4022.77"
-  cell $and $and$ls180.v:4022$1216
+  attribute \src "ls180.v:4007.22-4007.77"
+  cell $and $and$ls180.v:4007$1184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253134,21 +252650,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4022$1216_Y
+    connect \Y $and$ls180.v:4007$1184_Y
   end
-  attribute \src "ls180.v:4022.21-4022.113"
-  cell $and $and$ls180.v:4022$1217
+  attribute \src "ls180.v:4007.21-4007.113"
+  cell $and $and$ls180.v:4007$1185
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4022$1216_Y
+    connect \A $and$ls180.v:4007$1184_Y
     connect \B \sdram_choose_req_cmd_payload_ras
-    connect \Y $and$ls180.v:4022$1217_Y
+    connect \Y $and$ls180.v:4007$1185_Y
   end
-  attribute \src "ls180.v:4025.22-4025.77"
-  cell $and $and$ls180.v:4025$1218
+  attribute \src "ls180.v:4010.22-4010.77"
+  cell $and $and$ls180.v:4010$1186
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253156,21 +252672,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4025$1218_Y
+    connect \Y $and$ls180.v:4010$1186_Y
   end
-  attribute \src "ls180.v:4025.21-4025.113"
-  cell $and $and$ls180.v:4025$1219
+  attribute \src "ls180.v:4010.21-4010.113"
+  cell $and $and$ls180.v:4010$1187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4025$1218_Y
+    connect \A $and$ls180.v:4010$1186_Y
     connect \B \sdram_choose_req_cmd_payload_ras
-    connect \Y $and$ls180.v:4025$1219_Y
+    connect \Y $and$ls180.v:4010$1187_Y
   end
-  attribute \src "ls180.v:4028.22-4028.55"
-  cell $and $and$ls180.v:4028$1220
+  attribute \src "ls180.v:4013.22-4013.55"
+  cell $and $and$ls180.v:4013$1188
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253178,21 +252694,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_cmd_valid
     connect \B \sdram_cmd_ready
-    connect \Y $and$ls180.v:4028$1220_Y
+    connect \Y $and$ls180.v:4013$1188_Y
   end
-  attribute \src "ls180.v:4028.21-4028.80"
-  cell $and $and$ls180.v:4028$1221
+  attribute \src "ls180.v:4013.21-4013.80"
+  cell $and $and$ls180.v:4013$1189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4028$1220_Y
+    connect \A $and$ls180.v:4013$1188_Y
     connect \B \sdram_cmd_payload_ras
-    connect \Y $and$ls180.v:4028$1221_Y
+    connect \Y $and$ls180.v:4013$1189_Y
   end
-  attribute \src "ls180.v:4039.22-4039.77"
-  cell $and $and$ls180.v:4039$1223
+  attribute \src "ls180.v:4024.22-4024.77"
+  cell $and $and$ls180.v:4024$1191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253200,21 +252716,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4039$1223_Y
+    connect \Y $and$ls180.v:4024$1191_Y
   end
-  attribute \src "ls180.v:4039.21-4039.112"
-  cell $and $and$ls180.v:4039$1224
+  attribute \src "ls180.v:4024.21-4024.112"
+  cell $and $and$ls180.v:4024$1192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4039$1223_Y
+    connect \A $and$ls180.v:4024$1191_Y
     connect \B \sdram_choose_req_cmd_payload_we
-    connect \Y $and$ls180.v:4039$1224_Y
+    connect \Y $and$ls180.v:4024$1192_Y
   end
-  attribute \src "ls180.v:4042.22-4042.77"
-  cell $and $and$ls180.v:4042$1225
+  attribute \src "ls180.v:4027.22-4027.77"
+  cell $and $and$ls180.v:4027$1193
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253222,21 +252738,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4042$1225_Y
+    connect \Y $and$ls180.v:4027$1193_Y
   end
-  attribute \src "ls180.v:4042.21-4042.112"
-  cell $and $and$ls180.v:4042$1226
+  attribute \src "ls180.v:4027.21-4027.112"
+  cell $and $and$ls180.v:4027$1194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4042$1225_Y
+    connect \A $and$ls180.v:4027$1193_Y
     connect \B \sdram_choose_req_cmd_payload_we
-    connect \Y $and$ls180.v:4042$1226_Y
+    connect \Y $and$ls180.v:4027$1194_Y
   end
-  attribute \src "ls180.v:4045.22-4045.55"
-  cell $and $and$ls180.v:4045$1227
+  attribute \src "ls180.v:4030.22-4030.55"
+  cell $and $and$ls180.v:4030$1195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253244,21 +252760,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_cmd_valid
     connect \B \sdram_cmd_ready
-    connect \Y $and$ls180.v:4045$1227_Y
+    connect \Y $and$ls180.v:4030$1195_Y
   end
-  attribute \src "ls180.v:4045.21-4045.79"
-  cell $and $and$ls180.v:4045$1228
+  attribute \src "ls180.v:4030.21-4030.79"
+  cell $and $and$ls180.v:4030$1196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4045$1227_Y
+    connect \A $and$ls180.v:4030$1195_Y
     connect \B \sdram_cmd_payload_we
-    connect \Y $and$ls180.v:4045$1228_Y
+    connect \Y $and$ls180.v:4030$1196_Y
   end
-  attribute \src "ls180.v:4056.22-4056.77"
-  cell $and $and$ls180.v:4056$1230
+  attribute \src "ls180.v:4041.22-4041.77"
+  cell $and $and$ls180.v:4041$1198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253266,21 +252782,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4056$1230_Y
+    connect \Y $and$ls180.v:4041$1198_Y
   end
-  attribute \src "ls180.v:4056.21-4056.117"
-  cell $and $and$ls180.v:4056$1231
+  attribute \src "ls180.v:4041.21-4041.117"
+  cell $and $and$ls180.v:4041$1199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4056$1230_Y
+    connect \A $and$ls180.v:4041$1198_Y
     connect \B \sdram_choose_req_cmd_payload_is_read
-    connect \Y $and$ls180.v:4056$1231_Y
+    connect \Y $and$ls180.v:4041$1199_Y
   end
-  attribute \src "ls180.v:4059.22-4059.77"
-  cell $and $and$ls180.v:4059$1232
+  attribute \src "ls180.v:4044.22-4044.77"
+  cell $and $and$ls180.v:4044$1200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253288,21 +252804,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4059$1232_Y
+    connect \Y $and$ls180.v:4044$1200_Y
   end
-  attribute \src "ls180.v:4059.21-4059.117"
-  cell $and $and$ls180.v:4059$1233
+  attribute \src "ls180.v:4044.21-4044.117"
+  cell $and $and$ls180.v:4044$1201
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4059$1232_Y
+    connect \A $and$ls180.v:4044$1200_Y
     connect \B \sdram_choose_req_cmd_payload_is_read
-    connect \Y $and$ls180.v:4059$1233_Y
+    connect \Y $and$ls180.v:4044$1201_Y
   end
-  attribute \src "ls180.v:4062.22-4062.55"
-  cell $and $and$ls180.v:4062$1234
+  attribute \src "ls180.v:4047.22-4047.55"
+  cell $and $and$ls180.v:4047$1202
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253310,21 +252826,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_cmd_valid
     connect \B \sdram_cmd_ready
-    connect \Y $and$ls180.v:4062$1234_Y
+    connect \Y $and$ls180.v:4047$1202_Y
   end
-  attribute \src "ls180.v:4062.21-4062.84"
-  cell $and $and$ls180.v:4062$1235
+  attribute \src "ls180.v:4047.21-4047.84"
+  cell $and $and$ls180.v:4047$1203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4062$1234_Y
+    connect \A $and$ls180.v:4047$1202_Y
     connect \B \sdram_cmd_payload_is_read
-    connect \Y $and$ls180.v:4062$1235_Y
+    connect \Y $and$ls180.v:4047$1203_Y
   end
-  attribute \src "ls180.v:4073.22-4073.77"
-  cell $and $and$ls180.v:4073$1237
+  attribute \src "ls180.v:4058.22-4058.77"
+  cell $and $and$ls180.v:4058$1205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253332,21 +252848,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4073$1237_Y
+    connect \Y $and$ls180.v:4058$1205_Y
   end
-  attribute \src "ls180.v:4073.21-4073.118"
-  cell $and $and$ls180.v:4073$1238
+  attribute \src "ls180.v:4058.21-4058.118"
+  cell $and $and$ls180.v:4058$1206
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4073$1237_Y
+    connect \A $and$ls180.v:4058$1205_Y
     connect \B \sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:4073$1238_Y
+    connect \Y $and$ls180.v:4058$1206_Y
   end
-  attribute \src "ls180.v:4076.22-4076.77"
-  cell $and $and$ls180.v:4076$1239
+  attribute \src "ls180.v:4061.22-4061.77"
+  cell $and $and$ls180.v:4061$1207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253354,21 +252870,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
     connect \B \sdram_choose_req_cmd_ready
-    connect \Y $and$ls180.v:4076$1239_Y
+    connect \Y $and$ls180.v:4061$1207_Y
   end
-  attribute \src "ls180.v:4076.21-4076.118"
-  cell $and $and$ls180.v:4076$1240
+  attribute \src "ls180.v:4061.21-4061.118"
+  cell $and $and$ls180.v:4061$1208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4076$1239_Y
+    connect \A $and$ls180.v:4061$1207_Y
     connect \B \sdram_choose_req_cmd_payload_is_write
-    connect \Y $and$ls180.v:4076$1240_Y
+    connect \Y $and$ls180.v:4061$1208_Y
   end
-  attribute \src "ls180.v:4079.22-4079.55"
-  cell $and $and$ls180.v:4079$1241
+  attribute \src "ls180.v:4064.22-4064.55"
+  cell $and $and$ls180.v:4064$1209
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253376,21 +252892,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_cmd_valid
     connect \B \sdram_cmd_ready
-    connect \Y $and$ls180.v:4079$1241_Y
+    connect \Y $and$ls180.v:4064$1209_Y
   end
-  attribute \src "ls180.v:4079.21-4079.85"
-  cell $and $and$ls180.v:4079$1242
+  attribute \src "ls180.v:4064.21-4064.85"
+  cell $and $and$ls180.v:4064$1210
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4079$1241_Y
+    connect \A $and$ls180.v:4064$1209_Y
     connect \B \sdram_cmd_payload_is_write
-    connect \Y $and$ls180.v:4079$1242_Y
+    connect \Y $and$ls180.v:4064$1210_Y
   end
-  attribute \src "ls180.v:4247.57-4247.97"
-  cell $and $and$ls180.v:4247$1245
+  attribute \src "ls180.v:4232.57-4232.97"
+  cell $and $and$ls180.v:4232$1213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253398,10 +252914,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \dfi_p0_wrdata_en
     connect \B \dfi_p0_wrdata_mask [0]
-    connect \Y $and$ls180.v:4247$1245_Y
+    connect \Y $and$ls180.v:4232$1213_Y
   end
-  attribute \src "ls180.v:4248.57-4248.97"
-  cell $and $and$ls180.v:4248$1246
+  attribute \src "ls180.v:4233.57-4233.97"
+  cell $and $and$ls180.v:4233$1214
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253409,10 +252925,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \dfi_p0_wrdata_en
     connect \B \dfi_p0_wrdata_mask [1]
-    connect \Y $and$ls180.v:4248$1246_Y
+    connect \Y $and$ls180.v:4233$1214_Y
   end
-  attribute \src "ls180.v:4376.8-4376.57"
-  cell $and $and$ls180.v:4376$1289
+  attribute \src "ls180.v:4361.8-4361.57"
+  cell $and $and$ls180.v:4361$1257
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253420,32 +252936,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_cyc
     connect \B \libresocsim_ram_bus_stb
-    connect \Y $and$ls180.v:4376$1289_Y
+    connect \Y $and$ls180.v:4361$1257_Y
   end
-  attribute \src "ls180.v:4376.7-4376.87"
-  cell $and $and$ls180.v:4376$1291
+  attribute \src "ls180.v:4361.7-4361.87"
+  cell $and $and$ls180.v:4361$1259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4376$1289_Y
-    connect \B $not$ls180.v:4376$1290_Y
-    connect \Y $and$ls180.v:4376$1291_Y
+    connect \A $and$ls180.v:4361$1257_Y
+    connect \B $not$ls180.v:4361$1258_Y
+    connect \Y $and$ls180.v:4361$1259_Y
   end
-  attribute \src "ls180.v:4395.7-4395.65"
-  cell $and $and$ls180.v:4395$1295
+  attribute \src "ls180.v:4380.7-4380.65"
+  cell $and $and$ls180.v:4380$1263
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4395$1294_Y
+    connect \A $not$ls180.v:4380$1262_Y
     connect \B \libresocsim_zero_old_trigger
-    connect \Y $and$ls180.v:4395$1295_Y
+    connect \Y $and$ls180.v:4380$1263_Y
   end
-  attribute \src "ls180.v:4399.8-4399.49"
-  cell $and $and$ls180.v:4399$1296
+  attribute \src "ls180.v:4384.8-4384.49"
+  cell $and $and$ls180.v:4384$1264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253453,43 +252969,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_cyc
     connect \B \ram_bus_ram_bus_stb
-    connect \Y $and$ls180.v:4399$1296_Y
+    connect \Y $and$ls180.v:4384$1264_Y
   end
-  attribute \src "ls180.v:4399.7-4399.75"
-  cell $and $and$ls180.v:4399$1298
+  attribute \src "ls180.v:4384.7-4384.75"
+  cell $and $and$ls180.v:4384$1266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4399$1296_Y
-    connect \B $not$ls180.v:4399$1297_Y
-    connect \Y $and$ls180.v:4399$1298_Y
+    connect \A $and$ls180.v:4384$1264_Y
+    connect \B $not$ls180.v:4384$1265_Y
+    connect \Y $and$ls180.v:4384$1266_Y
   end
-  attribute \src "ls180.v:4407.7-4407.46"
-  cell $and $and$ls180.v:4407$1300
+  attribute \src "ls180.v:4392.7-4392.46"
+  cell $and $and$ls180.v:4392$1268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_timer_wait
-    connect \B $not$ls180.v:4407$1299_Y
-    connect \Y $and$ls180.v:4407$1300_Y
+    connect \B $not$ls180.v:4392$1267_Y
+    connect \Y $and$ls180.v:4392$1268_Y
   end
-  attribute \src "ls180.v:4435.7-4435.65"
-  cell $and $and$ls180.v:4435$1307
+  attribute \src "ls180.v:4420.7-4420.65"
+  cell $and $and$ls180.v:4420$1275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_start1
-    connect \B $eq$ls180.v:4435$1306_Y
-    connect \Y $and$ls180.v:4435$1307_Y
+    connect \B $eq$ls180.v:4420$1274_Y
+    connect \Y $and$ls180.v:4420$1275_Y
   end
-  attribute \src "ls180.v:4477.8-4477.121"
-  cell $and $and$ls180.v:4477$1313
+  attribute \src "ls180.v:4462.8-4462.121"
+  cell $and $and$ls180.v:4462$1281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253497,21 +253013,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:4477$1313_Y
+    connect \Y $and$ls180.v:4462$1281_Y
   end
-  attribute \src "ls180.v:4477.7-4477.175"
-  cell $and $and$ls180.v:4477$1315
+  attribute \src "ls180.v:4462.7-4462.175"
+  cell $and $and$ls180.v:4462$1283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4477$1313_Y
-    connect \B $not$ls180.v:4477$1314_Y
-    connect \Y $and$ls180.v:4477$1315_Y
+    connect \A $and$ls180.v:4462$1281_Y
+    connect \B $not$ls180.v:4462$1282_Y
+    connect \Y $and$ls180.v:4462$1283_Y
   end
-  attribute \src "ls180.v:4483.8-4483.121"
-  cell $and $and$ls180.v:4483$1318
+  attribute \src "ls180.v:4468.8-4468.121"
+  cell $and $and$ls180.v:4468$1286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253519,21 +253035,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
     connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
-    connect \Y $and$ls180.v:4483$1318_Y
+    connect \Y $and$ls180.v:4468$1286_Y
   end
-  attribute \src "ls180.v:4483.7-4483.175"
-  cell $and $and$ls180.v:4483$1320
+  attribute \src "ls180.v:4468.7-4468.175"
+  cell $and $and$ls180.v:4468$1288
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4483$1318_Y
-    connect \B $not$ls180.v:4483$1319_Y
-    connect \Y $and$ls180.v:4483$1320_Y
+    connect \A $and$ls180.v:4468$1286_Y
+    connect \B $not$ls180.v:4468$1287_Y
+    connect \Y $and$ls180.v:4468$1288_Y
   end
-  attribute \src "ls180.v:4523.8-4523.121"
-  cell $and $and$ls180.v:4523$1329
+  attribute \src "ls180.v:4508.8-4508.121"
+  cell $and $and$ls180.v:4508$1297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253541,21 +253057,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:4523$1329_Y
+    connect \Y $and$ls180.v:4508$1297_Y
   end
-  attribute \src "ls180.v:4523.7-4523.175"
-  cell $and $and$ls180.v:4523$1331
+  attribute \src "ls180.v:4508.7-4508.175"
+  cell $and $and$ls180.v:4508$1299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4523$1329_Y
-    connect \B $not$ls180.v:4523$1330_Y
-    connect \Y $and$ls180.v:4523$1331_Y
+    connect \A $and$ls180.v:4508$1297_Y
+    connect \B $not$ls180.v:4508$1298_Y
+    connect \Y $and$ls180.v:4508$1299_Y
   end
-  attribute \src "ls180.v:4529.8-4529.121"
-  cell $and $and$ls180.v:4529$1334
+  attribute \src "ls180.v:4514.8-4514.121"
+  cell $and $and$ls180.v:4514$1302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253563,21 +253079,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
     connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
-    connect \Y $and$ls180.v:4529$1334_Y
+    connect \Y $and$ls180.v:4514$1302_Y
   end
-  attribute \src "ls180.v:4529.7-4529.175"
-  cell $and $and$ls180.v:4529$1336
+  attribute \src "ls180.v:4514.7-4514.175"
+  cell $and $and$ls180.v:4514$1304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4529$1334_Y
-    connect \B $not$ls180.v:4529$1335_Y
-    connect \Y $and$ls180.v:4529$1336_Y
+    connect \A $and$ls180.v:4514$1302_Y
+    connect \B $not$ls180.v:4514$1303_Y
+    connect \Y $and$ls180.v:4514$1304_Y
   end
-  attribute \src "ls180.v:4569.8-4569.121"
-  cell $and $and$ls180.v:4569$1345
+  attribute \src "ls180.v:4554.8-4554.121"
+  cell $and $and$ls180.v:4554$1313
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253585,21 +253101,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:4569$1345_Y
+    connect \Y $and$ls180.v:4554$1313_Y
   end
-  attribute \src "ls180.v:4569.7-4569.175"
-  cell $and $and$ls180.v:4569$1347
+  attribute \src "ls180.v:4554.7-4554.175"
+  cell $and $and$ls180.v:4554$1315
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4569$1345_Y
-    connect \B $not$ls180.v:4569$1346_Y
-    connect \Y $and$ls180.v:4569$1347_Y
+    connect \A $and$ls180.v:4554$1313_Y
+    connect \B $not$ls180.v:4554$1314_Y
+    connect \Y $and$ls180.v:4554$1315_Y
   end
-  attribute \src "ls180.v:4575.8-4575.121"
-  cell $and $and$ls180.v:4575$1350
+  attribute \src "ls180.v:4560.8-4560.121"
+  cell $and $and$ls180.v:4560$1318
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253607,21 +253123,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
     connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
-    connect \Y $and$ls180.v:4575$1350_Y
+    connect \Y $and$ls180.v:4560$1318_Y
   end
-  attribute \src "ls180.v:4575.7-4575.175"
-  cell $and $and$ls180.v:4575$1352
+  attribute \src "ls180.v:4560.7-4560.175"
+  cell $and $and$ls180.v:4560$1320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4575$1350_Y
-    connect \B $not$ls180.v:4575$1351_Y
-    connect \Y $and$ls180.v:4575$1352_Y
+    connect \A $and$ls180.v:4560$1318_Y
+    connect \B $not$ls180.v:4560$1319_Y
+    connect \Y $and$ls180.v:4560$1320_Y
   end
-  attribute \src "ls180.v:4615.8-4615.121"
-  cell $and $and$ls180.v:4615$1361
+  attribute \src "ls180.v:4600.8-4600.121"
+  cell $and $and$ls180.v:4600$1329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253629,21 +253145,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:4615$1361_Y
+    connect \Y $and$ls180.v:4600$1329_Y
   end
-  attribute \src "ls180.v:4615.7-4615.175"
-  cell $and $and$ls180.v:4615$1363
+  attribute \src "ls180.v:4600.7-4600.175"
+  cell $and $and$ls180.v:4600$1331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4615$1361_Y
-    connect \B $not$ls180.v:4615$1362_Y
-    connect \Y $and$ls180.v:4615$1363_Y
+    connect \A $and$ls180.v:4600$1329_Y
+    connect \B $not$ls180.v:4600$1330_Y
+    connect \Y $and$ls180.v:4600$1331_Y
   end
-  attribute \src "ls180.v:4621.8-4621.121"
-  cell $and $and$ls180.v:4621$1366
+  attribute \src "ls180.v:4606.8-4606.121"
+  cell $and $and$ls180.v:4606$1334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253651,109 +253167,109 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
     connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
-    connect \Y $and$ls180.v:4621$1366_Y
+    connect \Y $and$ls180.v:4606$1334_Y
   end
-  attribute \src "ls180.v:4621.7-4621.175"
-  cell $and $and$ls180.v:4621$1368
+  attribute \src "ls180.v:4606.7-4606.175"
+  cell $and $and$ls180.v:4606$1336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4621$1366_Y
-    connect \B $not$ls180.v:4621$1367_Y
-    connect \Y $and$ls180.v:4621$1368_Y
+    connect \A $and$ls180.v:4606$1334_Y
+    connect \B $not$ls180.v:4606$1335_Y
+    connect \Y $and$ls180.v:4606$1336_Y
   end
-  attribute \src "ls180.v:4818.53-4818.129"
-  cell $and $and$ls180.v:4818$1393
+  attribute \src "ls180.v:4803.53-4803.129"
+  cell $and $and$ls180.v:4803$1361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4818$1392_Y
+    connect \A $eq$ls180.v:4803$1360_Y
     connect \B \sdram_interface_bank0_wdata_ready
-    connect \Y $and$ls180.v:4818$1393_Y
+    connect \Y $and$ls180.v:4803$1361_Y
   end
-  attribute \src "ls180.v:4818.135-4818.211"
-  cell $and $and$ls180.v:4818$1396
+  attribute \src "ls180.v:4803.135-4803.211"
+  cell $and $and$ls180.v:4803$1364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4818$1395_Y
+    connect \A $eq$ls180.v:4803$1363_Y
     connect \B \sdram_interface_bank1_wdata_ready
-    connect \Y $and$ls180.v:4818$1396_Y
+    connect \Y $and$ls180.v:4803$1364_Y
   end
-  attribute \src "ls180.v:4818.217-4818.293"
-  cell $and $and$ls180.v:4818$1399
+  attribute \src "ls180.v:4803.217-4803.293"
+  cell $and $and$ls180.v:4803$1367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4818$1398_Y
+    connect \A $eq$ls180.v:4803$1366_Y
     connect \B \sdram_interface_bank2_wdata_ready
-    connect \Y $and$ls180.v:4818$1399_Y
+    connect \Y $and$ls180.v:4803$1367_Y
   end
-  attribute \src "ls180.v:4818.299-4818.375"
-  cell $and $and$ls180.v:4818$1402
+  attribute \src "ls180.v:4803.299-4803.375"
+  cell $and $and$ls180.v:4803$1370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4818$1401_Y
+    connect \A $eq$ls180.v:4803$1369_Y
     connect \B \sdram_interface_bank3_wdata_ready
-    connect \Y $and$ls180.v:4818$1402_Y
+    connect \Y $and$ls180.v:4803$1370_Y
   end
-  attribute \src "ls180.v:4819.54-4819.130"
-  cell $and $and$ls180.v:4819$1405
+  attribute \src "ls180.v:4804.54-4804.130"
+  cell $and $and$ls180.v:4804$1373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4819$1404_Y
+    connect \A $eq$ls180.v:4804$1372_Y
     connect \B \sdram_interface_bank0_rdata_valid
-    connect \Y $and$ls180.v:4819$1405_Y
+    connect \Y $and$ls180.v:4804$1373_Y
   end
-  attribute \src "ls180.v:4819.136-4819.212"
-  cell $and $and$ls180.v:4819$1408
+  attribute \src "ls180.v:4804.136-4804.212"
+  cell $and $and$ls180.v:4804$1376
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4819$1407_Y
+    connect \A $eq$ls180.v:4804$1375_Y
     connect \B \sdram_interface_bank1_rdata_valid
-    connect \Y $and$ls180.v:4819$1408_Y
+    connect \Y $and$ls180.v:4804$1376_Y
   end
-  attribute \src "ls180.v:4819.218-4819.294"
-  cell $and $and$ls180.v:4819$1411
+  attribute \src "ls180.v:4804.218-4804.294"
+  cell $and $and$ls180.v:4804$1379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4819$1410_Y
+    connect \A $eq$ls180.v:4804$1378_Y
     connect \B \sdram_interface_bank2_rdata_valid
-    connect \Y $and$ls180.v:4819$1411_Y
+    connect \Y $and$ls180.v:4804$1379_Y
   end
-  attribute \src "ls180.v:4819.300-4819.376"
-  cell $and $and$ls180.v:4819$1414
+  attribute \src "ls180.v:4804.300-4804.376"
+  cell $and $and$ls180.v:4804$1382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $eq$ls180.v:4819$1413_Y
+    connect \A $eq$ls180.v:4804$1381_Y
     connect \B \sdram_interface_bank3_rdata_valid
-    connect \Y $and$ls180.v:4819$1414_Y
+    connect \Y $and$ls180.v:4804$1382_Y
   end
-  attribute \src "ls180.v:4838.8-4838.39"
-  cell $and $and$ls180.v:4838$1417
+  attribute \src "ls180.v:4823.8-4823.39"
+  cell $and $and$ls180.v:4823$1385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253761,10 +253277,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_valid
     connect \B \port_cmd_ready
-    connect \Y $and$ls180.v:4838$1417_Y
+    connect \Y $and$ls180.v:4823$1385_Y
   end
-  attribute \src "ls180.v:4841.8-4841.43"
-  cell $and $and$ls180.v:4841$1418
+  attribute \src "ls180.v:4826.8-4826.43"
+  cell $and $and$ls180.v:4826$1386
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253772,32 +253288,32 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_wdata_valid
     connect \B \port_wdata_ready
-    connect \Y $and$ls180.v:4841$1418_Y
+    connect \Y $and$ls180.v:4826$1386_Y
   end
-  attribute \src "ls180.v:4846.8-4846.49"
-  cell $and $and$ls180.v:4846$1420
+  attribute \src "ls180.v:4831.8-4831.49"
+  cell $and $and$ls180.v:4831$1388
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \uart_phy_sink_valid
-    connect \B $not$ls180.v:4846$1419_Y
-    connect \Y $and$ls180.v:4846$1420_Y
+    connect \B $not$ls180.v:4831$1387_Y
+    connect \Y $and$ls180.v:4831$1388_Y
   end
-  attribute \src "ls180.v:4846.7-4846.75"
-  cell $and $and$ls180.v:4846$1422
+  attribute \src "ls180.v:4831.7-4831.75"
+  cell $and $and$ls180.v:4831$1390
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4846$1420_Y
-    connect \B $not$ls180.v:4846$1421_Y
-    connect \Y $and$ls180.v:4846$1422_Y
+    connect \A $and$ls180.v:4831$1388_Y
+    connect \B $not$ls180.v:4831$1389_Y
+    connect \Y $and$ls180.v:4831$1390_Y
   end
-  attribute \src "ls180.v:4852.8-4852.49"
-  cell $and $and$ls180.v:4852$1423
+  attribute \src "ls180.v:4837.8-4837.49"
+  cell $and $and$ls180.v:4837$1391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253805,43 +253321,43 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \uart_phy_uart_clk_txen
     connect \B \uart_phy_tx_busy
-    connect \Y $and$ls180.v:4852$1423_Y
+    connect \Y $and$ls180.v:4837$1391_Y
   end
-  attribute \src "ls180.v:4876.8-4876.38"
-  cell $and $and$ls180.v:4876$1430
+  attribute \src "ls180.v:4861.8-4861.38"
+  cell $and $and$ls180.v:4861$1398
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4876$1429_Y
+    connect \A $not$ls180.v:4861$1397_Y
     connect \B \uart_phy_rx_r
-    connect \Y $and$ls180.v:4876$1430_Y
+    connect \Y $and$ls180.v:4861$1398_Y
   end
-  attribute \src "ls180.v:4909.7-4909.37"
-  cell $and $and$ls180.v:4909$1436
+  attribute \src "ls180.v:4894.7-4894.37"
+  cell $and $and$ls180.v:4894$1404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4909$1435_Y
+    connect \A $not$ls180.v:4894$1403_Y
     connect \B \tx_old_trigger
-    connect \Y $and$ls180.v:4909$1436_Y
+    connect \Y $and$ls180.v:4894$1404_Y
   end
-  attribute \src "ls180.v:4916.7-4916.37"
-  cell $and $and$ls180.v:4916$1438
+  attribute \src "ls180.v:4901.7-4901.37"
+  cell $and $and$ls180.v:4901$1406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4916$1437_Y
+    connect \A $not$ls180.v:4901$1405_Y
     connect \B \rx_old_trigger
-    connect \Y $and$ls180.v:4916$1438_Y
+    connect \Y $and$ls180.v:4901$1406_Y
   end
-  attribute \src "ls180.v:4926.8-4926.55"
-  cell $and $and$ls180.v:4926$1439
+  attribute \src "ls180.v:4911.8-4911.55"
+  cell $and $and$ls180.v:4911$1407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253849,21 +253365,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_we
     connect \B \tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:4926$1439_Y
+    connect \Y $and$ls180.v:4911$1407_Y
   end
-  attribute \src "ls180.v:4926.7-4926.77"
-  cell $and $and$ls180.v:4926$1441
+  attribute \src "ls180.v:4911.7-4911.77"
+  cell $and $and$ls180.v:4911$1409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4926$1439_Y
-    connect \B $not$ls180.v:4926$1440_Y
-    connect \Y $and$ls180.v:4926$1441_Y
+    connect \A $and$ls180.v:4911$1407_Y
+    connect \B $not$ls180.v:4911$1408_Y
+    connect \Y $and$ls180.v:4911$1409_Y
   end
-  attribute \src "ls180.v:4932.8-4932.55"
-  cell $and $and$ls180.v:4932$1444
+  attribute \src "ls180.v:4917.8-4917.55"
+  cell $and $and$ls180.v:4917$1412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253871,21 +253387,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_we
     connect \B \tx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:4932$1444_Y
+    connect \Y $and$ls180.v:4917$1412_Y
   end
-  attribute \src "ls180.v:4932.7-4932.77"
-  cell $and $and$ls180.v:4932$1446
+  attribute \src "ls180.v:4917.7-4917.77"
+  cell $and $and$ls180.v:4917$1414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4932$1444_Y
-    connect \B $not$ls180.v:4932$1445_Y
-    connect \Y $and$ls180.v:4932$1446_Y
+    connect \A $and$ls180.v:4917$1412_Y
+    connect \B $not$ls180.v:4917$1413_Y
+    connect \Y $and$ls180.v:4917$1414_Y
   end
-  attribute \src "ls180.v:4948.8-4948.55"
-  cell $and $and$ls180.v:4948$1450
+  attribute \src "ls180.v:4933.8-4933.55"
+  cell $and $and$ls180.v:4933$1418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253893,21 +253409,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_we
     connect \B \rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:4948$1450_Y
+    connect \Y $and$ls180.v:4933$1418_Y
   end
-  attribute \src "ls180.v:4948.7-4948.77"
-  cell $and $and$ls180.v:4948$1452
+  attribute \src "ls180.v:4933.7-4933.77"
+  cell $and $and$ls180.v:4933$1420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4948$1450_Y
-    connect \B $not$ls180.v:4948$1451_Y
-    connect \Y $and$ls180.v:4948$1452_Y
+    connect \A $and$ls180.v:4933$1418_Y
+    connect \B $not$ls180.v:4933$1419_Y
+    connect \Y $and$ls180.v:4933$1420_Y
   end
-  attribute \src "ls180.v:4954.8-4954.55"
-  cell $and $and$ls180.v:4954$1455
+  attribute \src "ls180.v:4939.8-4939.55"
+  cell $and $and$ls180.v:4939$1423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -253915,87 +253431,87 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_we
     connect \B \rx_fifo_syncfifo_writable
-    connect \Y $and$ls180.v:4954$1455_Y
+    connect \Y $and$ls180.v:4939$1423_Y
   end
-  attribute \src "ls180.v:4954.7-4954.77"
-  cell $and $and$ls180.v:4954$1457
+  attribute \src "ls180.v:4939.7-4939.77"
+  cell $and $and$ls180.v:4939$1425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:4954$1455_Y
-    connect \B $not$ls180.v:4954$1456_Y
-    connect \Y $and$ls180.v:4954$1457_Y
+    connect \A $and$ls180.v:4939$1423_Y
+    connect \B $not$ls180.v:4939$1424_Y
+    connect \Y $and$ls180.v:4939$1425_Y
   end
-  attribute \src "ls180.v:1563.25-1563.66"
-  cell $eq $eq$ls180.v:1563$29
+  attribute \src "ls180.v:1556.37-1556.91"
+  cell $eq $eq$ls180.v:1556$21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_icp_sel
+    connect \A \libresocsim_interface0_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:1563$29_Y
+    connect \Y $eq$ls180.v:1556$21_Y
   end
-  attribute \src "ls180.v:1570.11-1570.37"
-  cell $eq $eq$ls180.v:1570$34
+  attribute \src "ls180.v:1563.11-1563.49"
+  cell $eq $eq$ls180.v:1563$26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter0_counter
+    connect \A \libresocsim_converter0_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:1570$34_Y
+    connect \Y $eq$ls180.v:1563$26_Y
   end
-  attribute \src "ls180.v:1623.25-1623.66"
-  cell $eq $eq$ls180.v:1623$40
+  attribute \src "ls180.v:1616.37-1616.91"
+  cell $eq $eq$ls180.v:1616$32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_ics_sel
+    connect \A \libresocsim_interface1_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:1623$40_Y
+    connect \Y $eq$ls180.v:1616$32_Y
   end
-  attribute \src "ls180.v:1630.11-1630.37"
-  cell $eq $eq$ls180.v:1630$45
+  attribute \src "ls180.v:1623.11-1623.49"
+  cell $eq $eq$ls180.v:1623$37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter1_counter
+    connect \A \libresocsim_converter1_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:1630$45_Y
+    connect \Y $eq$ls180.v:1623$37_Y
   end
-  attribute \src "ls180.v:1683.28-1683.48"
-  cell $eq $eq$ls180.v:1683$51
+  attribute \src "ls180.v:1676.37-1676.91"
+  cell $eq $eq$ls180.v:1676$43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wb_sdram_sel
+    connect \A \libresocsim_interface2_converted_interface_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:1683$51_Y
+    connect \Y $eq$ls180.v:1676$43_Y
   end
-  attribute \src "ls180.v:1690.11-1690.40"
-  cell $eq $eq$ls180.v:1690$56
+  attribute \src "ls180.v:1683.11-1683.49"
+  cell $eq $eq$ls180.v:1683$48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_counter
+    connect \A \libresocsim_converter2_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:1690$56_Y
+    connect \Y $eq$ls180.v:1683$48_Y
   end
-  attribute \src "ls180.v:1894.29-1894.55"
-  cell $eq $eq$ls180.v:1894$121
+  attribute \src "ls180.v:1879.29-1879.55"
+  cell $eq $eq$ls180.v:1879$89
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -254003,10 +253519,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_timer_count1
     connect \B 1'0
-    connect \Y $eq$ls180.v:1894$121_Y
+    connect \Y $eq$ls180.v:1879$89_Y
   end
-  attribute \src "ls180.v:1898.58-1898.87"
-  cell $eq $eq$ls180.v:1898$124
+  attribute \src "ls180.v:1883.58-1883.87"
+  cell $eq $eq$ls180.v:1883$92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254014,10 +253530,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:1898$124_Y
+    connect \Y $eq$ls180.v:1883$92_Y
   end
-  attribute \src "ls180.v:1942.38-1942.119"
-  cell $eq $eq$ls180.v:1942$129
+  attribute \src "ls180.v:1927.38-1927.119"
+  cell $eq $eq$ls180.v:1927$97
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254025,10 +253541,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_row
     connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:1942$129_Y
+    connect \Y $eq$ls180.v:1927$97_Y
   end
-  attribute \src "ls180.v:1959.42-1959.78"
-  cell $eq $eq$ls180.v:1959$142
+  attribute \src "ls180.v:1944.42-1944.78"
+  cell $eq $eq$ls180.v:1944$110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254036,10 +253552,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:1959$142_Y
+    connect \Y $eq$ls180.v:1944$110_Y
   end
-  attribute \src "ls180.v:2099.38-2099.119"
-  cell $eq $eq$ls180.v:2099$159
+  attribute \src "ls180.v:2084.38-2084.119"
+  cell $eq $eq$ls180.v:2084$127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254047,10 +253563,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_row
     connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:2099$159_Y
+    connect \Y $eq$ls180.v:2084$127_Y
   end
-  attribute \src "ls180.v:2116.42-2116.78"
-  cell $eq $eq$ls180.v:2116$172
+  attribute \src "ls180.v:2101.42-2101.78"
+  cell $eq $eq$ls180.v:2101$140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254058,10 +253574,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:2116$172_Y
+    connect \Y $eq$ls180.v:2101$140_Y
   end
-  attribute \src "ls180.v:2256.38-2256.119"
-  cell $eq $eq$ls180.v:2256$189
+  attribute \src "ls180.v:2241.38-2241.119"
+  cell $eq $eq$ls180.v:2241$157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254069,10 +253585,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_row
     connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:2256$189_Y
+    connect \Y $eq$ls180.v:2241$157_Y
   end
-  attribute \src "ls180.v:2273.42-2273.78"
-  cell $eq $eq$ls180.v:2273$202
+  attribute \src "ls180.v:2258.42-2258.78"
+  cell $eq $eq$ls180.v:2258$170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254080,10 +253596,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:2273$202_Y
+    connect \Y $eq$ls180.v:2258$170_Y
   end
-  attribute \src "ls180.v:2413.38-2413.119"
-  cell $eq $eq$ls180.v:2413$219
+  attribute \src "ls180.v:2398.38-2398.119"
+  cell $eq $eq$ls180.v:2398$187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -254091,10 +253607,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_row
     connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $eq$ls180.v:2413$219_Y
+    connect \Y $eq$ls180.v:2398$187_Y
   end
-  attribute \src "ls180.v:2430.42-2430.78"
-  cell $eq $eq$ls180.v:2430$232
+  attribute \src "ls180.v:2415.42-2415.78"
+  cell $eq $eq$ls180.v:2415$200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254102,10 +253618,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_row_close
     connect \B 1'0
-    connect \Y $eq$ls180.v:2430$232_Y
+    connect \Y $eq$ls180.v:2415$200_Y
   end
-  attribute \src "ls180.v:2567.27-2567.46"
-  cell $eq $eq$ls180.v:2567$279
+  attribute \src "ls180.v:2552.27-2552.46"
+  cell $eq $eq$ls180.v:2552$247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -254113,10 +253629,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_time0
     connect \B 1'0
-    connect \Y $eq$ls180.v:2567$279_Y
+    connect \Y $eq$ls180.v:2552$247_Y
   end
-  attribute \src "ls180.v:2568.27-2568.46"
-  cell $eq $eq$ls180.v:2568$280
+  attribute \src "ls180.v:2553.27-2553.46"
+  cell $eq $eq$ls180.v:2553$248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254124,10 +253640,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_time1
     connect \B 1'0
-    connect \Y $eq$ls180.v:2568$280_Y
+    connect \Y $eq$ls180.v:2553$248_Y
   end
-  attribute \src "ls180.v:2579.299-2579.368"
-  cell $eq $eq$ls180.v:2579$294
+  attribute \src "ls180.v:2564.299-2564.368"
+  cell $eq $eq$ls180.v:2564$262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254135,10 +253651,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_read
     connect \B \sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:2579$294_Y
+    connect \Y $eq$ls180.v:2564$262_Y
   end
-  attribute \src "ls180.v:2579.373-2579.444"
-  cell $eq $eq$ls180.v:2579$295
+  attribute \src "ls180.v:2564.373-2564.444"
+  cell $eq $eq$ls180.v:2564$263
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254146,10 +253662,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_write
     connect \B \sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:2579$295_Y
+    connect \Y $eq$ls180.v:2564$263_Y
   end
-  attribute \src "ls180.v:2580.299-2580.368"
-  cell $eq $eq$ls180.v:2580$307
+  attribute \src "ls180.v:2565.299-2565.368"
+  cell $eq $eq$ls180.v:2565$275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254157,10 +253673,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_read
     connect \B \sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:2580$307_Y
+    connect \Y $eq$ls180.v:2565$275_Y
   end
-  attribute \src "ls180.v:2580.373-2580.444"
-  cell $eq $eq$ls180.v:2580$308
+  attribute \src "ls180.v:2565.373-2565.444"
+  cell $eq $eq$ls180.v:2565$276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254168,10 +253684,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_write
     connect \B \sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:2580$308_Y
+    connect \Y $eq$ls180.v:2565$276_Y
   end
-  attribute \src "ls180.v:2581.299-2581.368"
-  cell $eq $eq$ls180.v:2581$320
+  attribute \src "ls180.v:2566.299-2566.368"
+  cell $eq $eq$ls180.v:2566$288
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254179,10 +253695,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_read
     connect \B \sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:2581$320_Y
+    connect \Y $eq$ls180.v:2566$288_Y
   end
-  attribute \src "ls180.v:2581.373-2581.444"
-  cell $eq $eq$ls180.v:2581$321
+  attribute \src "ls180.v:2566.373-2566.444"
+  cell $eq $eq$ls180.v:2566$289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254190,10 +253706,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_write
     connect \B \sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:2581$321_Y
+    connect \Y $eq$ls180.v:2566$289_Y
   end
-  attribute \src "ls180.v:2582.299-2582.368"
-  cell $eq $eq$ls180.v:2582$333
+  attribute \src "ls180.v:2567.299-2567.368"
+  cell $eq $eq$ls180.v:2567$301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254201,10 +253717,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_read
     connect \B \sdram_choose_cmd_want_reads
-    connect \Y $eq$ls180.v:2582$333_Y
+    connect \Y $eq$ls180.v:2567$301_Y
   end
-  attribute \src "ls180.v:2582.373-2582.444"
-  cell $eq $eq$ls180.v:2582$334
+  attribute \src "ls180.v:2567.373-2567.444"
+  cell $eq $eq$ls180.v:2567$302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254212,10 +253728,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_write
     connect \B \sdram_choose_cmd_want_writes
-    connect \Y $eq$ls180.v:2582$334_Y
+    connect \Y $eq$ls180.v:2567$302_Y
   end
-  attribute \src "ls180.v:2612.299-2612.368"
-  cell $eq $eq$ls180.v:2612$352
+  attribute \src "ls180.v:2597.299-2597.368"
+  cell $eq $eq$ls180.v:2597$320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254223,10 +253739,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_read
     connect \B \sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:2612$352_Y
+    connect \Y $eq$ls180.v:2597$320_Y
   end
-  attribute \src "ls180.v:2612.373-2612.444"
-  cell $eq $eq$ls180.v:2612$353
+  attribute \src "ls180.v:2597.373-2597.444"
+  cell $eq $eq$ls180.v:2597$321
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254234,10 +253750,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_is_write
     connect \B \sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:2612$353_Y
+    connect \Y $eq$ls180.v:2597$321_Y
   end
-  attribute \src "ls180.v:2613.299-2613.368"
-  cell $eq $eq$ls180.v:2613$365
+  attribute \src "ls180.v:2598.299-2598.368"
+  cell $eq $eq$ls180.v:2598$333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254245,10 +253761,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_read
     connect \B \sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:2613$365_Y
+    connect \Y $eq$ls180.v:2598$333_Y
   end
-  attribute \src "ls180.v:2613.373-2613.444"
-  cell $eq $eq$ls180.v:2613$366
+  attribute \src "ls180.v:2598.373-2598.444"
+  cell $eq $eq$ls180.v:2598$334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254256,10 +253772,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_is_write
     connect \B \sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:2613$366_Y
+    connect \Y $eq$ls180.v:2598$334_Y
   end
-  attribute \src "ls180.v:2614.299-2614.368"
-  cell $eq $eq$ls180.v:2614$378
+  attribute \src "ls180.v:2599.299-2599.368"
+  cell $eq $eq$ls180.v:2599$346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254267,10 +253783,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_read
     connect \B \sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:2614$378_Y
+    connect \Y $eq$ls180.v:2599$346_Y
   end
-  attribute \src "ls180.v:2614.373-2614.444"
-  cell $eq $eq$ls180.v:2614$379
+  attribute \src "ls180.v:2599.373-2599.444"
+  cell $eq $eq$ls180.v:2599$347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254278,10 +253794,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_is_write
     connect \B \sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:2614$379_Y
+    connect \Y $eq$ls180.v:2599$347_Y
   end
-  attribute \src "ls180.v:2615.299-2615.368"
-  cell $eq $eq$ls180.v:2615$391
+  attribute \src "ls180.v:2600.299-2600.368"
+  cell $eq $eq$ls180.v:2600$359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254289,10 +253805,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_read
     connect \B \sdram_choose_req_want_reads
-    connect \Y $eq$ls180.v:2615$391_Y
+    connect \Y $eq$ls180.v:2600$359_Y
   end
-  attribute \src "ls180.v:2615.373-2615.444"
-  cell $eq $eq$ls180.v:2615$392
+  attribute \src "ls180.v:2600.373-2600.444"
+  cell $eq $eq$ls180.v:2600$360
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254300,10 +253816,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_is_write
     connect \B \sdram_choose_req_want_writes
-    connect \Y $eq$ls180.v:2615$392_Y
+    connect \Y $eq$ls180.v:2600$360_Y
   end
-  attribute \src "ls180.v:2644.68-2644.98"
-  cell $eq $eq$ls180.v:2644$401
+  attribute \src "ls180.v:2629.68-2629.98"
+  cell $eq $eq$ls180.v:2629$369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254311,10 +253827,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2644$401_Y
+    connect \Y $eq$ls180.v:2629$369_Y
   end
-  attribute \src "ls180.v:2647.68-2647.98"
-  cell $eq $eq$ls180.v:2647$404
+  attribute \src "ls180.v:2632.68-2632.98"
+  cell $eq $eq$ls180.v:2632$372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254322,10 +253838,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2647$404_Y
+    connect \Y $eq$ls180.v:2632$372_Y
   end
-  attribute \src "ls180.v:2653.68-2653.98"
-  cell $eq $eq$ls180.v:2653$408
+  attribute \src "ls180.v:2638.68-2638.98"
+  cell $eq $eq$ls180.v:2638$376
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254333,10 +253849,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:2653$408_Y
+    connect \Y $eq$ls180.v:2638$376_Y
   end
-  attribute \src "ls180.v:2656.68-2656.98"
-  cell $eq $eq$ls180.v:2656$411
+  attribute \src "ls180.v:2641.68-2641.98"
+  cell $eq $eq$ls180.v:2641$379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254344,10 +253860,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:2656$411_Y
+    connect \Y $eq$ls180.v:2641$379_Y
   end
-  attribute \src "ls180.v:2662.68-2662.98"
-  cell $eq $eq$ls180.v:2662$415
+  attribute \src "ls180.v:2647.68-2647.98"
+  cell $eq $eq$ls180.v:2647$383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254355,10 +253871,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:2662$415_Y
+    connect \Y $eq$ls180.v:2647$383_Y
   end
-  attribute \src "ls180.v:2665.68-2665.98"
-  cell $eq $eq$ls180.v:2665$418
+  attribute \src "ls180.v:2650.68-2650.98"
+  cell $eq $eq$ls180.v:2650$386
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254366,10 +253882,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:2665$418_Y
+    connect \Y $eq$ls180.v:2650$386_Y
   end
-  attribute \src "ls180.v:2671.68-2671.98"
-  cell $eq $eq$ls180.v:2671$422
+  attribute \src "ls180.v:2656.68-2656.98"
+  cell $eq $eq$ls180.v:2656$390
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254377,10 +253893,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:2671$422_Y
+    connect \Y $eq$ls180.v:2656$390_Y
   end
-  attribute \src "ls180.v:2674.68-2674.98"
-  cell $eq $eq$ls180.v:2674$425
+  attribute \src "ls180.v:2659.68-2659.98"
+  cell $eq $eq$ls180.v:2659$393
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254388,10 +253904,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_grant
     connect \B 2'11
-    connect \Y $eq$ls180.v:2674$425_Y
+    connect \Y $eq$ls180.v:2659$393_Y
   end
-  attribute \src "ls180.v:2755.47-2755.82"
-  cell $eq $eq$ls180.v:2755$448
+  attribute \src "ls180.v:2740.47-2740.82"
+  cell $eq $eq$ls180.v:2740$416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254399,10 +253915,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:2755$448_Y
+    connect \Y $eq$ls180.v:2740$416_Y
   end
-  attribute \src "ls180.v:2755.145-2755.183"
-  cell $eq $eq$ls180.v:2755$449
+  attribute \src "ls180.v:2740.145-2740.183"
+  cell $eq $eq$ls180.v:2740$417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254410,10 +253926,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2755$449_Y
+    connect \Y $eq$ls180.v:2740$417_Y
   end
-  attribute \src "ls180.v:2755.220-2755.258"
-  cell $eq $eq$ls180.v:2755$452
+  attribute \src "ls180.v:2740.220-2740.258"
+  cell $eq $eq$ls180.v:2740$420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254421,10 +253937,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2755$452_Y
+    connect \Y $eq$ls180.v:2740$420_Y
   end
-  attribute \src "ls180.v:2755.295-2755.333"
-  cell $eq $eq$ls180.v:2755$455
+  attribute \src "ls180.v:2740.295-2740.333"
+  cell $eq $eq$ls180.v:2740$423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254432,10 +253948,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2755$455_Y
+    connect \Y $eq$ls180.v:2740$423_Y
   end
-  attribute \src "ls180.v:2760.47-2760.82"
-  cell $eq $eq$ls180.v:2760$464
+  attribute \src "ls180.v:2745.47-2745.82"
+  cell $eq $eq$ls180.v:2745$432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254443,10 +253959,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:2760$464_Y
+    connect \Y $eq$ls180.v:2745$432_Y
   end
-  attribute \src "ls180.v:2760.145-2760.183"
-  cell $eq $eq$ls180.v:2760$465
+  attribute \src "ls180.v:2745.145-2745.183"
+  cell $eq $eq$ls180.v:2745$433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254454,10 +253970,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2760$465_Y
+    connect \Y $eq$ls180.v:2745$433_Y
   end
-  attribute \src "ls180.v:2760.220-2760.258"
-  cell $eq $eq$ls180.v:2760$468
+  attribute \src "ls180.v:2745.220-2745.258"
+  cell $eq $eq$ls180.v:2745$436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254465,10 +253981,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2760$468_Y
+    connect \Y $eq$ls180.v:2745$436_Y
   end
-  attribute \src "ls180.v:2760.295-2760.333"
-  cell $eq $eq$ls180.v:2760$471
+  attribute \src "ls180.v:2745.295-2745.333"
+  cell $eq $eq$ls180.v:2745$439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254476,10 +253992,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2760$471_Y
+    connect \Y $eq$ls180.v:2745$439_Y
   end
-  attribute \src "ls180.v:2765.47-2765.82"
-  cell $eq $eq$ls180.v:2765$480
+  attribute \src "ls180.v:2750.47-2750.82"
+  cell $eq $eq$ls180.v:2750$448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254487,10 +254003,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:2765$480_Y
+    connect \Y $eq$ls180.v:2750$448_Y
   end
-  attribute \src "ls180.v:2765.145-2765.183"
-  cell $eq $eq$ls180.v:2765$481
+  attribute \src "ls180.v:2750.145-2750.183"
+  cell $eq $eq$ls180.v:2750$449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254498,10 +254014,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2765$481_Y
+    connect \Y $eq$ls180.v:2750$449_Y
   end
-  attribute \src "ls180.v:2765.220-2765.258"
-  cell $eq $eq$ls180.v:2765$484
+  attribute \src "ls180.v:2750.220-2750.258"
+  cell $eq $eq$ls180.v:2750$452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254509,10 +254025,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2765$484_Y
+    connect \Y $eq$ls180.v:2750$452_Y
   end
-  attribute \src "ls180.v:2765.295-2765.333"
-  cell $eq $eq$ls180.v:2765$487
+  attribute \src "ls180.v:2750.295-2750.333"
+  cell $eq $eq$ls180.v:2750$455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254520,10 +254036,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2765$487_Y
+    connect \Y $eq$ls180.v:2750$455_Y
   end
-  attribute \src "ls180.v:2770.47-2770.82"
-  cell $eq $eq$ls180.v:2770$496
+  attribute \src "ls180.v:2755.47-2755.82"
+  cell $eq $eq$ls180.v:2755$464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254531,10 +254047,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:2770$496_Y
+    connect \Y $eq$ls180.v:2755$464_Y
   end
-  attribute \src "ls180.v:2770.145-2770.183"
-  cell $eq $eq$ls180.v:2770$497
+  attribute \src "ls180.v:2755.145-2755.183"
+  cell $eq $eq$ls180.v:2755$465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254542,10 +254058,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2770$497_Y
+    connect \Y $eq$ls180.v:2755$465_Y
   end
-  attribute \src "ls180.v:2770.220-2770.258"
-  cell $eq $eq$ls180.v:2770$500
+  attribute \src "ls180.v:2755.220-2755.258"
+  cell $eq $eq$ls180.v:2755$468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254553,10 +254069,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2770$500_Y
+    connect \Y $eq$ls180.v:2755$468_Y
   end
-  attribute \src "ls180.v:2770.295-2770.333"
-  cell $eq $eq$ls180.v:2770$503
+  attribute \src "ls180.v:2755.295-2755.333"
+  cell $eq $eq$ls180.v:2755$471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254564,10 +254080,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2770$503_Y
+    connect \Y $eq$ls180.v:2755$471_Y
   end
-  attribute \src "ls180.v:2775.39-2775.77"
-  cell $eq $eq$ls180.v:2775$512
+  attribute \src "ls180.v:2760.39-2760.77"
+  cell $eq $eq$ls180.v:2760$480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254575,10 +254091,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$512_Y
+    connect \Y $eq$ls180.v:2760$480_Y
   end
-  attribute \src "ls180.v:2775.83-2775.118"
-  cell $eq $eq$ls180.v:2775$513
+  attribute \src "ls180.v:2760.83-2760.118"
+  cell $eq $eq$ls180.v:2760$481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254586,10 +254102,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$513_Y
+    connect \Y $eq$ls180.v:2760$481_Y
   end
-  attribute \src "ls180.v:2775.181-2775.219"
-  cell $eq $eq$ls180.v:2775$514
+  attribute \src "ls180.v:2760.181-2760.219"
+  cell $eq $eq$ls180.v:2760$482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254597,10 +254113,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$514_Y
+    connect \Y $eq$ls180.v:2760$482_Y
   end
-  attribute \src "ls180.v:2775.256-2775.294"
-  cell $eq $eq$ls180.v:2775$517
+  attribute \src "ls180.v:2760.256-2760.294"
+  cell $eq $eq$ls180.v:2760$485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254608,10 +254124,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$517_Y
+    connect \Y $eq$ls180.v:2760$485_Y
   end
-  attribute \src "ls180.v:2775.331-2775.369"
-  cell $eq $eq$ls180.v:2775$520
+  attribute \src "ls180.v:2760.331-2760.369"
+  cell $eq $eq$ls180.v:2760$488
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254619,10 +254135,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$520_Y
+    connect \Y $eq$ls180.v:2760$488_Y
   end
-  attribute \src "ls180.v:2775.413-2775.451"
-  cell $eq $eq$ls180.v:2775$528
+  attribute \src "ls180.v:2760.413-2760.451"
+  cell $eq $eq$ls180.v:2760$496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254630,10 +254146,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$528_Y
+    connect \Y $eq$ls180.v:2760$496_Y
   end
-  attribute \src "ls180.v:2775.457-2775.492"
-  cell $eq $eq$ls180.v:2775$529
+  attribute \src "ls180.v:2760.457-2760.492"
+  cell $eq $eq$ls180.v:2760$497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254641,10 +254157,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:2775$529_Y
+    connect \Y $eq$ls180.v:2760$497_Y
   end
-  attribute \src "ls180.v:2775.555-2775.593"
-  cell $eq $eq$ls180.v:2775$530
+  attribute \src "ls180.v:2760.555-2760.593"
+  cell $eq $eq$ls180.v:2760$498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254652,10 +254168,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$530_Y
+    connect \Y $eq$ls180.v:2760$498_Y
   end
-  attribute \src "ls180.v:2775.630-2775.668"
-  cell $eq $eq$ls180.v:2775$533
+  attribute \src "ls180.v:2760.630-2760.668"
+  cell $eq $eq$ls180.v:2760$501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254663,10 +254179,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$533_Y
+    connect \Y $eq$ls180.v:2760$501_Y
   end
-  attribute \src "ls180.v:2775.705-2775.743"
-  cell $eq $eq$ls180.v:2775$536
+  attribute \src "ls180.v:2760.705-2760.743"
+  cell $eq $eq$ls180.v:2760$504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254674,10 +254190,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$536_Y
+    connect \Y $eq$ls180.v:2760$504_Y
   end
-  attribute \src "ls180.v:2775.787-2775.825"
-  cell $eq $eq$ls180.v:2775$544
+  attribute \src "ls180.v:2760.787-2760.825"
+  cell $eq $eq$ls180.v:2760$512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254685,10 +254201,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$544_Y
+    connect \Y $eq$ls180.v:2760$512_Y
   end
-  attribute \src "ls180.v:2775.831-2775.866"
-  cell $eq $eq$ls180.v:2775$545
+  attribute \src "ls180.v:2760.831-2760.866"
+  cell $eq $eq$ls180.v:2760$513
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254696,10 +254212,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:2775$545_Y
+    connect \Y $eq$ls180.v:2760$513_Y
   end
-  attribute \src "ls180.v:2775.929-2775.967"
-  cell $eq $eq$ls180.v:2775$546
+  attribute \src "ls180.v:2760.929-2760.967"
+  cell $eq $eq$ls180.v:2760$514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254707,10 +254223,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$546_Y
+    connect \Y $eq$ls180.v:2760$514_Y
   end
-  attribute \src "ls180.v:2775.1004-2775.1042"
-  cell $eq $eq$ls180.v:2775$549
+  attribute \src "ls180.v:2760.1004-2760.1042"
+  cell $eq $eq$ls180.v:2760$517
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254718,10 +254234,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$549_Y
+    connect \Y $eq$ls180.v:2760$517_Y
   end
-  attribute \src "ls180.v:2775.1079-2775.1117"
-  cell $eq $eq$ls180.v:2775$552
+  attribute \src "ls180.v:2760.1079-2760.1117"
+  cell $eq $eq$ls180.v:2760$520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254729,10 +254245,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$552_Y
+    connect \Y $eq$ls180.v:2760$520_Y
   end
-  attribute \src "ls180.v:2775.1161-2775.1199"
-  cell $eq $eq$ls180.v:2775$560
+  attribute \src "ls180.v:2760.1161-2760.1199"
+  cell $eq $eq$ls180.v:2760$528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254740,10 +254256,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$560_Y
+    connect \Y $eq$ls180.v:2760$528_Y
   end
-  attribute \src "ls180.v:2775.1205-2775.1240"
-  cell $eq $eq$ls180.v:2775$561
+  attribute \src "ls180.v:2760.1205-2760.1240"
+  cell $eq $eq$ls180.v:2760$529
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254751,10 +254267,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:2775$561_Y
+    connect \Y $eq$ls180.v:2760$529_Y
   end
-  attribute \src "ls180.v:2775.1303-2775.1341"
-  cell $eq $eq$ls180.v:2775$562
+  attribute \src "ls180.v:2760.1303-2760.1341"
+  cell $eq $eq$ls180.v:2760$530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254762,10 +254278,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$562_Y
+    connect \Y $eq$ls180.v:2760$530_Y
   end
-  attribute \src "ls180.v:2775.1378-2775.1416"
-  cell $eq $eq$ls180.v:2775$565
+  attribute \src "ls180.v:2760.1378-2760.1416"
+  cell $eq $eq$ls180.v:2760$533
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254773,10 +254289,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$565_Y
+    connect \Y $eq$ls180.v:2760$533_Y
   end
-  attribute \src "ls180.v:2775.1453-2775.1491"
-  cell $eq $eq$ls180.v:2775$568
+  attribute \src "ls180.v:2760.1453-2760.1491"
+  cell $eq $eq$ls180.v:2760$536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254784,10 +254300,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:2775$568_Y
+    connect \Y $eq$ls180.v:2760$536_Y
   end
-  attribute \src "ls180.v:2834.24-2834.47"
-  cell $eq $eq$ls180.v:2834$581
+  attribute \src "ls180.v:2819.24-2819.47"
+  cell $eq $eq$ls180.v:2819$549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254795,10 +254311,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_sel
     connect \B 1'0
-    connect \Y $eq$ls180.v:2834$581_Y
+    connect \Y $eq$ls180.v:2819$549_Y
   end
-  attribute \src "ls180.v:2841.11-2841.36"
-  cell $eq $eq$ls180.v:2841$586
+  attribute \src "ls180.v:2826.11-2826.36"
+  cell $eq $eq$ls180.v:2826$554
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -254806,10 +254322,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \converter_counter
     connect \B 1'1
-    connect \Y $eq$ls180.v:2841$586_Y
+    connect \Y $eq$ls180.v:2826$554_Y
   end
-  attribute \src "ls180.v:3098.67-3098.92"
-  cell $eq $eq$ls180.v:3098$658
+  attribute \src "ls180.v:3083.84-3083.109"
+  cell $eq $eq$ls180.v:3083$626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254817,10 +254333,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3098$658_Y
+    connect \Y $eq$ls180.v:3083$626_Y
   end
-  attribute \src "ls180.v:3099.67-3099.92"
-  cell $eq $eq$ls180.v:3099$660
+  attribute \src "ls180.v:3084.84-3084.109"
+  cell $eq $eq$ls180.v:3084$628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254828,10 +254344,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:3099$660_Y
+    connect \Y $eq$ls180.v:3084$628_Y
   end
-  attribute \src "ls180.v:3100.70-3100.95"
-  cell $eq $eq$ls180.v:3100$662
+  attribute \src "ls180.v:3085.84-3085.109"
+  cell $eq $eq$ls180.v:3085$630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254839,10 +254355,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:3100$662_Y
+    connect \Y $eq$ls180.v:3085$630_Y
   end
-  attribute \src "ls180.v:3101.67-3101.92"
-  cell $eq $eq$ls180.v:3101$664
+  attribute \src "ls180.v:3086.84-3086.109"
+  cell $eq $eq$ls180.v:3086$632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254850,10 +254366,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3101$664_Y
+    connect \Y $eq$ls180.v:3086$632_Y
   end
-  attribute \src "ls180.v:3102.67-3102.92"
-  cell $eq $eq$ls180.v:3102$666
+  attribute \src "ls180.v:3087.84-3087.109"
+  cell $eq $eq$ls180.v:3087$634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254861,10 +254377,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 1'1
-    connect \Y $eq$ls180.v:3102$666_Y
+    connect \Y $eq$ls180.v:3087$634_Y
   end
-  attribute \src "ls180.v:3103.70-3103.95"
-  cell $eq $eq$ls180.v:3103$668
+  attribute \src "ls180.v:3088.84-3088.109"
+  cell $eq $eq$ls180.v:3088$636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -254872,76 +254388,76 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_grant
     connect \B 2'10
-    connect \Y $eq$ls180.v:3103$668_Y
+    connect \Y $eq$ls180.v:3088$636_Y
   end
-  attribute \src "ls180.v:3107.31-3107.67"
-  cell $eq $eq$ls180.v:3107$671
+  attribute \src "ls180.v:3092.31-3092.67"
+  cell $eq $eq$ls180.v:3092$639
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 24
+    parameter \A_WIDTH 23
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:6]
+    connect \A \libresocsim_shared_adr [29:7]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3107$671_Y
+    connect \Y $eq$ls180.v:3092$639_Y
   end
-  attribute \src "ls180.v:3108.31-3108.68"
-  cell $eq $eq$ls180.v:3108$672
+  attribute \src "ls180.v:3093.31-3093.68"
+  cell $eq $eq$ls180.v:3093$640
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 26
+    parameter \A_WIDTH 25
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:4]
+    connect \A \libresocsim_shared_adr [29:5]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:3108$672_Y
+    connect \Y $eq$ls180.v:3093$640_Y
   end
-  attribute \src "ls180.v:3109.31-3109.76"
-  cell $eq $eq$ls180.v:3109$673
+  attribute \src "ls180.v:3094.31-3094.76"
+  cell $eq $eq$ls180.v:3094$641
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 28
+    parameter \A_WIDTH 27
     parameter \B_SIGNED 0
     parameter \B_WIDTH 27
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:2]
+    connect \A \libresocsim_shared_adr [29:3]
     connect \B 27'110000000000000100000000000
-    connect \Y $eq$ls180.v:3109$673_Y
+    connect \Y $eq$ls180.v:3094$641_Y
   end
-  attribute \src "ls180.v:3110.31-3110.73"
-  cell $eq $eq$ls180.v:3110$674
+  attribute \src "ls180.v:3095.31-3095.74"
+  cell $eq $eq$ls180.v:3095$642
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 21
+    parameter \A_WIDTH 20
     parameter \B_SIGNED 0
     parameter \B_WIDTH 20
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:9]
+    connect \A \libresocsim_shared_adr [29:10]
     connect \B 20'11000000000000010001
-    connect \Y $eq$ls180.v:3110$674_Y
+    connect \Y $eq$ls180.v:3095$642_Y
   end
-  attribute \src "ls180.v:3111.31-3111.69"
-  cell $eq $eq$ls180.v:3111$675
+  attribute \src "ls180.v:3096.31-3096.69"
+  cell $eq $eq$ls180.v:3096$643
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:22]
+    connect \A \libresocsim_shared_adr [29:23]
     connect \B 7'1001000
-    connect \Y $eq$ls180.v:3111$675_Y
+    connect \Y $eq$ls180.v:3096$643_Y
   end
-  attribute \src "ls180.v:3112.31-3112.73"
-  cell $eq $eq$ls180.v:3112$676
+  attribute \src "ls180.v:3097.31-3097.73"
+  cell $eq $eq$ls180.v:3097$644
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 17
+    parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 16
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_shared_adr [29:13]
+    connect \A \libresocsim_shared_adr [29:14]
     connect \B 16'1100000000000000
-    connect \Y $eq$ls180.v:3112$676_Y
+    connect \Y $eq$ls180.v:3097$644_Y
   end
-  attribute \src "ls180.v:3176.28-3176.53"
-  cell $eq $eq$ls180.v:3176$708
+  attribute \src "ls180.v:3161.28-3161.53"
+  cell $eq $eq$ls180.v:3161$676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -254949,21 +254465,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:3176$708_Y
+    connect \Y $eq$ls180.v:3161$676_Y
   end
-  attribute \src "ls180.v:3177.36-3177.85"
-  cell $eq $eq$ls180.v:3177$709
+  attribute \src "ls180.v:3162.36-3162.85"
+  cell $eq $eq$ls180.v:3162$677
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface0_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface0_bank_bus_adr [13:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3177$709_Y
+    connect \Y $eq$ls180.v:3162$677_Y
   end
-  attribute \src "ls180.v:3179.109-3179.157"
-  cell $eq $eq$ls180.v:3179$711
+  attribute \src "ls180.v:3164.109-3164.157"
+  cell $eq $eq$ls180.v:3164$679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254971,10 +254487,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3179$711_Y
+    connect \Y $eq$ls180.v:3164$679_Y
   end
-  attribute \src "ls180.v:3180.112-3180.160"
-  cell $eq $eq$ls180.v:3180$715
+  attribute \src "ls180.v:3165.112-3165.160"
+  cell $eq $eq$ls180.v:3165$683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254982,10 +254498,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3180$715_Y
+    connect \Y $eq$ls180.v:3165$683_Y
   end
-  attribute \src "ls180.v:3182.111-3182.159"
-  cell $eq $eq$ls180.v:3182$718
+  attribute \src "ls180.v:3167.111-3167.159"
+  cell $eq $eq$ls180.v:3167$686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -254993,10 +254509,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3182$718_Y
+    connect \Y $eq$ls180.v:3167$686_Y
   end
-  attribute \src "ls180.v:3183.114-3183.162"
-  cell $eq $eq$ls180.v:3183$722
+  attribute \src "ls180.v:3168.114-3168.162"
+  cell $eq $eq$ls180.v:3168$690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255004,10 +254520,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3183$722_Y
+    connect \Y $eq$ls180.v:3168$690_Y
   end
-  attribute \src "ls180.v:3185.111-3185.159"
-  cell $eq $eq$ls180.v:3185$725
+  attribute \src "ls180.v:3170.111-3170.159"
+  cell $eq $eq$ls180.v:3170$693
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255015,10 +254531,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3185$725_Y
+    connect \Y $eq$ls180.v:3170$693_Y
   end
-  attribute \src "ls180.v:3186.114-3186.162"
-  cell $eq $eq$ls180.v:3186$729
+  attribute \src "ls180.v:3171.114-3171.162"
+  cell $eq $eq$ls180.v:3171$697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255026,10 +254542,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3186$729_Y
+    connect \Y $eq$ls180.v:3171$697_Y
   end
-  attribute \src "ls180.v:3188.111-3188.159"
-  cell $eq $eq$ls180.v:3188$732
+  attribute \src "ls180.v:3173.111-3173.159"
+  cell $eq $eq$ls180.v:3173$700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255037,10 +254553,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3188$732_Y
+    connect \Y $eq$ls180.v:3173$700_Y
   end
-  attribute \src "ls180.v:3189.114-3189.162"
-  cell $eq $eq$ls180.v:3189$736
+  attribute \src "ls180.v:3174.114-3174.162"
+  cell $eq $eq$ls180.v:3174$704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255048,10 +254564,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3189$736_Y
+    connect \Y $eq$ls180.v:3174$704_Y
   end
-  attribute \src "ls180.v:3191.111-3191.159"
-  cell $eq $eq$ls180.v:3191$739
+  attribute \src "ls180.v:3176.111-3176.159"
+  cell $eq $eq$ls180.v:3176$707
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255059,10 +254575,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3191$739_Y
+    connect \Y $eq$ls180.v:3176$707_Y
   end
-  attribute \src "ls180.v:3192.114-3192.162"
-  cell $eq $eq$ls180.v:3192$743
+  attribute \src "ls180.v:3177.114-3177.162"
+  cell $eq $eq$ls180.v:3177$711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255070,10 +254586,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3192$743_Y
+    connect \Y $eq$ls180.v:3177$711_Y
   end
-  attribute \src "ls180.v:3194.114-3194.162"
-  cell $eq $eq$ls180.v:3194$746
+  attribute \src "ls180.v:3179.114-3179.162"
+  cell $eq $eq$ls180.v:3179$714
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255081,10 +254597,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3194$746_Y
+    connect \Y $eq$ls180.v:3179$714_Y
   end
-  attribute \src "ls180.v:3195.117-3195.165"
-  cell $eq $eq$ls180.v:3195$750
+  attribute \src "ls180.v:3180.117-3180.165"
+  cell $eq $eq$ls180.v:3180$718
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255092,10 +254608,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3195$750_Y
+    connect \Y $eq$ls180.v:3180$718_Y
   end
-  attribute \src "ls180.v:3197.114-3197.162"
-  cell $eq $eq$ls180.v:3197$753
+  attribute \src "ls180.v:3182.114-3182.162"
+  cell $eq $eq$ls180.v:3182$721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255103,10 +254619,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3197$753_Y
+    connect \Y $eq$ls180.v:3182$721_Y
   end
-  attribute \src "ls180.v:3198.117-3198.165"
-  cell $eq $eq$ls180.v:3198$757
+  attribute \src "ls180.v:3183.117-3183.165"
+  cell $eq $eq$ls180.v:3183$725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255114,10 +254630,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3198$757_Y
+    connect \Y $eq$ls180.v:3183$725_Y
   end
-  attribute \src "ls180.v:3200.114-3200.162"
-  cell $eq $eq$ls180.v:3200$760
+  attribute \src "ls180.v:3185.114-3185.162"
+  cell $eq $eq$ls180.v:3185$728
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255125,10 +254641,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3200$760_Y
+    connect \Y $eq$ls180.v:3185$728_Y
   end
-  attribute \src "ls180.v:3201.117-3201.165"
-  cell $eq $eq$ls180.v:3201$764
+  attribute \src "ls180.v:3186.117-3186.165"
+  cell $eq $eq$ls180.v:3186$732
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255136,10 +254652,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3201$764_Y
+    connect \Y $eq$ls180.v:3186$732_Y
   end
-  attribute \src "ls180.v:3203.114-3203.162"
-  cell $eq $eq$ls180.v:3203$767
+  attribute \src "ls180.v:3188.114-3188.162"
+  cell $eq $eq$ls180.v:3188$735
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255147,10 +254663,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3203$767_Y
+    connect \Y $eq$ls180.v:3188$735_Y
   end
-  attribute \src "ls180.v:3204.117-3204.165"
-  cell $eq $eq$ls180.v:3204$771
+  attribute \src "ls180.v:3189.117-3189.165"
+  cell $eq $eq$ls180.v:3189$739
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255158,21 +254674,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3204$771_Y
+    connect \Y $eq$ls180.v:3189$739_Y
   end
-  attribute \src "ls180.v:3215.36-3215.85"
-  cell $eq $eq$ls180.v:3215$773
+  attribute \src "ls180.v:3200.36-3200.85"
+  cell $eq $eq$ls180.v:3200$741
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface1_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface1_bank_bus_adr [13:9]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3215$773_Y
+    connect \Y $eq$ls180.v:3200$741_Y
   end
-  attribute \src "ls180.v:3217.106-3217.154"
-  cell $eq $eq$ls180.v:3217$775
+  attribute \src "ls180.v:3202.106-3202.154"
+  cell $eq $eq$ls180.v:3202$743
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255180,10 +254696,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3217$775_Y
+    connect \Y $eq$ls180.v:3202$743_Y
   end
-  attribute \src "ls180.v:3218.109-3218.157"
-  cell $eq $eq$ls180.v:3218$779
+  attribute \src "ls180.v:3203.109-3203.157"
+  cell $eq $eq$ls180.v:3203$747
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255191,10 +254707,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3218$779_Y
+    connect \Y $eq$ls180.v:3203$747_Y
   end
-  attribute \src "ls180.v:3220.105-3220.153"
-  cell $eq $eq$ls180.v:3220$782
+  attribute \src "ls180.v:3205.105-3205.153"
+  cell $eq $eq$ls180.v:3205$750
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255202,10 +254718,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3220$782_Y
+    connect \Y $eq$ls180.v:3205$750_Y
   end
-  attribute \src "ls180.v:3221.108-3221.156"
-  cell $eq $eq$ls180.v:3221$786
+  attribute \src "ls180.v:3206.108-3206.156"
+  cell $eq $eq$ls180.v:3206$754
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255213,10 +254729,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3221$786_Y
+    connect \Y $eq$ls180.v:3206$754_Y
   end
-  attribute \src "ls180.v:3223.107-3223.155"
-  cell $eq $eq$ls180.v:3223$789
+  attribute \src "ls180.v:3208.107-3208.155"
+  cell $eq $eq$ls180.v:3208$757
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255224,10 +254740,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3223$789_Y
+    connect \Y $eq$ls180.v:3208$757_Y
   end
-  attribute \src "ls180.v:3224.110-3224.158"
-  cell $eq $eq$ls180.v:3224$793
+  attribute \src "ls180.v:3209.110-3209.158"
+  cell $eq $eq$ls180.v:3209$761
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255235,21 +254751,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3224$793_Y
+    connect \Y $eq$ls180.v:3209$761_Y
   end
-  attribute \src "ls180.v:3229.36-3229.85"
-  cell $eq $eq$ls180.v:3229$795
+  attribute \src "ls180.v:3214.36-3214.85"
+  cell $eq $eq$ls180.v:3214$763
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface2_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface2_bank_bus_adr [13:9]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3229$795_Y
+    connect \Y $eq$ls180.v:3214$763_Y
   end
-  attribute \src "ls180.v:3231.106-3231.154"
-  cell $eq $eq$ls180.v:3231$797
+  attribute \src "ls180.v:3216.106-3216.154"
+  cell $eq $eq$ls180.v:3216$765
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255257,10 +254773,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3231$797_Y
+    connect \Y $eq$ls180.v:3216$765_Y
   end
-  attribute \src "ls180.v:3232.109-3232.157"
-  cell $eq $eq$ls180.v:3232$801
+  attribute \src "ls180.v:3217.109-3217.157"
+  cell $eq $eq$ls180.v:3217$769
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255268,10 +254784,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3232$801_Y
+    connect \Y $eq$ls180.v:3217$769_Y
   end
-  attribute \src "ls180.v:3234.105-3234.153"
-  cell $eq $eq$ls180.v:3234$804
+  attribute \src "ls180.v:3219.105-3219.153"
+  cell $eq $eq$ls180.v:3219$772
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255279,10 +254795,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3234$804_Y
+    connect \Y $eq$ls180.v:3219$772_Y
   end
-  attribute \src "ls180.v:3235.108-3235.156"
-  cell $eq $eq$ls180.v:3235$808
+  attribute \src "ls180.v:3220.108-3220.156"
+  cell $eq $eq$ls180.v:3220$776
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255290,10 +254806,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3235$808_Y
+    connect \Y $eq$ls180.v:3220$776_Y
   end
-  attribute \src "ls180.v:3237.107-3237.155"
-  cell $eq $eq$ls180.v:3237$811
+  attribute \src "ls180.v:3222.107-3222.155"
+  cell $eq $eq$ls180.v:3222$779
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255301,10 +254817,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3237$811_Y
+    connect \Y $eq$ls180.v:3222$779_Y
   end
-  attribute \src "ls180.v:3238.110-3238.158"
-  cell $eq $eq$ls180.v:3238$815
+  attribute \src "ls180.v:3223.110-3223.158"
+  cell $eq $eq$ls180.v:3223$783
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -255312,21 +254828,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3238$815_Y
+    connect \Y $eq$ls180.v:3223$783_Y
   end
-  attribute \src "ls180.v:3243.36-3243.85"
-  cell $eq $eq$ls180.v:3243$817
+  attribute \src "ls180.v:3228.36-3228.85"
+  cell $eq $eq$ls180.v:3228$785
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface3_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface3_bank_bus_adr [13:9]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3243$817_Y
+    connect \Y $eq$ls180.v:3228$785_Y
   end
-  attribute \src "ls180.v:3245.105-3245.151"
-  cell $eq $eq$ls180.v:3245$819
+  attribute \src "ls180.v:3230.105-3230.151"
+  cell $eq $eq$ls180.v:3230$787
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -255334,10 +254850,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_adr [0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3245$819_Y
+    connect \Y $eq$ls180.v:3230$787_Y
   end
-  attribute \src "ls180.v:3246.108-3246.154"
-  cell $eq $eq$ls180.v:3246$823
+  attribute \src "ls180.v:3231.108-3231.154"
+  cell $eq $eq$ls180.v:3231$791
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -255345,10 +254861,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_adr [0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3246$823_Y
+    connect \Y $eq$ls180.v:3231$791_Y
   end
-  attribute \src "ls180.v:3248.104-3248.150"
-  cell $eq $eq$ls180.v:3248$826
+  attribute \src "ls180.v:3233.104-3233.150"
+  cell $eq $eq$ls180.v:3233$794
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -255356,10 +254872,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_adr [0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3248$826_Y
+    connect \Y $eq$ls180.v:3233$794_Y
   end
-  attribute \src "ls180.v:3249.107-3249.153"
-  cell $eq $eq$ls180.v:3249$830
+  attribute \src "ls180.v:3234.107-3234.153"
+  cell $eq $eq$ls180.v:3234$798
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -255367,21 +254883,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_adr [0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3249$830_Y
+    connect \Y $eq$ls180.v:3234$798_Y
   end
-  attribute \src "ls180.v:3257.36-3257.85"
-  cell $eq $eq$ls180.v:3257$832
+  attribute \src "ls180.v:3242.36-3242.85"
+  cell $eq $eq$ls180.v:3242$800
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface4_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface4_bank_bus_adr [13:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3257$832_Y
+    connect \Y $eq$ls180.v:3242$800_Y
   end
-  attribute \src "ls180.v:3259.116-3259.164"
-  cell $eq $eq$ls180.v:3259$834
+  attribute \src "ls180.v:3244.116-3244.164"
+  cell $eq $eq$ls180.v:3244$802
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255389,10 +254905,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3259$834_Y
+    connect \Y $eq$ls180.v:3244$802_Y
   end
-  attribute \src "ls180.v:3260.119-3260.167"
-  cell $eq $eq$ls180.v:3260$838
+  attribute \src "ls180.v:3245.119-3245.167"
+  cell $eq $eq$ls180.v:3245$806
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255400,10 +254916,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3260$838_Y
+    connect \Y $eq$ls180.v:3245$806_Y
   end
-  attribute \src "ls180.v:3262.120-3262.168"
-  cell $eq $eq$ls180.v:3262$841
+  attribute \src "ls180.v:3247.120-3247.168"
+  cell $eq $eq$ls180.v:3247$809
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255411,10 +254927,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3262$841_Y
+    connect \Y $eq$ls180.v:3247$809_Y
   end
-  attribute \src "ls180.v:3263.123-3263.171"
-  cell $eq $eq$ls180.v:3263$845
+  attribute \src "ls180.v:3248.123-3248.171"
+  cell $eq $eq$ls180.v:3248$813
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255422,10 +254938,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3263$845_Y
+    connect \Y $eq$ls180.v:3248$813_Y
   end
-  attribute \src "ls180.v:3265.101-3265.149"
-  cell $eq $eq$ls180.v:3265$848
+  attribute \src "ls180.v:3250.101-3250.149"
+  cell $eq $eq$ls180.v:3250$816
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255433,10 +254949,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3265$848_Y
+    connect \Y $eq$ls180.v:3250$816_Y
   end
-  attribute \src "ls180.v:3266.104-3266.152"
-  cell $eq $eq$ls180.v:3266$852
+  attribute \src "ls180.v:3251.104-3251.152"
+  cell $eq $eq$ls180.v:3251$820
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255444,10 +254960,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3266$852_Y
+    connect \Y $eq$ls180.v:3251$820_Y
   end
-  attribute \src "ls180.v:3268.120-3268.168"
-  cell $eq $eq$ls180.v:3268$855
+  attribute \src "ls180.v:3253.120-3253.168"
+  cell $eq $eq$ls180.v:3253$823
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255455,10 +254971,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3268$855_Y
+    connect \Y $eq$ls180.v:3253$823_Y
   end
-  attribute \src "ls180.v:3269.123-3269.171"
-  cell $eq $eq$ls180.v:3269$859
+  attribute \src "ls180.v:3254.123-3254.171"
+  cell $eq $eq$ls180.v:3254$827
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255466,10 +254982,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3269$859_Y
+    connect \Y $eq$ls180.v:3254$827_Y
   end
-  attribute \src "ls180.v:3271.120-3271.168"
-  cell $eq $eq$ls180.v:3271$862
+  attribute \src "ls180.v:3256.120-3256.168"
+  cell $eq $eq$ls180.v:3256$830
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255477,10 +254993,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3271$862_Y
+    connect \Y $eq$ls180.v:3256$830_Y
   end
-  attribute \src "ls180.v:3272.123-3272.171"
-  cell $eq $eq$ls180.v:3272$866
+  attribute \src "ls180.v:3257.123-3257.171"
+  cell $eq $eq$ls180.v:3257$834
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255488,10 +255004,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3272$866_Y
+    connect \Y $eq$ls180.v:3257$834_Y
   end
-  attribute \src "ls180.v:3274.121-3274.169"
-  cell $eq $eq$ls180.v:3274$869
+  attribute \src "ls180.v:3259.121-3259.169"
+  cell $eq $eq$ls180.v:3259$837
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255499,10 +255015,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3274$869_Y
+    connect \Y $eq$ls180.v:3259$837_Y
   end
-  attribute \src "ls180.v:3275.124-3275.172"
-  cell $eq $eq$ls180.v:3275$873
+  attribute \src "ls180.v:3260.124-3260.172"
+  cell $eq $eq$ls180.v:3260$841
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255510,10 +255026,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3275$873_Y
+    connect \Y $eq$ls180.v:3260$841_Y
   end
-  attribute \src "ls180.v:3277.119-3277.167"
-  cell $eq $eq$ls180.v:3277$876
+  attribute \src "ls180.v:3262.119-3262.167"
+  cell $eq $eq$ls180.v:3262$844
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255521,10 +255037,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3277$876_Y
+    connect \Y $eq$ls180.v:3262$844_Y
   end
-  attribute \src "ls180.v:3278.122-3278.170"
-  cell $eq $eq$ls180.v:3278$880
+  attribute \src "ls180.v:3263.122-3263.170"
+  cell $eq $eq$ls180.v:3263$848
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255532,10 +255048,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3278$880_Y
+    connect \Y $eq$ls180.v:3263$848_Y
   end
-  attribute \src "ls180.v:3280.119-3280.167"
-  cell $eq $eq$ls180.v:3280$883
+  attribute \src "ls180.v:3265.119-3265.167"
+  cell $eq $eq$ls180.v:3265$851
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255543,10 +255059,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3280$883_Y
+    connect \Y $eq$ls180.v:3265$851_Y
   end
-  attribute \src "ls180.v:3281.122-3281.170"
-  cell $eq $eq$ls180.v:3281$887
+  attribute \src "ls180.v:3266.122-3266.170"
+  cell $eq $eq$ls180.v:3266$855
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255554,10 +255070,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3281$887_Y
+    connect \Y $eq$ls180.v:3266$855_Y
   end
-  attribute \src "ls180.v:3283.119-3283.167"
-  cell $eq $eq$ls180.v:3283$890
+  attribute \src "ls180.v:3268.119-3268.167"
+  cell $eq $eq$ls180.v:3268$858
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255565,10 +255081,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3283$890_Y
+    connect \Y $eq$ls180.v:3268$858_Y
   end
-  attribute \src "ls180.v:3284.122-3284.170"
-  cell $eq $eq$ls180.v:3284$894
+  attribute \src "ls180.v:3269.122-3269.170"
+  cell $eq $eq$ls180.v:3269$862
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255576,10 +255092,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3284$894_Y
+    connect \Y $eq$ls180.v:3269$862_Y
   end
-  attribute \src "ls180.v:3286.119-3286.167"
-  cell $eq $eq$ls180.v:3286$897
+  attribute \src "ls180.v:3271.119-3271.167"
+  cell $eq $eq$ls180.v:3271$865
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255587,10 +255103,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:3286$897_Y
+    connect \Y $eq$ls180.v:3271$865_Y
   end
-  attribute \src "ls180.v:3287.122-3287.170"
-  cell $eq $eq$ls180.v:3287$901
+  attribute \src "ls180.v:3272.122-3272.170"
+  cell $eq $eq$ls180.v:3272$869
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -255598,21 +255114,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_adr [3:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:3287$901_Y
+    connect \Y $eq$ls180.v:3272$869_Y
   end
-  attribute \src "ls180.v:3302.36-3302.85"
-  cell $eq $eq$ls180.v:3302$903
+  attribute \src "ls180.v:3287.36-3287.85"
+  cell $eq $eq$ls180.v:3287$871
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface5_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface5_bank_bus_adr [13:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3302$903_Y
+    connect \Y $eq$ls180.v:3287$871_Y
   end
-  attribute \src "ls180.v:3304.108-3304.156"
-  cell $eq $eq$ls180.v:3304$905
+  attribute \src "ls180.v:3289.108-3289.156"
+  cell $eq $eq$ls180.v:3289$873
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255620,10 +255136,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3304$905_Y
+    connect \Y $eq$ls180.v:3289$873_Y
   end
-  attribute \src "ls180.v:3305.111-3305.159"
-  cell $eq $eq$ls180.v:3305$909
+  attribute \src "ls180.v:3290.111-3290.159"
+  cell $eq $eq$ls180.v:3290$877
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255631,10 +255147,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3305$909_Y
+    connect \Y $eq$ls180.v:3290$877_Y
   end
-  attribute \src "ls180.v:3307.108-3307.156"
-  cell $eq $eq$ls180.v:3307$912
+  attribute \src "ls180.v:3292.108-3292.156"
+  cell $eq $eq$ls180.v:3292$880
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255642,10 +255158,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3307$912_Y
+    connect \Y $eq$ls180.v:3292$880_Y
   end
-  attribute \src "ls180.v:3308.111-3308.159"
-  cell $eq $eq$ls180.v:3308$916
+  attribute \src "ls180.v:3293.111-3293.159"
+  cell $eq $eq$ls180.v:3293$884
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255653,10 +255169,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3308$916_Y
+    connect \Y $eq$ls180.v:3293$884_Y
   end
-  attribute \src "ls180.v:3310.108-3310.156"
-  cell $eq $eq$ls180.v:3310$919
+  attribute \src "ls180.v:3295.108-3295.156"
+  cell $eq $eq$ls180.v:3295$887
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255664,10 +255180,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3310$919_Y
+    connect \Y $eq$ls180.v:3295$887_Y
   end
-  attribute \src "ls180.v:3311.111-3311.159"
-  cell $eq $eq$ls180.v:3311$923
+  attribute \src "ls180.v:3296.111-3296.159"
+  cell $eq $eq$ls180.v:3296$891
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255675,10 +255191,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3311$923_Y
+    connect \Y $eq$ls180.v:3296$891_Y
   end
-  attribute \src "ls180.v:3313.108-3313.156"
-  cell $eq $eq$ls180.v:3313$926
+  attribute \src "ls180.v:3298.108-3298.156"
+  cell $eq $eq$ls180.v:3298$894
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255686,10 +255202,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3313$926_Y
+    connect \Y $eq$ls180.v:3298$894_Y
   end
-  attribute \src "ls180.v:3314.111-3314.159"
-  cell $eq $eq$ls180.v:3314$930
+  attribute \src "ls180.v:3299.111-3299.159"
+  cell $eq $eq$ls180.v:3299$898
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255697,10 +255213,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3314$930_Y
+    connect \Y $eq$ls180.v:3299$898_Y
   end
-  attribute \src "ls180.v:3316.110-3316.158"
-  cell $eq $eq$ls180.v:3316$933
+  attribute \src "ls180.v:3301.110-3301.158"
+  cell $eq $eq$ls180.v:3301$901
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255708,10 +255224,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3316$933_Y
+    connect \Y $eq$ls180.v:3301$901_Y
   end
-  attribute \src "ls180.v:3317.113-3317.161"
-  cell $eq $eq$ls180.v:3317$937
+  attribute \src "ls180.v:3302.113-3302.161"
+  cell $eq $eq$ls180.v:3302$905
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255719,10 +255235,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3317$937_Y
+    connect \Y $eq$ls180.v:3302$905_Y
   end
-  attribute \src "ls180.v:3319.110-3319.158"
-  cell $eq $eq$ls180.v:3319$940
+  attribute \src "ls180.v:3304.110-3304.158"
+  cell $eq $eq$ls180.v:3304$908
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255730,10 +255246,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3319$940_Y
+    connect \Y $eq$ls180.v:3304$908_Y
   end
-  attribute \src "ls180.v:3320.113-3320.161"
-  cell $eq $eq$ls180.v:3320$944
+  attribute \src "ls180.v:3305.113-3305.161"
+  cell $eq $eq$ls180.v:3305$912
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255741,10 +255257,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3320$944_Y
+    connect \Y $eq$ls180.v:3305$912_Y
   end
-  attribute \src "ls180.v:3322.110-3322.158"
-  cell $eq $eq$ls180.v:3322$947
+  attribute \src "ls180.v:3307.110-3307.158"
+  cell $eq $eq$ls180.v:3307$915
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255752,10 +255268,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3322$947_Y
+    connect \Y $eq$ls180.v:3307$915_Y
   end
-  attribute \src "ls180.v:3323.113-3323.161"
-  cell $eq $eq$ls180.v:3323$951
+  attribute \src "ls180.v:3308.113-3308.161"
+  cell $eq $eq$ls180.v:3308$919
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255763,10 +255279,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3323$951_Y
+    connect \Y $eq$ls180.v:3308$919_Y
   end
-  attribute \src "ls180.v:3325.110-3325.158"
-  cell $eq $eq$ls180.v:3325$954
+  attribute \src "ls180.v:3310.110-3310.158"
+  cell $eq $eq$ls180.v:3310$922
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255774,10 +255290,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3325$954_Y
+    connect \Y $eq$ls180.v:3310$922_Y
   end
-  attribute \src "ls180.v:3326.113-3326.161"
-  cell $eq $eq$ls180.v:3326$958
+  attribute \src "ls180.v:3311.113-3311.161"
+  cell $eq $eq$ls180.v:3311$926
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255785,10 +255301,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3326$958_Y
+    connect \Y $eq$ls180.v:3311$926_Y
   end
-  attribute \src "ls180.v:3328.106-3328.154"
-  cell $eq $eq$ls180.v:3328$961
+  attribute \src "ls180.v:3313.106-3313.154"
+  cell $eq $eq$ls180.v:3313$929
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255796,10 +255312,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3328$961_Y
+    connect \Y $eq$ls180.v:3313$929_Y
   end
-  attribute \src "ls180.v:3329.109-3329.157"
-  cell $eq $eq$ls180.v:3329$965
+  attribute \src "ls180.v:3314.109-3314.157"
+  cell $eq $eq$ls180.v:3314$933
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255807,10 +255323,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1000
-    connect \Y $eq$ls180.v:3329$965_Y
+    connect \Y $eq$ls180.v:3314$933_Y
   end
-  attribute \src "ls180.v:3331.116-3331.164"
-  cell $eq $eq$ls180.v:3331$968
+  attribute \src "ls180.v:3316.116-3316.164"
+  cell $eq $eq$ls180.v:3316$936
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255818,10 +255334,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:3331$968_Y
+    connect \Y $eq$ls180.v:3316$936_Y
   end
-  attribute \src "ls180.v:3332.119-3332.167"
-  cell $eq $eq$ls180.v:3332$972
+  attribute \src "ls180.v:3317.119-3317.167"
+  cell $eq $eq$ls180.v:3317$940
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255829,10 +255345,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1001
-    connect \Y $eq$ls180.v:3332$972_Y
+    connect \Y $eq$ls180.v:3317$940_Y
   end
-  attribute \src "ls180.v:3334.109-3334.158"
-  cell $eq $eq$ls180.v:3334$975
+  attribute \src "ls180.v:3319.109-3319.158"
+  cell $eq $eq$ls180.v:3319$943
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255840,10 +255356,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:3334$975_Y
+    connect \Y $eq$ls180.v:3319$943_Y
   end
-  attribute \src "ls180.v:3335.112-3335.161"
-  cell $eq $eq$ls180.v:3335$979
+  attribute \src "ls180.v:3320.112-3320.161"
+  cell $eq $eq$ls180.v:3320$947
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255851,10 +255367,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1010
-    connect \Y $eq$ls180.v:3335$979_Y
+    connect \Y $eq$ls180.v:3320$947_Y
   end
-  attribute \src "ls180.v:3337.109-3337.158"
-  cell $eq $eq$ls180.v:3337$982
+  attribute \src "ls180.v:3322.109-3322.158"
+  cell $eq $eq$ls180.v:3322$950
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255862,10 +255378,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:3337$982_Y
+    connect \Y $eq$ls180.v:3322$950_Y
   end
-  attribute \src "ls180.v:3338.112-3338.161"
-  cell $eq $eq$ls180.v:3338$986
+  attribute \src "ls180.v:3323.112-3323.161"
+  cell $eq $eq$ls180.v:3323$954
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255873,10 +255389,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1011
-    connect \Y $eq$ls180.v:3338$986_Y
+    connect \Y $eq$ls180.v:3323$954_Y
   end
-  attribute \src "ls180.v:3340.109-3340.158"
-  cell $eq $eq$ls180.v:3340$989
+  attribute \src "ls180.v:3325.109-3325.158"
+  cell $eq $eq$ls180.v:3325$957
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255884,10 +255400,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:3340$989_Y
+    connect \Y $eq$ls180.v:3325$957_Y
   end
-  attribute \src "ls180.v:3341.112-3341.161"
-  cell $eq $eq$ls180.v:3341$993
+  attribute \src "ls180.v:3326.112-3326.161"
+  cell $eq $eq$ls180.v:3326$961
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255895,10 +255411,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1100
-    connect \Y $eq$ls180.v:3341$993_Y
+    connect \Y $eq$ls180.v:3326$961_Y
   end
-  attribute \src "ls180.v:3343.109-3343.158"
-  cell $eq $eq$ls180.v:3343$996
+  attribute \src "ls180.v:3328.109-3328.158"
+  cell $eq $eq$ls180.v:3328$964
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255906,10 +255422,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:3343$996_Y
+    connect \Y $eq$ls180.v:3328$964_Y
   end
-  attribute \src "ls180.v:3344.112-3344.161"
-  cell $eq $eq$ls180.v:3344$1000
+  attribute \src "ls180.v:3329.112-3329.161"
+  cell $eq $eq$ls180.v:3329$968
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255917,10 +255433,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1101
-    connect \Y $eq$ls180.v:3344$1000_Y
+    connect \Y $eq$ls180.v:3329$968_Y
   end
-  attribute \src "ls180.v:3346.113-3346.162"
-  cell $eq $eq$ls180.v:3346$1003
+  attribute \src "ls180.v:3331.113-3331.162"
+  cell $eq $eq$ls180.v:3331$971
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255928,10 +255444,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:3346$1003_Y
+    connect \Y $eq$ls180.v:3331$971_Y
   end
-  attribute \src "ls180.v:3347.116-3347.165"
-  cell $eq $eq$ls180.v:3347$1007
+  attribute \src "ls180.v:3332.116-3332.165"
+  cell $eq $eq$ls180.v:3332$975
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255939,10 +255455,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1110
-    connect \Y $eq$ls180.v:3347$1007_Y
+    connect \Y $eq$ls180.v:3332$975_Y
   end
-  attribute \src "ls180.v:3349.114-3349.163"
-  cell $eq $eq$ls180.v:3349$1010
+  attribute \src "ls180.v:3334.114-3334.163"
+  cell $eq $eq$ls180.v:3334$978
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255950,10 +255466,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:3349$1010_Y
+    connect \Y $eq$ls180.v:3334$978_Y
   end
-  attribute \src "ls180.v:3350.117-3350.166"
-  cell $eq $eq$ls180.v:3350$1014
+  attribute \src "ls180.v:3335.117-3335.166"
+  cell $eq $eq$ls180.v:3335$982
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255961,10 +255477,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 4'1111
-    connect \Y $eq$ls180.v:3350$1014_Y
+    connect \Y $eq$ls180.v:3335$982_Y
   end
-  attribute \src "ls180.v:3352.113-3352.162"
-  cell $eq $eq$ls180.v:3352$1017
+  attribute \src "ls180.v:3337.113-3337.162"
+  cell $eq $eq$ls180.v:3337$985
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255972,10 +255488,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:3352$1017_Y
+    connect \Y $eq$ls180.v:3337$985_Y
   end
-  attribute \src "ls180.v:3353.116-3353.165"
-  cell $eq $eq$ls180.v:3353$1021
+  attribute \src "ls180.v:3338.116-3338.165"
+  cell $eq $eq$ls180.v:3338$989
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -255983,21 +255499,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_adr [4:0]
     connect \B 5'10000
-    connect \Y $eq$ls180.v:3353$1021_Y
+    connect \Y $eq$ls180.v:3338$989_Y
   end
-  attribute \src "ls180.v:3370.36-3370.85"
-  cell $eq $eq$ls180.v:3370$1023
+  attribute \src "ls180.v:3355.36-3355.85"
+  cell $eq $eq$ls180.v:3355$991
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface6_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface6_bank_bus_adr [13:9]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3370$1023_Y
+    connect \Y $eq$ls180.v:3355$991_Y
   end
-  attribute \src "ls180.v:3372.86-3372.134"
-  cell $eq $eq$ls180.v:3372$1025
+  attribute \src "ls180.v:3357.86-3357.134"
+  cell $eq $eq$ls180.v:3357$993
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256005,10 +255521,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3372$1025_Y
+    connect \Y $eq$ls180.v:3357$993_Y
   end
-  attribute \src "ls180.v:3373.89-3373.137"
-  cell $eq $eq$ls180.v:3373$1029
+  attribute \src "ls180.v:3358.89-3358.137"
+  cell $eq $eq$ls180.v:3358$997
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256016,10 +255532,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3373$1029_Y
+    connect \Y $eq$ls180.v:3358$997_Y
   end
-  attribute \src "ls180.v:3375.109-3375.157"
-  cell $eq $eq$ls180.v:3375$1032
+  attribute \src "ls180.v:3360.109-3360.157"
+  cell $eq $eq$ls180.v:3360$1000
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256027,10 +255543,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3375$1032_Y
+    connect \Y $eq$ls180.v:3360$1000_Y
   end
-  attribute \src "ls180.v:3376.112-3376.160"
-  cell $eq $eq$ls180.v:3376$1036
+  attribute \src "ls180.v:3361.112-3361.160"
+  cell $eq $eq$ls180.v:3361$1004
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256038,10 +255554,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3376$1036_Y
+    connect \Y $eq$ls180.v:3361$1004_Y
   end
-  attribute \src "ls180.v:3378.110-3378.158"
-  cell $eq $eq$ls180.v:3378$1039
+  attribute \src "ls180.v:3363.110-3363.158"
+  cell $eq $eq$ls180.v:3363$1007
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256049,10 +255565,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3378$1039_Y
+    connect \Y $eq$ls180.v:3363$1007_Y
   end
-  attribute \src "ls180.v:3379.113-3379.161"
-  cell $eq $eq$ls180.v:3379$1043
+  attribute \src "ls180.v:3364.113-3364.161"
+  cell $eq $eq$ls180.v:3364$1011
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256060,10 +255576,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3379$1043_Y
+    connect \Y $eq$ls180.v:3364$1011_Y
   end
-  attribute \src "ls180.v:3381.101-3381.149"
-  cell $eq $eq$ls180.v:3381$1046
+  attribute \src "ls180.v:3366.101-3366.149"
+  cell $eq $eq$ls180.v:3366$1014
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256071,10 +255587,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3381$1046_Y
+    connect \Y $eq$ls180.v:3366$1014_Y
   end
-  attribute \src "ls180.v:3382.104-3382.152"
-  cell $eq $eq$ls180.v:3382$1050
+  attribute \src "ls180.v:3367.104-3367.152"
+  cell $eq $eq$ls180.v:3367$1018
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256082,10 +255598,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3382$1050_Y
+    connect \Y $eq$ls180.v:3367$1018_Y
   end
-  attribute \src "ls180.v:3384.102-3384.150"
-  cell $eq $eq$ls180.v:3384$1053
+  attribute \src "ls180.v:3369.102-3369.150"
+  cell $eq $eq$ls180.v:3369$1021
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256093,10 +255609,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3384$1053_Y
+    connect \Y $eq$ls180.v:3369$1021_Y
   end
-  attribute \src "ls180.v:3385.105-3385.153"
-  cell $eq $eq$ls180.v:3385$1057
+  attribute \src "ls180.v:3370.105-3370.153"
+  cell $eq $eq$ls180.v:3370$1025
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256104,10 +255620,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3385$1057_Y
+    connect \Y $eq$ls180.v:3370$1025_Y
   end
-  attribute \src "ls180.v:3387.113-3387.161"
-  cell $eq $eq$ls180.v:3387$1060
+  attribute \src "ls180.v:3372.113-3372.161"
+  cell $eq $eq$ls180.v:3372$1028
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256115,10 +255631,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3387$1060_Y
+    connect \Y $eq$ls180.v:3372$1028_Y
   end
-  attribute \src "ls180.v:3388.116-3388.164"
-  cell $eq $eq$ls180.v:3388$1064
+  attribute \src "ls180.v:3373.116-3373.164"
+  cell $eq $eq$ls180.v:3373$1032
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256126,10 +255642,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'101
-    connect \Y $eq$ls180.v:3388$1064_Y
+    connect \Y $eq$ls180.v:3373$1032_Y
   end
-  attribute \src "ls180.v:3390.110-3390.158"
-  cell $eq $eq$ls180.v:3390$1067
+  attribute \src "ls180.v:3375.110-3375.158"
+  cell $eq $eq$ls180.v:3375$1035
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256137,10 +255653,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3390$1067_Y
+    connect \Y $eq$ls180.v:3375$1035_Y
   end
-  attribute \src "ls180.v:3391.113-3391.161"
-  cell $eq $eq$ls180.v:3391$1071
+  attribute \src "ls180.v:3376.113-3376.161"
+  cell $eq $eq$ls180.v:3376$1039
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256148,10 +255664,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'110
-    connect \Y $eq$ls180.v:3391$1071_Y
+    connect \Y $eq$ls180.v:3376$1039_Y
   end
-  attribute \src "ls180.v:3393.109-3393.157"
-  cell $eq $eq$ls180.v:3393$1074
+  attribute \src "ls180.v:3378.109-3378.157"
+  cell $eq $eq$ls180.v:3378$1042
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256159,10 +255675,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3393$1074_Y
+    connect \Y $eq$ls180.v:3378$1042_Y
   end
-  attribute \src "ls180.v:3394.112-3394.160"
-  cell $eq $eq$ls180.v:3394$1078
+  attribute \src "ls180.v:3379.112-3379.160"
+  cell $eq $eq$ls180.v:3379$1046
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256170,21 +255686,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_adr [2:0]
     connect \B 3'111
-    connect \Y $eq$ls180.v:3394$1078_Y
+    connect \Y $eq$ls180.v:3379$1046_Y
   end
-  attribute \src "ls180.v:3404.36-3404.85"
-  cell $eq $eq$ls180.v:3404$1080
+  attribute \src "ls180.v:3389.36-3389.85"
+  cell $eq $eq$ls180.v:3389$1048
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
+    parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_interface7_bank_bus_adr [13:8]
+    connect \A \libresocsim_interface7_bank_bus_adr [13:9]
     connect \B 3'100
-    connect \Y $eq$ls180.v:3404$1080_Y
+    connect \Y $eq$ls180.v:3389$1048_Y
   end
-  attribute \src "ls180.v:3406.115-3406.163"
-  cell $eq $eq$ls180.v:3406$1082
+  attribute \src "ls180.v:3391.115-3391.163"
+  cell $eq $eq$ls180.v:3391$1050
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256192,10 +255708,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3406$1082_Y
+    connect \Y $eq$ls180.v:3391$1050_Y
   end
-  attribute \src "ls180.v:3407.118-3407.166"
-  cell $eq $eq$ls180.v:3407$1086
+  attribute \src "ls180.v:3392.118-3392.166"
+  cell $eq $eq$ls180.v:3392$1054
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256203,10 +255719,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3407$1086_Y
+    connect \Y $eq$ls180.v:3392$1054_Y
   end
-  attribute \src "ls180.v:3409.115-3409.163"
-  cell $eq $eq$ls180.v:3409$1089
+  attribute \src "ls180.v:3394.115-3394.163"
+  cell $eq $eq$ls180.v:3394$1057
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256214,10 +255730,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3409$1089_Y
+    connect \Y $eq$ls180.v:3394$1057_Y
   end
-  attribute \src "ls180.v:3410.118-3410.166"
-  cell $eq $eq$ls180.v:3410$1093
+  attribute \src "ls180.v:3395.118-3395.166"
+  cell $eq $eq$ls180.v:3395$1061
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256225,10 +255741,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3410$1093_Y
+    connect \Y $eq$ls180.v:3395$1061_Y
   end
-  attribute \src "ls180.v:3412.115-3412.163"
-  cell $eq $eq$ls180.v:3412$1096
+  attribute \src "ls180.v:3397.115-3397.163"
+  cell $eq $eq$ls180.v:3397$1064
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256236,10 +255752,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3412$1096_Y
+    connect \Y $eq$ls180.v:3397$1064_Y
   end
-  attribute \src "ls180.v:3413.118-3413.166"
-  cell $eq $eq$ls180.v:3413$1100
+  attribute \src "ls180.v:3398.118-3398.166"
+  cell $eq $eq$ls180.v:3398$1068
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256247,10 +255763,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3413$1100_Y
+    connect \Y $eq$ls180.v:3398$1068_Y
   end
-  attribute \src "ls180.v:3415.115-3415.163"
-  cell $eq $eq$ls180.v:3415$1103
+  attribute \src "ls180.v:3400.115-3400.163"
+  cell $eq $eq$ls180.v:3400$1071
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256258,10 +255774,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3415$1103_Y
+    connect \Y $eq$ls180.v:3400$1071_Y
   end
-  attribute \src "ls180.v:3416.118-3416.166"
-  cell $eq $eq$ls180.v:3416$1107
+  attribute \src "ls180.v:3401.118-3401.166"
+  cell $eq $eq$ls180.v:3401$1075
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256269,10 +255785,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_adr [1:0]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3416$1107_Y
+    connect \Y $eq$ls180.v:3401$1075_Y
   end
-  attribute \src "ls180.v:3776.28-3776.63"
-  cell $eq $eq$ls180.v:3776$1137
+  attribute \src "ls180.v:3761.28-3761.63"
+  cell $eq $eq$ls180.v:3761$1105
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256280,10 +255796,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'0
-    connect \Y $eq$ls180.v:3776$1137_Y
+    connect \Y $eq$ls180.v:3761$1105_Y
   end
-  attribute \src "ls180.v:3776.126-3776.164"
-  cell $eq $eq$ls180.v:3776$1138
+  attribute \src "ls180.v:3761.126-3761.164"
+  cell $eq $eq$ls180.v:3761$1106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256291,10 +255807,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3776$1138_Y
+    connect \Y $eq$ls180.v:3761$1106_Y
   end
-  attribute \src "ls180.v:3776.201-3776.239"
-  cell $eq $eq$ls180.v:3776$1141
+  attribute \src "ls180.v:3761.201-3761.239"
+  cell $eq $eq$ls180.v:3761$1109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256302,10 +255818,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3776$1141_Y
+    connect \Y $eq$ls180.v:3761$1109_Y
   end
-  attribute \src "ls180.v:3776.276-3776.314"
-  cell $eq $eq$ls180.v:3776$1144
+  attribute \src "ls180.v:3761.276-3761.314"
+  cell $eq $eq$ls180.v:3761$1112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256313,10 +255829,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3776$1144_Y
+    connect \Y $eq$ls180.v:3761$1112_Y
   end
-  attribute \src "ls180.v:3800.28-3800.63"
-  cell $eq $eq$ls180.v:3800$1153
+  attribute \src "ls180.v:3785.28-3785.63"
+  cell $eq $eq$ls180.v:3785$1121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256324,10 +255840,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 1'1
-    connect \Y $eq$ls180.v:3800$1153_Y
+    connect \Y $eq$ls180.v:3785$1121_Y
   end
-  attribute \src "ls180.v:3800.126-3800.164"
-  cell $eq $eq$ls180.v:3800$1154
+  attribute \src "ls180.v:3785.126-3785.164"
+  cell $eq $eq$ls180.v:3785$1122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256335,10 +255851,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3800$1154_Y
+    connect \Y $eq$ls180.v:3785$1122_Y
   end
-  attribute \src "ls180.v:3800.201-3800.239"
-  cell $eq $eq$ls180.v:3800$1157
+  attribute \src "ls180.v:3785.201-3785.239"
+  cell $eq $eq$ls180.v:3785$1125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256346,10 +255862,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3800$1157_Y
+    connect \Y $eq$ls180.v:3785$1125_Y
   end
-  attribute \src "ls180.v:3800.276-3800.314"
-  cell $eq $eq$ls180.v:3800$1160
+  attribute \src "ls180.v:3785.276-3785.314"
+  cell $eq $eq$ls180.v:3785$1128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256357,10 +255873,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3800$1160_Y
+    connect \Y $eq$ls180.v:3785$1128_Y
   end
-  attribute \src "ls180.v:3824.28-3824.63"
-  cell $eq $eq$ls180.v:3824$1169
+  attribute \src "ls180.v:3809.28-3809.63"
+  cell $eq $eq$ls180.v:3809$1137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256368,10 +255884,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'10
-    connect \Y $eq$ls180.v:3824$1169_Y
+    connect \Y $eq$ls180.v:3809$1137_Y
   end
-  attribute \src "ls180.v:3824.126-3824.164"
-  cell $eq $eq$ls180.v:3824$1170
+  attribute \src "ls180.v:3809.126-3809.164"
+  cell $eq $eq$ls180.v:3809$1138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256379,10 +255895,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3824$1170_Y
+    connect \Y $eq$ls180.v:3809$1138_Y
   end
-  attribute \src "ls180.v:3824.201-3824.239"
-  cell $eq $eq$ls180.v:3824$1173
+  attribute \src "ls180.v:3809.201-3809.239"
+  cell $eq $eq$ls180.v:3809$1141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256390,10 +255906,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3824$1173_Y
+    connect \Y $eq$ls180.v:3809$1141_Y
   end
-  attribute \src "ls180.v:3824.276-3824.314"
-  cell $eq $eq$ls180.v:3824$1176
+  attribute \src "ls180.v:3809.276-3809.314"
+  cell $eq $eq$ls180.v:3809$1144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256401,10 +255917,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3824$1176_Y
+    connect \Y $eq$ls180.v:3809$1144_Y
   end
-  attribute \src "ls180.v:3848.28-3848.63"
-  cell $eq $eq$ls180.v:3848$1185
+  attribute \src "ls180.v:3833.28-3833.63"
+  cell $eq $eq$ls180.v:3833$1153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -256412,10 +255928,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_addr [10:9]
     connect \B 2'11
-    connect \Y $eq$ls180.v:3848$1185_Y
+    connect \Y $eq$ls180.v:3833$1153_Y
   end
-  attribute \src "ls180.v:3848.126-3848.164"
-  cell $eq $eq$ls180.v:3848$1186
+  attribute \src "ls180.v:3833.126-3833.164"
+  cell $eq $eq$ls180.v:3833$1154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256423,10 +255939,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3848$1186_Y
+    connect \Y $eq$ls180.v:3833$1154_Y
   end
-  attribute \src "ls180.v:3848.201-3848.239"
-  cell $eq $eq$ls180.v:3848$1189
+  attribute \src "ls180.v:3833.201-3833.239"
+  cell $eq $eq$ls180.v:3833$1157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256434,10 +255950,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3848$1189_Y
+    connect \Y $eq$ls180.v:3833$1157_Y
   end
-  attribute \src "ls180.v:3848.276-3848.314"
-  cell $eq $eq$ls180.v:3848$1192
+  attribute \src "ls180.v:3833.276-3833.314"
+  cell $eq $eq$ls180.v:3833$1160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256445,10 +255961,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:3848$1192_Y
+    connect \Y $eq$ls180.v:3833$1160_Y
   end
-  attribute \src "ls180.v:4380.8-4380.33"
-  cell $eq $eq$ls180.v:4380$1292
+  attribute \src "ls180.v:4365.8-4365.33"
+  cell $eq $eq$ls180.v:4365$1260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -256456,10 +255972,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_value
     connect \B 1'0
-    connect \Y $eq$ls180.v:4380$1292_Y
+    connect \Y $eq$ls180.v:4365$1260_Y
   end
-  attribute \src "ls180.v:4415.8-4415.37"
-  cell $eq $eq$ls180.v:4415$1303
+  attribute \src "ls180.v:4400.8-4400.37"
+  cell $eq $eq$ls180.v:4400$1271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256467,10 +255983,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_postponer_count
     connect \B 1'0
-    connect \Y $eq$ls180.v:4415$1303_Y
+    connect \Y $eq$ls180.v:4400$1271_Y
   end
-  attribute \src "ls180.v:4435.33-4435.64"
-  cell $eq $eq$ls180.v:4435$1306
+  attribute \src "ls180.v:4420.33-4420.64"
+  cell $eq $eq$ls180.v:4420$1274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256478,10 +255994,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $eq$ls180.v:4435$1306_Y
+    connect \Y $eq$ls180.v:4420$1274_Y
   end
-  attribute \src "ls180.v:4442.7-4442.38"
-  cell $eq $eq$ls180.v:4442$1308
+  attribute \src "ls180.v:4427.7-4427.38"
+  cell $eq $eq$ls180.v:4427$1276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256489,10 +256005,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_counter
     connect \B 2'10
-    connect \Y $eq$ls180.v:4442$1308_Y
+    connect \Y $eq$ls180.v:4427$1276_Y
   end
-  attribute \src "ls180.v:4449.7-4449.38"
-  cell $eq $eq$ls180.v:4449$1309
+  attribute \src "ls180.v:4434.7-4434.38"
+  cell $eq $eq$ls180.v:4434$1277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256500,10 +256016,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:4449$1309_Y
+    connect \Y $eq$ls180.v:4434$1277_Y
   end
-  attribute \src "ls180.v:4457.7-4457.38"
-  cell $eq $eq$ls180.v:4457$1310
+  attribute \src "ls180.v:4442.7-4442.38"
+  cell $eq $eq$ls180.v:4442$1278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256511,10 +256027,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_counter
     connect \B 4'1000
-    connect \Y $eq$ls180.v:4457$1310_Y
+    connect \Y $eq$ls180.v:4442$1278_Y
   end
-  attribute \src "ls180.v:4509.9-4509.49"
-  cell $eq $eq$ls180.v:4509$1328
+  attribute \src "ls180.v:4494.9-4494.49"
+  cell $eq $eq$ls180.v:4494$1296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256522,10 +256038,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4509$1328_Y
+    connect \Y $eq$ls180.v:4494$1296_Y
   end
-  attribute \src "ls180.v:4555.9-4555.49"
-  cell $eq $eq$ls180.v:4555$1344
+  attribute \src "ls180.v:4540.9-4540.49"
+  cell $eq $eq$ls180.v:4540$1312
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256533,10 +256049,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4555$1344_Y
+    connect \Y $eq$ls180.v:4540$1312_Y
   end
-  attribute \src "ls180.v:4601.9-4601.49"
-  cell $eq $eq$ls180.v:4601$1360
+  attribute \src "ls180.v:4586.9-4586.49"
+  cell $eq $eq$ls180.v:4586$1328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256544,10 +256060,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4601$1360_Y
+    connect \Y $eq$ls180.v:4586$1328_Y
   end
-  attribute \src "ls180.v:4647.9-4647.49"
-  cell $eq $eq$ls180.v:4647$1376
+  attribute \src "ls180.v:4632.9-4632.49"
+  cell $eq $eq$ls180.v:4632$1344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256555,10 +256071,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4647$1376_Y
+    connect \Y $eq$ls180.v:4632$1344_Y
   end
-  attribute \src "ls180.v:4797.9-4797.36"
-  cell $eq $eq$ls180.v:4797$1388
+  attribute \src "ls180.v:4782.9-4782.36"
+  cell $eq $eq$ls180.v:4782$1356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256566,10 +256082,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4797$1388_Y
+    connect \Y $eq$ls180.v:4782$1356_Y
   end
-  attribute \src "ls180.v:4812.9-4812.36"
-  cell $eq $eq$ls180.v:4812$1391
+  attribute \src "ls180.v:4797.9-4797.36"
+  cell $eq $eq$ls180.v:4797$1359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -256577,10 +256093,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $eq$ls180.v:4812$1391_Y
+    connect \Y $eq$ls180.v:4797$1359_Y
   end
-  attribute \src "ls180.v:4818.54-4818.92"
-  cell $eq $eq$ls180.v:4818$1392
+  attribute \src "ls180.v:4803.54-4803.92"
+  cell $eq $eq$ls180.v:4803$1360
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256588,10 +256104,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4818$1392_Y
+    connect \Y $eq$ls180.v:4803$1360_Y
   end
-  attribute \src "ls180.v:4818.136-4818.174"
-  cell $eq $eq$ls180.v:4818$1395
+  attribute \src "ls180.v:4803.136-4803.174"
+  cell $eq $eq$ls180.v:4803$1363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256599,10 +256115,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4818$1395_Y
+    connect \Y $eq$ls180.v:4803$1363_Y
   end
-  attribute \src "ls180.v:4818.218-4818.256"
-  cell $eq $eq$ls180.v:4818$1398
+  attribute \src "ls180.v:4803.218-4803.256"
+  cell $eq $eq$ls180.v:4803$1366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256610,10 +256126,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4818$1398_Y
+    connect \Y $eq$ls180.v:4803$1366_Y
   end
-  attribute \src "ls180.v:4818.300-4818.338"
-  cell $eq $eq$ls180.v:4818$1401
+  attribute \src "ls180.v:4803.300-4803.338"
+  cell $eq $eq$ls180.v:4803$1369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256621,10 +256137,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4818$1401_Y
+    connect \Y $eq$ls180.v:4803$1369_Y
   end
-  attribute \src "ls180.v:4819.55-4819.93"
-  cell $eq $eq$ls180.v:4819$1404
+  attribute \src "ls180.v:4804.55-4804.93"
+  cell $eq $eq$ls180.v:4804$1372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256632,10 +256148,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin0_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4819$1404_Y
+    connect \Y $eq$ls180.v:4804$1372_Y
   end
-  attribute \src "ls180.v:4819.137-4819.175"
-  cell $eq $eq$ls180.v:4819$1407
+  attribute \src "ls180.v:4804.137-4804.175"
+  cell $eq $eq$ls180.v:4804$1375
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256643,10 +256159,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin1_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4819$1407_Y
+    connect \Y $eq$ls180.v:4804$1375_Y
   end
-  attribute \src "ls180.v:4819.219-4819.257"
-  cell $eq $eq$ls180.v:4819$1410
+  attribute \src "ls180.v:4804.219-4804.257"
+  cell $eq $eq$ls180.v:4804$1378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256654,10 +256170,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin2_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4819$1410_Y
+    connect \Y $eq$ls180.v:4804$1378_Y
   end
-  attribute \src "ls180.v:4819.301-4819.339"
-  cell $eq $eq$ls180.v:4819$1413
+  attribute \src "ls180.v:4804.301-4804.339"
+  cell $eq $eq$ls180.v:4804$1381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256665,10 +256181,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \subfragments_roundrobin3_grant
     connect \B 1'0
-    connect \Y $eq$ls180.v:4819$1413_Y
+    connect \Y $eq$ls180.v:4804$1381_Y
   end
-  attribute \src "ls180.v:4854.9-4854.37"
-  cell $eq $eq$ls180.v:4854$1425
+  attribute \src "ls180.v:4839.9-4839.37"
+  cell $eq $eq$ls180.v:4839$1393
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256676,10 +256192,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \uart_phy_tx_bitcount
     connect \B 4'1000
-    connect \Y $eq$ls180.v:4854$1425_Y
+    connect \Y $eq$ls180.v:4839$1393_Y
   end
-  attribute \src "ls180.v:4857.10-4857.38"
-  cell $eq $eq$ls180.v:4857$1426
+  attribute \src "ls180.v:4842.10-4842.38"
+  cell $eq $eq$ls180.v:4842$1394
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256687,10 +256203,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \uart_phy_tx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:4857$1426_Y
+    connect \Y $eq$ls180.v:4842$1394_Y
   end
-  attribute \src "ls180.v:4883.9-4883.37"
-  cell $eq $eq$ls180.v:4883$1432
+  attribute \src "ls180.v:4868.9-4868.37"
+  cell $eq $eq$ls180.v:4868$1400
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256698,10 +256214,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \uart_phy_rx_bitcount
     connect \B 1'0
-    connect \Y $eq$ls180.v:4883$1432_Y
+    connect \Y $eq$ls180.v:4868$1400_Y
   end
-  attribute \src "ls180.v:4888.10-4888.38"
-  cell $eq $eq$ls180.v:4888$1433
+  attribute \src "ls180.v:4873.10-4873.38"
+  cell $eq $eq$ls180.v:4873$1401
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256709,36 +256225,36 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \uart_phy_rx_bitcount
     connect \B 4'1001
-    connect \Y $eq$ls180.v:4888$1433_Y
+    connect \Y $eq$ls180.v:4873$1401_Y
   end
-  attribute \src "ls180.v:5530.28-5530.31"
-  cell $memrd $memrd$\mem$ls180.v:5530$1515
-    parameter \ABITS 6
+  attribute \src "ls180.v:5507.28-5507.31"
+  cell $memrd $memrd$\mem$ls180.v:5507$1459
+    parameter \ABITS 7
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
     parameter \TRANSPARENT 0
-    parameter \WIDTH 64
+    parameter \WIDTH 32
     connect \ADDR \memadr
     connect \CLK 1'x
-    connect \DATA $memrd$\mem$ls180.v:5530$1515_DATA
+    connect \DATA $memrd$\mem$ls180.v:5507$1459_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5558.20-5558.25"
-  cell $memrd $memrd$\mem_1$ls180.v:5558$1565
-    parameter \ABITS 4
+  attribute \src "ls180.v:5527.20-5527.25"
+  cell $memrd $memrd$\mem_1$ls180.v:5527$1485
+    parameter \ABITS 5
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
     parameter \TRANSPARENT 0
-    parameter \WIDTH 64
+    parameter \WIDTH 32
     connect \ADDR \memadr_1
     connect \CLK 1'x
-    connect \DATA $memrd$\mem_1$ls180.v:5558$1565_DATA
+    connect \DATA $memrd$\mem_1$ls180.v:5527$1485_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5569.12-5569.19"
-  cell $memrd $memrd$\storage$ls180.v:5569$1573
+  attribute \src "ls180.v:5538.12-5538.19"
+  cell $memrd $memrd$\storage$ls180.v:5538$1493
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256747,11 +256263,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:5569$1573_DATA
+    connect \DATA $memrd$\storage$ls180.v:5538$1493_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5576.63-5576.70"
-  cell $memrd $memrd$\storage$ls180.v:5576$1575
+  attribute \src "ls180.v:5545.63-5545.70"
+  cell $memrd $memrd$\storage$ls180.v:5545$1495
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256760,11 +256276,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage$ls180.v:5576$1575_DATA
+    connect \DATA $memrd$\storage$ls180.v:5545$1495_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5583.14-5583.23"
-  cell $memrd $memrd$\storage_1$ls180.v:5583$1583
+  attribute \src "ls180.v:5552.14-5552.23"
+  cell $memrd $memrd$\storage_1$ls180.v:5552$1503
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256773,11 +256289,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:5583$1583_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:5552$1503_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5590.63-5590.72"
-  cell $memrd $memrd$\storage_1$ls180.v:5590$1585
+  attribute \src "ls180.v:5559.63-5559.72"
+  cell $memrd $memrd$\storage_1$ls180.v:5559$1505
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256786,11 +256302,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_1$ls180.v:5590$1585_DATA
+    connect \DATA $memrd$\storage_1$ls180.v:5559$1505_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5597.14-5597.23"
-  cell $memrd $memrd$\storage_2$ls180.v:5597$1593
+  attribute \src "ls180.v:5566.14-5566.23"
+  cell $memrd $memrd$\storage_2$ls180.v:5566$1513
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256799,11 +256315,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:5597$1593_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:5566$1513_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5604.63-5604.72"
-  cell $memrd $memrd$\storage_2$ls180.v:5604$1595
+  attribute \src "ls180.v:5573.63-5573.72"
+  cell $memrd $memrd$\storage_2$ls180.v:5573$1515
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256812,11 +256328,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_2$ls180.v:5604$1595_DATA
+    connect \DATA $memrd$\storage_2$ls180.v:5573$1515_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5611.14-5611.23"
-  cell $memrd $memrd$\storage_3$ls180.v:5611$1603
+  attribute \src "ls180.v:5580.14-5580.23"
+  cell $memrd $memrd$\storage_3$ls180.v:5580$1523
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256825,11 +256341,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:5611$1603_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:5580$1523_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5618.63-5618.72"
-  cell $memrd $memrd$\storage_3$ls180.v:5618$1605
+  attribute \src "ls180.v:5587.63-5587.72"
+  cell $memrd $memrd$\storage_3$ls180.v:5587$1525
     parameter \ABITS 3
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256838,11 +256354,11 @@ module \ls180
     parameter \WIDTH 25
     connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_3$ls180.v:5618$1605_DATA
+    connect \DATA $memrd$\storage_3$ls180.v:5587$1525_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5626.14-5626.23"
-  cell $memrd $memrd$\storage_4$ls180.v:5626$1613
+  attribute \src "ls180.v:5595.14-5595.23"
+  cell $memrd $memrd$\storage_4$ls180.v:5595$1533
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256851,11 +256367,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \tx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:5626$1613_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:5595$1533_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5631.15-5631.24"
-  cell $memrd $memrd$\storage_4$ls180.v:5631$1615
+  attribute \src "ls180.v:5600.15-5600.24"
+  cell $memrd $memrd$\storage_4$ls180.v:5600$1535
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256864,11 +256380,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \tx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_4$ls180.v:5631$1615_DATA
+    connect \DATA $memrd$\storage_4$ls180.v:5600$1535_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5643.14-5643.23"
-  cell $memrd $memrd$\storage_5$ls180.v:5643$1623
+  attribute \src "ls180.v:5612.14-5612.23"
+  cell $memrd $memrd$\storage_5$ls180.v:5612$1543
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256877,11 +256393,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \rx_fifo_wrport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:5643$1623_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:5612$1543_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:5648.15-5648.24"
-  cell $memrd $memrd$\storage_5$ls180.v:5648$1625
+  attribute \src "ls180.v:5617.15-5617.24"
+  cell $memrd $memrd$\storage_5$ls180.v:5617$1545
     parameter \ABITS 4
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
@@ -256890,11 +256406,11 @@ module \ls180
     parameter \WIDTH 10
     connect \ADDR \rx_fifo_rdport_adr
     connect \CLK 1'x
-    connect \DATA $memrd$\storage_5$ls180.v:5648$1625_DATA
+    connect \DATA $memrd$\storage_5$ls180.v:5617$1545_DATA
     connect \EN 1'x
   end
-  attribute \src "ls180.v:1722.36-1722.61"
-  cell $ne $ne$ls180.v:1722$83
+  attribute \src "ls180.v:1711.36-1711.61"
+  cell $ne $ne$ls180.v:1711$63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -256902,10 +256418,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_value
     connect \B 1'0
-    connect \Y $ne$ls180.v:1722$83_Y
+    connect \Y $ne$ls180.v:1711$63_Y
   end
-  attribute \src "ls180.v:1897.60-1897.89"
-  cell $ne $ne$ls180.v:1897$122
+  attribute \src "ls180.v:1882.60-1882.89"
+  cell $ne $ne$ls180.v:1882$90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -256913,10 +256429,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_count
     connect \B 1'0
-    connect \Y $ne$ls180.v:1897$122_Y
+    connect \Y $ne$ls180.v:1882$90_Y
   end
-  attribute \src "ls180.v:1958.8-1958.132"
-  cell $ne $ne$ls180.v:1958$141
+  attribute \src "ls180.v:1943.8-1943.132"
+  cell $ne $ne$ls180.v:1943$109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -256924,10 +256440,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:1958$141_Y
+    connect \Y $ne$ls180.v:1943$109_Y
   end
-  attribute \src "ls180.v:1990.70-1990.123"
-  cell $ne $ne$ls180.v:1990$148
+  attribute \src "ls180.v:1975.70-1975.123"
+  cell $ne $ne$ls180.v:1975$116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256935,10 +256451,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:1990$148_Y
+    connect \Y $ne$ls180.v:1975$116_Y
   end
-  attribute \src "ls180.v:1991.70-1991.123"
-  cell $ne $ne$ls180.v:1991$149
+  attribute \src "ls180.v:1976.70-1976.123"
+  cell $ne $ne$ls180.v:1976$117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256946,10 +256462,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:1991$149_Y
+    connect \Y $ne$ls180.v:1976$117_Y
   end
-  attribute \src "ls180.v:2115.8-2115.132"
-  cell $ne $ne$ls180.v:2115$171
+  attribute \src "ls180.v:2100.8-2100.132"
+  cell $ne $ne$ls180.v:2100$139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -256957,10 +256473,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:2115$171_Y
+    connect \Y $ne$ls180.v:2100$139_Y
   end
-  attribute \src "ls180.v:2147.70-2147.123"
-  cell $ne $ne$ls180.v:2147$178
+  attribute \src "ls180.v:2132.70-2132.123"
+  cell $ne $ne$ls180.v:2132$146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256968,10 +256484,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:2147$178_Y
+    connect \Y $ne$ls180.v:2132$146_Y
   end
-  attribute \src "ls180.v:2148.70-2148.123"
-  cell $ne $ne$ls180.v:2148$179
+  attribute \src "ls180.v:2133.70-2133.123"
+  cell $ne $ne$ls180.v:2133$147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -256979,10 +256495,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:2148$179_Y
+    connect \Y $ne$ls180.v:2133$147_Y
   end
-  attribute \src "ls180.v:2272.8-2272.132"
-  cell $ne $ne$ls180.v:2272$201
+  attribute \src "ls180.v:2257.8-2257.132"
+  cell $ne $ne$ls180.v:2257$169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -256990,10 +256506,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:2272$201_Y
+    connect \Y $ne$ls180.v:2257$169_Y
   end
-  attribute \src "ls180.v:2304.70-2304.123"
-  cell $ne $ne$ls180.v:2304$208
+  attribute \src "ls180.v:2289.70-2289.123"
+  cell $ne $ne$ls180.v:2289$176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257001,10 +256517,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:2304$208_Y
+    connect \Y $ne$ls180.v:2289$176_Y
   end
-  attribute \src "ls180.v:2305.70-2305.123"
-  cell $ne $ne$ls180.v:2305$209
+  attribute \src "ls180.v:2290.70-2290.123"
+  cell $ne $ne$ls180.v:2290$177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257012,10 +256528,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:2305$209_Y
+    connect \Y $ne$ls180.v:2290$177_Y
   end
-  attribute \src "ls180.v:2429.8-2429.132"
-  cell $ne $ne$ls180.v:2429$231
+  attribute \src "ls180.v:2414.8-2414.132"
+  cell $ne $ne$ls180.v:2414$199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
@@ -257023,10 +256539,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
     connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-    connect \Y $ne$ls180.v:2429$231_Y
+    connect \Y $ne$ls180.v:2414$199_Y
   end
-  attribute \src "ls180.v:2461.70-2461.123"
-  cell $ne $ne$ls180.v:2461$238
+  attribute \src "ls180.v:2446.70-2446.123"
+  cell $ne $ne$ls180.v:2446$206
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257034,10 +256550,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 4'1000
-    connect \Y $ne$ls180.v:2461$238_Y
+    connect \Y $ne$ls180.v:2446$206_Y
   end
-  attribute \src "ls180.v:2462.70-2462.123"
-  cell $ne $ne$ls180.v:2462$239
+  attribute \src "ls180.v:2447.70-2447.123"
+  cell $ne $ne$ls180.v:2447$207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257045,10 +256561,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'0
-    connect \Y $ne$ls180.v:2462$239_Y
+    connect \Y $ne$ls180.v:2447$207_Y
   end
-  attribute \src "ls180.v:2954.37-2954.60"
-  cell $ne $ne$ls180.v:2954$637
+  attribute \src "ls180.v:2939.37-2939.60"
+  cell $ne $ne$ls180.v:2939$605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -257056,10 +256572,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_level0
     connect \B 5'10000
-    connect \Y $ne$ls180.v:2954$637_Y
+    connect \Y $ne$ls180.v:2939$605_Y
   end
-  attribute \src "ls180.v:2955.37-2955.59"
-  cell $ne $ne$ls180.v:2955$638
+  attribute \src "ls180.v:2940.37-2940.59"
+  cell $ne $ne$ls180.v:2940$606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -257067,10 +256583,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_level0
     connect \B 1'0
-    connect \Y $ne$ls180.v:2955$638_Y
+    connect \Y $ne$ls180.v:2940$606_Y
   end
-  attribute \src "ls180.v:2984.37-2984.60"
-  cell $ne $ne$ls180.v:2984$648
+  attribute \src "ls180.v:2969.37-2969.60"
+  cell $ne $ne$ls180.v:2969$616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -257078,10 +256594,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_level0
     connect \B 5'10000
-    connect \Y $ne$ls180.v:2984$648_Y
+    connect \Y $ne$ls180.v:2969$616_Y
   end
-  attribute \src "ls180.v:2985.37-2985.59"
-  cell $ne $ne$ls180.v:2985$649
+  attribute \src "ls180.v:2970.37-2970.59"
+  cell $ne $ne$ls180.v:2970$617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -257089,10 +256605,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_level0
     connect \B 1'0
-    connect \Y $ne$ls180.v:2985$649_Y
+    connect \Y $ne$ls180.v:2970$617_Y
   end
-  attribute \src "ls180.v:3080.99-3080.143"
-  cell $ne $ne$ls180.v:3080$656
+  attribute \src "ls180.v:3065.99-3065.143"
+  cell $ne $ne$ls180.v:3065$624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257100,10 +256616,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_libresocsim_wishbone_sel
     connect \B 1'0
-    connect \Y $ne$ls180.v:3080$656_Y
+    connect \Y $ne$ls180.v:3065$624_Y
   end
-  attribute \src "ls180.v:4370.7-4370.47"
-  cell $ne $ne$ls180.v:4370$1287
+  attribute \src "ls180.v:4355.7-4355.47"
+  cell $ne $ne$ls180.v:4355$1255
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -257111,10 +256627,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_bus_errors
     connect \B 32'11111111111111111111111111111111
-    connect \Y $ne$ls180.v:4370$1287_Y
+    connect \Y $ne$ls180.v:4355$1255_Y
   end
-  attribute \src "ls180.v:4424.9-4424.38"
-  cell $ne $ne$ls180.v:4424$1304
+  attribute \src "ls180.v:4409.9-4409.38"
+  cell $ne $ne$ls180.v:4409$1272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -257122,10 +256638,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_count
     connect \B 1'0
-    connect \Y $ne$ls180.v:4424$1304_Y
+    connect \Y $ne$ls180.v:4409$1272_Y
   end
-  attribute \src "ls180.v:4460.8-4460.39"
-  cell $ne $ne$ls180.v:4460$1311
+  attribute \src "ls180.v:4445.8-4445.39"
+  cell $ne $ne$ls180.v:4445$1279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -257133,1686 +256649,1686 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_counter
     connect \B 1'0
-    connect \Y $ne$ls180.v:4460$1311_Y
+    connect \Y $ne$ls180.v:4445$1279_Y
   end
-  attribute \src "ls180.v:1526.28-1526.63"
-  cell $not $not$ls180.v:1526$25
+  attribute \src "ls180.v:1519.40-1519.70"
+  cell $not $not$ls180.v:1519$17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface0_converted_interface_cyc
-    connect \Y $not$ls180.v:1526$25_Y
+    connect \A \libresocsim_libresoc_ibus_cyc
+    connect \Y $not$ls180.v:1519$17_Y
   end
-  attribute \src "ls180.v:1565.43-1565.59"
-  cell $not $not$ls180.v:1565$30
+  attribute \src "ls180.v:1558.56-1558.84"
+  cell $not $not$ls180.v:1558$22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter0_skip
-    connect \Y $not$ls180.v:1565$30_Y
+    connect \A \libresocsim_converter0_skip
+    connect \Y $not$ls180.v:1558$22_Y
   end
-  attribute \src "ls180.v:1566.43-1566.59"
-  cell $not $not$ls180.v:1566$31
+  attribute \src "ls180.v:1559.56-1559.84"
+  cell $not $not$ls180.v:1559$23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter0_skip
-    connect \Y $not$ls180.v:1566$31_Y
+    connect \A \libresocsim_converter0_skip
+    connect \Y $not$ls180.v:1559$23_Y
   end
-  attribute \src "ls180.v:1586.28-1586.63"
-  cell $not $not$ls180.v:1586$36
+  attribute \src "ls180.v:1579.40-1579.70"
+  cell $not $not$ls180.v:1579$28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \interface1_converted_interface_cyc
-    connect \Y $not$ls180.v:1586$36_Y
+    connect \A \libresocsim_libresoc_dbus_cyc
+    connect \Y $not$ls180.v:1579$28_Y
   end
-  attribute \src "ls180.v:1625.43-1625.59"
-  cell $not $not$ls180.v:1625$41
+  attribute \src "ls180.v:1618.56-1618.84"
+  cell $not $not$ls180.v:1618$33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter1_skip
-    connect \Y $not$ls180.v:1625$41_Y
+    connect \A \libresocsim_converter1_skip
+    connect \Y $not$ls180.v:1618$33_Y
   end
-  attribute \src "ls180.v:1626.43-1626.59"
-  cell $not $not$ls180.v:1626$42
+  attribute \src "ls180.v:1619.56-1619.84"
+  cell $not $not$ls180.v:1619$34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \converter1_skip
-    connect \Y $not$ls180.v:1626$42_Y
+    connect \A \libresocsim_converter1_skip
+    connect \Y $not$ls180.v:1619$34_Y
   end
-  attribute \src "ls180.v:1646.31-1646.69"
-  cell $not $not$ls180.v:1646$47
+  attribute \src "ls180.v:1639.40-1639.73"
+  cell $not $not$ls180.v:1639$39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_converted_interface_cyc
-    connect \Y $not$ls180.v:1646$47_Y
+    connect \A \libresocsim_libresoc_jtag_wb_cyc
+    connect \Y $not$ls180.v:1639$39_Y
   end
-  attribute \src "ls180.v:1685.22-1685.41"
-  cell $not $not$ls180.v:1685$52
+  attribute \src "ls180.v:1678.56-1678.84"
+  cell $not $not$ls180.v:1678$44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_skip
-    connect \Y $not$ls180.v:1685$52_Y
+    connect \A \libresocsim_converter2_skip
+    connect \Y $not$ls180.v:1678$44_Y
   end
-  attribute \src "ls180.v:1686.22-1686.41"
-  cell $not $not$ls180.v:1686$53
+  attribute \src "ls180.v:1679.56-1679.84"
+  cell $not $not$ls180.v:1679$45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \socbushandler_skip
-    connect \Y $not$ls180.v:1686$53_Y
+    connect \A \libresocsim_converter2_skip
+    connect \Y $not$ls180.v:1679$45_Y
   end
-  attribute \src "ls180.v:1846.29-1846.54"
-  cell $not $not$ls180.v:1846$114
+  attribute \src "ls180.v:1831.29-1831.54"
+  cell $not $not$ls180.v:1831$82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_command_storage [0]
-    connect \Y $not$ls180.v:1846$114_Y
+    connect \Y $not$ls180.v:1831$82_Y
   end
-  attribute \src "ls180.v:1847.26-1847.51"
-  cell $not $not$ls180.v:1847$115
+  attribute \src "ls180.v:1832.26-1832.51"
+  cell $not $not$ls180.v:1832$83
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_command_storage [1]
-    connect \Y $not$ls180.v:1847$115_Y
+    connect \Y $not$ls180.v:1832$83_Y
   end
-  attribute \src "ls180.v:1848.27-1848.52"
-  cell $not $not$ls180.v:1848$116
+  attribute \src "ls180.v:1833.27-1833.52"
+  cell $not $not$ls180.v:1833$84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_command_storage [2]
-    connect \Y $not$ls180.v:1848$116_Y
+    connect \Y $not$ls180.v:1833$84_Y
   end
-  attribute \src "ls180.v:1849.27-1849.52"
-  cell $not $not$ls180.v:1849$117
+  attribute \src "ls180.v:1834.27-1834.52"
+  cell $not $not$ls180.v:1834$85
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_command_storage [3]
-    connect \Y $not$ls180.v:1849$117_Y
+    connect \Y $not$ls180.v:1834$85_Y
   end
-  attribute \src "ls180.v:1891.28-1891.46"
-  cell $not $not$ls180.v:1891$120
+  attribute \src "ls180.v:1876.28-1876.46"
+  cell $not $not$ls180.v:1876$88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_timer_done0
-    connect \Y $not$ls180.v:1891$120_Y
+    connect \Y $not$ls180.v:1876$88_Y
   end
-  attribute \src "ls180.v:1992.53-1992.96"
-  cell $not $not$ls180.v:1992$150
+  attribute \src "ls180.v:1977.53-1977.96"
+  cell $not $not$ls180.v:1977$118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:1992$150_Y
+    connect \Y $not$ls180.v:1977$118_Y
   end
-  attribute \src "ls180.v:2046.9-2046.40"
-  cell $not $not$ls180.v:2046$155
+  attribute \src "ls180.v:2031.9-2031.40"
+  cell $not $not$ls180.v:2031$123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_refresh_req
-    connect \Y $not$ls180.v:2046$155_Y
+    connect \Y $not$ls180.v:2031$123_Y
   end
-  attribute \src "ls180.v:2149.53-2149.96"
-  cell $not $not$ls180.v:2149$180
+  attribute \src "ls180.v:2134.53-2134.96"
+  cell $not $not$ls180.v:2134$148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:2149$180_Y
+    connect \Y $not$ls180.v:2134$148_Y
   end
-  attribute \src "ls180.v:2203.9-2203.40"
-  cell $not $not$ls180.v:2203$185
+  attribute \src "ls180.v:2188.9-2188.40"
+  cell $not $not$ls180.v:2188$153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_refresh_req
-    connect \Y $not$ls180.v:2203$185_Y
+    connect \Y $not$ls180.v:2188$153_Y
   end
-  attribute \src "ls180.v:2306.53-2306.96"
-  cell $not $not$ls180.v:2306$210
+  attribute \src "ls180.v:2291.53-2291.96"
+  cell $not $not$ls180.v:2291$178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:2306$210_Y
+    connect \Y $not$ls180.v:2291$178_Y
   end
-  attribute \src "ls180.v:2360.9-2360.40"
-  cell $not $not$ls180.v:2360$215
+  attribute \src "ls180.v:2345.9-2345.40"
+  cell $not $not$ls180.v:2345$183
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_refresh_req
-    connect \Y $not$ls180.v:2360$215_Y
+    connect \Y $not$ls180.v:2345$183_Y
   end
-  attribute \src "ls180.v:2463.53-2463.96"
-  cell $not $not$ls180.v:2463$240
+  attribute \src "ls180.v:2448.53-2448.96"
+  cell $not $not$ls180.v:2448$208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:2463$240_Y
+    connect \Y $not$ls180.v:2448$208_Y
   end
-  attribute \src "ls180.v:2517.9-2517.40"
-  cell $not $not$ls180.v:2517$245
+  attribute \src "ls180.v:2502.9-2502.40"
+  cell $not $not$ls180.v:2502$213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_refresh_req
-    connect \Y $not$ls180.v:2517$245_Y
+    connect \Y $not$ls180.v:2502$213_Y
   end
-  attribute \src "ls180.v:2559.129-2559.162"
-  cell $not $not$ls180.v:2559$248
+  attribute \src "ls180.v:2544.129-2544.162"
+  cell $not $not$ls180.v:2544$216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:2559$248_Y
+    connect \Y $not$ls180.v:2544$216_Y
   end
-  attribute \src "ls180.v:2559.168-2559.200"
-  cell $not $not$ls180.v:2559$250
+  attribute \src "ls180.v:2544.168-2544.200"
+  cell $not $not$ls180.v:2544$218
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:2559$250_Y
+    connect \Y $not$ls180.v:2544$218_Y
   end
-  attribute \src "ls180.v:2560.129-2560.162"
-  cell $not $not$ls180.v:2560$254
+  attribute \src "ls180.v:2545.129-2545.162"
+  cell $not $not$ls180.v:2545$222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:2560$254_Y
+    connect \Y $not$ls180.v:2545$222_Y
   end
-  attribute \src "ls180.v:2560.168-2560.200"
-  cell $not $not$ls180.v:2560$256
+  attribute \src "ls180.v:2545.168-2545.200"
+  cell $not $not$ls180.v:2545$224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:2560$256_Y
+    connect \Y $not$ls180.v:2545$224_Y
   end
-  attribute \src "ls180.v:2576.38-2576.63"
-  cell $not $not$ls180.v:2576$284
+  attribute \src "ls180.v:2561.38-2561.63"
+  cell $not $not$ls180.v:2561$252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \sdram_interface_wdata_we
-    connect \Y $not$ls180.v:2576$284_Y
+    connect \Y $not$ls180.v:2561$252_Y
   end
-  attribute \src "ls180.v:2579.180-2579.215"
-  cell $not $not$ls180.v:2579$287
+  attribute \src "ls180.v:2564.180-2564.215"
+  cell $not $not$ls180.v:2564$255
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_cas
-    connect \Y $not$ls180.v:2579$287_Y
+    connect \Y $not$ls180.v:2564$255_Y
   end
-  attribute \src "ls180.v:2579.221-2579.255"
-  cell $not $not$ls180.v:2579$289
+  attribute \src "ls180.v:2564.221-2564.255"
+  cell $not $not$ls180.v:2564$257
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_we
-    connect \Y $not$ls180.v:2579$289_Y
+    connect \Y $not$ls180.v:2564$257_Y
   end
-  attribute \src "ls180.v:2579.139-2579.257"
-  cell $not $not$ls180.v:2579$291
+  attribute \src "ls180.v:2564.139-2564.257"
+  cell $not $not$ls180.v:2564$259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2579$290_Y
-    connect \Y $not$ls180.v:2579$291_Y
+    connect \A $and$ls180.v:2564$258_Y
+    connect \Y $not$ls180.v:2564$259_Y
   end
-  attribute \src "ls180.v:2580.180-2580.215"
-  cell $not $not$ls180.v:2580$300
+  attribute \src "ls180.v:2565.180-2565.215"
+  cell $not $not$ls180.v:2565$268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_cas
-    connect \Y $not$ls180.v:2580$300_Y
+    connect \Y $not$ls180.v:2565$268_Y
   end
-  attribute \src "ls180.v:2580.221-2580.255"
-  cell $not $not$ls180.v:2580$302
+  attribute \src "ls180.v:2565.221-2565.255"
+  cell $not $not$ls180.v:2565$270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_we
-    connect \Y $not$ls180.v:2580$302_Y
+    connect \Y $not$ls180.v:2565$270_Y
   end
-  attribute \src "ls180.v:2580.139-2580.257"
-  cell $not $not$ls180.v:2580$304
+  attribute \src "ls180.v:2565.139-2565.257"
+  cell $not $not$ls180.v:2565$272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2580$303_Y
-    connect \Y $not$ls180.v:2580$304_Y
+    connect \A $and$ls180.v:2565$271_Y
+    connect \Y $not$ls180.v:2565$272_Y
   end
-  attribute \src "ls180.v:2581.180-2581.215"
-  cell $not $not$ls180.v:2581$313
+  attribute \src "ls180.v:2566.180-2566.215"
+  cell $not $not$ls180.v:2566$281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_cas
-    connect \Y $not$ls180.v:2581$313_Y
+    connect \Y $not$ls180.v:2566$281_Y
   end
-  attribute \src "ls180.v:2581.221-2581.255"
-  cell $not $not$ls180.v:2581$315
+  attribute \src "ls180.v:2566.221-2566.255"
+  cell $not $not$ls180.v:2566$283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_we
-    connect \Y $not$ls180.v:2581$315_Y
+    connect \Y $not$ls180.v:2566$283_Y
   end
-  attribute \src "ls180.v:2581.139-2581.257"
-  cell $not $not$ls180.v:2581$317
+  attribute \src "ls180.v:2566.139-2566.257"
+  cell $not $not$ls180.v:2566$285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2581$316_Y
-    connect \Y $not$ls180.v:2581$317_Y
+    connect \A $and$ls180.v:2566$284_Y
+    connect \Y $not$ls180.v:2566$285_Y
   end
-  attribute \src "ls180.v:2582.180-2582.215"
-  cell $not $not$ls180.v:2582$326
+  attribute \src "ls180.v:2567.180-2567.215"
+  cell $not $not$ls180.v:2567$294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_cas
-    connect \Y $not$ls180.v:2582$326_Y
+    connect \Y $not$ls180.v:2567$294_Y
   end
-  attribute \src "ls180.v:2582.221-2582.255"
-  cell $not $not$ls180.v:2582$328
+  attribute \src "ls180.v:2567.221-2567.255"
+  cell $not $not$ls180.v:2567$296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_we
-    connect \Y $not$ls180.v:2582$328_Y
+    connect \Y $not$ls180.v:2567$296_Y
   end
-  attribute \src "ls180.v:2582.139-2582.257"
-  cell $not $not$ls180.v:2582$330
+  attribute \src "ls180.v:2567.139-2567.257"
+  cell $not $not$ls180.v:2567$298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2582$329_Y
-    connect \Y $not$ls180.v:2582$330_Y
+    connect \A $and$ls180.v:2567$297_Y
+    connect \Y $not$ls180.v:2567$298_Y
   end
-  attribute \src "ls180.v:2609.61-2609.88"
-  cell $not $not$ls180.v:2609$341
+  attribute \src "ls180.v:2594.61-2594.88"
+  cell $not $not$ls180.v:2594$309
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_valid
-    connect \Y $not$ls180.v:2609$341_Y
+    connect \Y $not$ls180.v:2594$309_Y
   end
-  attribute \src "ls180.v:2612.180-2612.215"
-  cell $not $not$ls180.v:2612$345
+  attribute \src "ls180.v:2597.180-2597.215"
+  cell $not $not$ls180.v:2597$313
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_cas
-    connect \Y $not$ls180.v:2612$345_Y
+    connect \Y $not$ls180.v:2597$313_Y
   end
-  attribute \src "ls180.v:2612.221-2612.255"
-  cell $not $not$ls180.v:2612$347
+  attribute \src "ls180.v:2597.221-2597.255"
+  cell $not $not$ls180.v:2597$315
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_payload_we
-    connect \Y $not$ls180.v:2612$347_Y
+    connect \Y $not$ls180.v:2597$315_Y
   end
-  attribute \src "ls180.v:2612.139-2612.257"
-  cell $not $not$ls180.v:2612$349
+  attribute \src "ls180.v:2597.139-2597.257"
+  cell $not $not$ls180.v:2597$317
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2612$348_Y
-    connect \Y $not$ls180.v:2612$349_Y
+    connect \A $and$ls180.v:2597$316_Y
+    connect \Y $not$ls180.v:2597$317_Y
   end
-  attribute \src "ls180.v:2613.180-2613.215"
-  cell $not $not$ls180.v:2613$358
+  attribute \src "ls180.v:2598.180-2598.215"
+  cell $not $not$ls180.v:2598$326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_cas
-    connect \Y $not$ls180.v:2613$358_Y
+    connect \Y $not$ls180.v:2598$326_Y
   end
-  attribute \src "ls180.v:2613.221-2613.255"
-  cell $not $not$ls180.v:2613$360
+  attribute \src "ls180.v:2598.221-2598.255"
+  cell $not $not$ls180.v:2598$328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_payload_we
-    connect \Y $not$ls180.v:2613$360_Y
+    connect \Y $not$ls180.v:2598$328_Y
   end
-  attribute \src "ls180.v:2613.139-2613.257"
-  cell $not $not$ls180.v:2613$362
+  attribute \src "ls180.v:2598.139-2598.257"
+  cell $not $not$ls180.v:2598$330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2613$361_Y
-    connect \Y $not$ls180.v:2613$362_Y
+    connect \A $and$ls180.v:2598$329_Y
+    connect \Y $not$ls180.v:2598$330_Y
   end
-  attribute \src "ls180.v:2614.180-2614.215"
-  cell $not $not$ls180.v:2614$371
+  attribute \src "ls180.v:2599.180-2599.215"
+  cell $not $not$ls180.v:2599$339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_cas
-    connect \Y $not$ls180.v:2614$371_Y
+    connect \Y $not$ls180.v:2599$339_Y
   end
-  attribute \src "ls180.v:2614.221-2614.255"
-  cell $not $not$ls180.v:2614$373
+  attribute \src "ls180.v:2599.221-2599.255"
+  cell $not $not$ls180.v:2599$341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_payload_we
-    connect \Y $not$ls180.v:2614$373_Y
+    connect \Y $not$ls180.v:2599$341_Y
   end
-  attribute \src "ls180.v:2614.139-2614.257"
-  cell $not $not$ls180.v:2614$375
+  attribute \src "ls180.v:2599.139-2599.257"
+  cell $not $not$ls180.v:2599$343
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2614$374_Y
-    connect \Y $not$ls180.v:2614$375_Y
+    connect \A $and$ls180.v:2599$342_Y
+    connect \Y $not$ls180.v:2599$343_Y
   end
-  attribute \src "ls180.v:2615.180-2615.215"
-  cell $not $not$ls180.v:2615$384
+  attribute \src "ls180.v:2600.180-2600.215"
+  cell $not $not$ls180.v:2600$352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_cas
-    connect \Y $not$ls180.v:2615$384_Y
+    connect \Y $not$ls180.v:2600$352_Y
   end
-  attribute \src "ls180.v:2615.221-2615.255"
-  cell $not $not$ls180.v:2615$386
+  attribute \src "ls180.v:2600.221-2600.255"
+  cell $not $not$ls180.v:2600$354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_payload_we
-    connect \Y $not$ls180.v:2615$386_Y
+    connect \Y $not$ls180.v:2600$354_Y
   end
-  attribute \src "ls180.v:2615.139-2615.257"
-  cell $not $not$ls180.v:2615$388
+  attribute \src "ls180.v:2600.139-2600.257"
+  cell $not $not$ls180.v:2600$356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2615$387_Y
-    connect \Y $not$ls180.v:2615$388_Y
+    connect \A $and$ls180.v:2600$355_Y
+    connect \Y $not$ls180.v:2600$356_Y
   end
-  attribute \src "ls180.v:2678.61-2678.88"
-  cell $not $not$ls180.v:2678$427
+  attribute \src "ls180.v:2663.61-2663.88"
+  cell $not $not$ls180.v:2663$395
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_valid
-    connect \Y $not$ls180.v:2678$427_Y
+    connect \Y $not$ls180.v:2663$395_Y
   end
-  attribute \src "ls180.v:2699.97-2699.130"
-  cell $not $not$ls180.v:2699$430
+  attribute \src "ls180.v:2684.97-2684.130"
+  cell $not $not$ls180.v:2684$398
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:2699$430_Y
+    connect \Y $not$ls180.v:2684$398_Y
   end
-  attribute \src "ls180.v:2699.136-2699.168"
-  cell $not $not$ls180.v:2699$432
+  attribute \src "ls180.v:2684.136-2684.168"
+  cell $not $not$ls180.v:2684$400
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:2699$432_Y
+    connect \Y $not$ls180.v:2684$400_Y
   end
-  attribute \src "ls180.v:2699.58-2699.170"
-  cell $not $not$ls180.v:2699$434
+  attribute \src "ls180.v:2684.58-2684.170"
+  cell $not $not$ls180.v:2684$402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2699$433_Y
-    connect \Y $not$ls180.v:2699$434_Y
+    connect \A $and$ls180.v:2684$401_Y
+    connect \Y $not$ls180.v:2684$402_Y
   end
-  attribute \src "ls180.v:2707.11-2707.33"
-  cell $not $not$ls180.v:2707$437
+  attribute \src "ls180.v:2692.11-2692.33"
+  cell $not $not$ls180.v:2692$405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_write_available
-    connect \Y $not$ls180.v:2707$437_Y
+    connect \Y $not$ls180.v:2692$405_Y
   end
-  attribute \src "ls180.v:2737.97-2737.130"
-  cell $not $not$ls180.v:2737$439
+  attribute \src "ls180.v:2722.97-2722.130"
+  cell $not $not$ls180.v:2722$407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_cas
-    connect \Y $not$ls180.v:2737$439_Y
+    connect \Y $not$ls180.v:2722$407_Y
   end
-  attribute \src "ls180.v:2737.136-2737.168"
-  cell $not $not$ls180.v:2737$441
+  attribute \src "ls180.v:2722.136-2722.168"
+  cell $not $not$ls180.v:2722$409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_we
-    connect \Y $not$ls180.v:2737$441_Y
+    connect \Y $not$ls180.v:2722$409_Y
   end
-  attribute \src "ls180.v:2737.58-2737.170"
-  cell $not $not$ls180.v:2737$443
+  attribute \src "ls180.v:2722.58-2722.170"
+  cell $not $not$ls180.v:2722$411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2737$442_Y
-    connect \Y $not$ls180.v:2737$443_Y
+    connect \A $and$ls180.v:2722$410_Y
+    connect \Y $not$ls180.v:2722$411_Y
   end
-  attribute \src "ls180.v:2745.11-2745.32"
-  cell $not $not$ls180.v:2745$446
+  attribute \src "ls180.v:2730.11-2730.32"
+  cell $not $not$ls180.v:2730$414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_read_available
-    connect \Y $not$ls180.v:2745$446_Y
+    connect \Y $not$ls180.v:2730$414_Y
   end
-  attribute \src "ls180.v:2755.87-2755.336"
-  cell $not $not$ls180.v:2755$458
+  attribute \src "ls180.v:2740.87-2740.336"
+  cell $not $not$ls180.v:2740$426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2755$457_Y
-    connect \Y $not$ls180.v:2755$458_Y
+    connect \A $or$ls180.v:2740$425_Y
+    connect \Y $not$ls180.v:2740$426_Y
   end
-  attribute \src "ls180.v:2756.40-2756.68"
-  cell $not $not$ls180.v:2756$461
+  attribute \src "ls180.v:2741.40-2741.68"
+  cell $not $not$ls180.v:2741$429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_valid
-    connect \Y $not$ls180.v:2756$461_Y
+    connect \Y $not$ls180.v:2741$429_Y
   end
-  attribute \src "ls180.v:2756.73-2756.100"
-  cell $not $not$ls180.v:2756$462
+  attribute \src "ls180.v:2741.73-2741.100"
+  cell $not $not$ls180.v:2741$430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank0_lock
-    connect \Y $not$ls180.v:2756$462_Y
+    connect \Y $not$ls180.v:2741$430_Y
   end
-  attribute \src "ls180.v:2760.87-2760.336"
-  cell $not $not$ls180.v:2760$474
+  attribute \src "ls180.v:2745.87-2745.336"
+  cell $not $not$ls180.v:2745$442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2760$473_Y
-    connect \Y $not$ls180.v:2760$474_Y
+    connect \A $or$ls180.v:2745$441_Y
+    connect \Y $not$ls180.v:2745$442_Y
   end
-  attribute \src "ls180.v:2761.40-2761.68"
-  cell $not $not$ls180.v:2761$477
+  attribute \src "ls180.v:2746.40-2746.68"
+  cell $not $not$ls180.v:2746$445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_valid
-    connect \Y $not$ls180.v:2761$477_Y
+    connect \Y $not$ls180.v:2746$445_Y
   end
-  attribute \src "ls180.v:2761.73-2761.100"
-  cell $not $not$ls180.v:2761$478
+  attribute \src "ls180.v:2746.73-2746.100"
+  cell $not $not$ls180.v:2746$446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank1_lock
-    connect \Y $not$ls180.v:2761$478_Y
+    connect \Y $not$ls180.v:2746$446_Y
   end
-  attribute \src "ls180.v:2765.87-2765.336"
-  cell $not $not$ls180.v:2765$490
+  attribute \src "ls180.v:2750.87-2750.336"
+  cell $not $not$ls180.v:2750$458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2765$489_Y
-    connect \Y $not$ls180.v:2765$490_Y
+    connect \A $or$ls180.v:2750$457_Y
+    connect \Y $not$ls180.v:2750$458_Y
   end
-  attribute \src "ls180.v:2766.40-2766.68"
-  cell $not $not$ls180.v:2766$493
+  attribute \src "ls180.v:2751.40-2751.68"
+  cell $not $not$ls180.v:2751$461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_valid
-    connect \Y $not$ls180.v:2766$493_Y
+    connect \Y $not$ls180.v:2751$461_Y
   end
-  attribute \src "ls180.v:2766.73-2766.100"
-  cell $not $not$ls180.v:2766$494
+  attribute \src "ls180.v:2751.73-2751.100"
+  cell $not $not$ls180.v:2751$462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank2_lock
-    connect \Y $not$ls180.v:2766$494_Y
+    connect \Y $not$ls180.v:2751$462_Y
   end
-  attribute \src "ls180.v:2770.87-2770.336"
-  cell $not $not$ls180.v:2770$506
+  attribute \src "ls180.v:2755.87-2755.336"
+  cell $not $not$ls180.v:2755$474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2770$505_Y
-    connect \Y $not$ls180.v:2770$506_Y
+    connect \A $or$ls180.v:2755$473_Y
+    connect \Y $not$ls180.v:2755$474_Y
   end
-  attribute \src "ls180.v:2771.40-2771.68"
-  cell $not $not$ls180.v:2771$509
+  attribute \src "ls180.v:2756.40-2756.68"
+  cell $not $not$ls180.v:2756$477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_valid
-    connect \Y $not$ls180.v:2771$509_Y
+    connect \Y $not$ls180.v:2756$477_Y
   end
-  attribute \src "ls180.v:2771.73-2771.100"
-  cell $not $not$ls180.v:2771$510
+  attribute \src "ls180.v:2756.73-2756.100"
+  cell $not $not$ls180.v:2756$478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_interface_bank3_lock
-    connect \Y $not$ls180.v:2771$510_Y
+    connect \Y $not$ls180.v:2756$478_Y
   end
-  attribute \src "ls180.v:2775.123-2775.372"
-  cell $not $not$ls180.v:2775$523
+  attribute \src "ls180.v:2760.123-2760.372"
+  cell $not $not$ls180.v:2760$491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$522_Y
-    connect \Y $not$ls180.v:2775$523_Y
+    connect \A $or$ls180.v:2760$490_Y
+    connect \Y $not$ls180.v:2760$491_Y
   end
-  attribute \src "ls180.v:2775.497-2775.746"
-  cell $not $not$ls180.v:2775$539
+  attribute \src "ls180.v:2760.497-2760.746"
+  cell $not $not$ls180.v:2760$507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$538_Y
-    connect \Y $not$ls180.v:2775$539_Y
+    connect \A $or$ls180.v:2760$506_Y
+    connect \Y $not$ls180.v:2760$507_Y
   end
-  attribute \src "ls180.v:2775.871-2775.1120"
-  cell $not $not$ls180.v:2775$555
+  attribute \src "ls180.v:2760.871-2760.1120"
+  cell $not $not$ls180.v:2760$523
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$554_Y
-    connect \Y $not$ls180.v:2775$555_Y
+    connect \A $or$ls180.v:2760$522_Y
+    connect \Y $not$ls180.v:2760$523_Y
   end
-  attribute \src "ls180.v:2775.1245-2775.1494"
-  cell $not $not$ls180.v:2775$571
+  attribute \src "ls180.v:2760.1245-2760.1494"
+  cell $not $not$ls180.v:2760$539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$570_Y
-    connect \Y $not$ls180.v:2775$571_Y
+    connect \A $or$ls180.v:2760$538_Y
+    connect \Y $not$ls180.v:2760$539_Y
   end
-  attribute \src "ls180.v:2797.27-2797.40"
-  cell $not $not$ls180.v:2797$577
+  attribute \src "ls180.v:2782.27-2782.40"
+  cell $not $not$ls180.v:2782$545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \wb_sdram_cyc
-    connect \Y $not$ls180.v:2797$577_Y
+    connect \Y $not$ls180.v:2782$545_Y
   end
-  attribute \src "ls180.v:2836.25-2836.40"
-  cell $not $not$ls180.v:2836$582
+  attribute \src "ls180.v:2821.25-2821.40"
+  cell $not $not$ls180.v:2821$550
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \converter_skip
-    connect \Y $not$ls180.v:2836$582_Y
+    connect \Y $not$ls180.v:2821$550_Y
   end
-  attribute \src "ls180.v:2837.25-2837.40"
-  cell $not $not$ls180.v:2837$583
+  attribute \src "ls180.v:2822.25-2822.40"
+  cell $not $not$ls180.v:2822$551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \converter_skip
-    connect \Y $not$ls180.v:2837$583_Y
+    connect \Y $not$ls180.v:2822$551_Y
   end
-  attribute \src "ls180.v:2862.22-2862.38"
-  cell $not $not$ls180.v:2862$589
+  attribute \src "ls180.v:2847.22-2847.38"
+  cell $not $not$ls180.v:2847$557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_cyc
-    connect \Y $not$ls180.v:2862$589_Y
+    connect \Y $not$ls180.v:2847$557_Y
   end
-  attribute \src "ls180.v:2863.25-2863.40"
-  cell $not $not$ls180.v:2863$590
+  attribute \src "ls180.v:2848.25-2848.40"
+  cell $not $not$ls180.v:2848$558
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_we
-    connect \Y $not$ls180.v:2863$590_Y
+    connect \Y $not$ls180.v:2848$558_Y
   end
-  attribute \src "ls180.v:2864.65-2864.78"
-  cell $not $not$ls180.v:2864$592
+  attribute \src "ls180.v:2849.65-2849.78"
+  cell $not $not$ls180.v:2849$560
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \cmd_consumed
-    connect \Y $not$ls180.v:2864$592_Y
+    connect \Y $not$ls180.v:2849$560_Y
   end
-  attribute \src "ls180.v:2865.87-2865.102"
-  cell $not $not$ls180.v:2865$596
+  attribute \src "ls180.v:2850.87-2850.102"
+  cell $not $not$ls180.v:2850$564
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \wdata_consumed
-    connect \Y $not$ls180.v:2865$596_Y
+    connect \Y $not$ls180.v:2850$564_Y
   end
-  attribute \src "ls180.v:2866.63-2866.83"
-  cell $not $not$ls180.v:2866$599
+  attribute \src "ls180.v:2851.63-2851.83"
+  cell $not $not$ls180.v:2851$567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \port_cmd_payload_we
-    connect \Y $not$ls180.v:2866$599_Y
+    connect \Y $not$ls180.v:2851$567_Y
   end
-  attribute \src "ls180.v:2867.71-2867.86"
-  cell $not $not$ls180.v:2867$602
+  attribute \src "ls180.v:2852.71-2852.86"
+  cell $not $not$ls180.v:2852$570
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_we
-    connect \Y $not$ls180.v:2867$602_Y
+    connect \Y $not$ls180.v:2852$570_Y
   end
-  attribute \src "ls180.v:2883.25-2883.44"
-  cell $not $not$ls180.v:2883$611
+  attribute \src "ls180.v:2868.25-2868.44"
+  cell $not $not$ls180.v:2868$579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_sink_ready
-    connect \Y $not$ls180.v:2883$611_Y
+    connect \Y $not$ls180.v:2868$579_Y
   end
-  attribute \src "ls180.v:2884.26-2884.47"
-  cell $not $not$ls180.v:2884$612
+  attribute \src "ls180.v:2869.26-2869.47"
+  cell $not $not$ls180.v:2869$580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_source_valid
-    connect \Y $not$ls180.v:2884$612_Y
+    connect \Y $not$ls180.v:2869$580_Y
   end
-  attribute \src "ls180.v:2890.22-2890.41"
-  cell $not $not$ls180.v:2890$613
+  attribute \src "ls180.v:2875.22-2875.41"
+  cell $not $not$ls180.v:2875$581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_sink_ready
-    connect \Y $not$ls180.v:2890$613_Y
+    connect \Y $not$ls180.v:2875$581_Y
   end
-  attribute \src "ls180.v:2896.26-2896.47"
-  cell $not $not$ls180.v:2896$614
+  attribute \src "ls180.v:2881.26-2881.47"
+  cell $not $not$ls180.v:2881$582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_source_valid
-    connect \Y $not$ls180.v:2896$614_Y
+    connect \Y $not$ls180.v:2881$582_Y
   end
-  attribute \src "ls180.v:2897.25-2897.44"
-  cell $not $not$ls180.v:2897$615
+  attribute \src "ls180.v:2882.25-2882.44"
+  cell $not $not$ls180.v:2882$583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_sink_ready
-    connect \Y $not$ls180.v:2897$615_Y
+    connect \Y $not$ls180.v:2882$583_Y
   end
-  attribute \src "ls180.v:2900.22-2900.43"
-  cell $not $not$ls180.v:2900$618
+  attribute \src "ls180.v:2885.22-2885.43"
+  cell $not $not$ls180.v:2885$586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_source_valid
-    connect \Y $not$ls180.v:2900$618_Y
+    connect \Y $not$ls180.v:2885$586_Y
   end
-  attribute \src "ls180.v:2938.61-2938.78"
-  cell $not $not$ls180.v:2938$628
+  attribute \src "ls180.v:2923.61-2923.78"
+  cell $not $not$ls180.v:2923$596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_readable
-    connect \Y $not$ls180.v:2938$628_Y
+    connect \Y $not$ls180.v:2923$596_Y
   end
-  attribute \src "ls180.v:2968.61-2968.78"
-  cell $not $not$ls180.v:2968$639
+  attribute \src "ls180.v:2953.61-2953.78"
+  cell $not $not$ls180.v:2953$607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_readable
-    connect \Y $not$ls180.v:2968$639_Y
+    connect \Y $not$ls180.v:2953$607_Y
   end
-  attribute \src "ls180.v:3163.81-3163.104"
-  cell $not $not$ls180.v:3163$689
+  attribute \src "ls180.v:3148.81-3148.104"
+  cell $not $not$ls180.v:3148$657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_shared_ack
-    connect \Y $not$ls180.v:3163$689_Y
+    connect \Y $not$ls180.v:3148$657_Y
   end
-  attribute \src "ls180.v:3180.71-3180.106"
-  cell $not $not$ls180.v:3180$713
+  attribute \src "ls180.v:3165.71-3165.106"
+  cell $not $not$ls180.v:3165$681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3180$713_Y
+    connect \Y $not$ls180.v:3165$681_Y
   end
-  attribute \src "ls180.v:3183.73-3183.108"
-  cell $not $not$ls180.v:3183$720
+  attribute \src "ls180.v:3168.73-3168.108"
+  cell $not $not$ls180.v:3168$688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3183$720_Y
+    connect \Y $not$ls180.v:3168$688_Y
   end
-  attribute \src "ls180.v:3186.73-3186.108"
-  cell $not $not$ls180.v:3186$727
+  attribute \src "ls180.v:3171.73-3171.108"
+  cell $not $not$ls180.v:3171$695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3186$727_Y
+    connect \Y $not$ls180.v:3171$695_Y
   end
-  attribute \src "ls180.v:3189.73-3189.108"
-  cell $not $not$ls180.v:3189$734
+  attribute \src "ls180.v:3174.73-3174.108"
+  cell $not $not$ls180.v:3174$702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3189$734_Y
+    connect \Y $not$ls180.v:3174$702_Y
   end
-  attribute \src "ls180.v:3192.73-3192.108"
-  cell $not $not$ls180.v:3192$741
+  attribute \src "ls180.v:3177.73-3177.108"
+  cell $not $not$ls180.v:3177$709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3192$741_Y
+    connect \Y $not$ls180.v:3177$709_Y
   end
-  attribute \src "ls180.v:3195.76-3195.111"
-  cell $not $not$ls180.v:3195$748
+  attribute \src "ls180.v:3180.76-3180.111"
+  cell $not $not$ls180.v:3180$716
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3195$748_Y
+    connect \Y $not$ls180.v:3180$716_Y
   end
-  attribute \src "ls180.v:3198.76-3198.111"
-  cell $not $not$ls180.v:3198$755
+  attribute \src "ls180.v:3183.76-3183.111"
+  cell $not $not$ls180.v:3183$723
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3198$755_Y
+    connect \Y $not$ls180.v:3183$723_Y
   end
-  attribute \src "ls180.v:3201.76-3201.111"
-  cell $not $not$ls180.v:3201$762
+  attribute \src "ls180.v:3186.76-3186.111"
+  cell $not $not$ls180.v:3186$730
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3201$762_Y
+    connect \Y $not$ls180.v:3186$730_Y
   end
-  attribute \src "ls180.v:3204.76-3204.111"
-  cell $not $not$ls180.v:3204$769
+  attribute \src "ls180.v:3189.76-3189.111"
+  cell $not $not$ls180.v:3189$737
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface0_bank_bus_we
-    connect \Y $not$ls180.v:3204$769_Y
+    connect \Y $not$ls180.v:3189$737_Y
   end
-  attribute \src "ls180.v:3218.68-3218.103"
-  cell $not $not$ls180.v:3218$777
+  attribute \src "ls180.v:3203.68-3203.103"
+  cell $not $not$ls180.v:3203$745
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_we
-    connect \Y $not$ls180.v:3218$777_Y
+    connect \Y $not$ls180.v:3203$745_Y
   end
-  attribute \src "ls180.v:3221.67-3221.102"
-  cell $not $not$ls180.v:3221$784
+  attribute \src "ls180.v:3206.67-3206.102"
+  cell $not $not$ls180.v:3206$752
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_we
-    connect \Y $not$ls180.v:3221$784_Y
+    connect \Y $not$ls180.v:3206$752_Y
   end
-  attribute \src "ls180.v:3224.69-3224.104"
-  cell $not $not$ls180.v:3224$791
+  attribute \src "ls180.v:3209.69-3209.104"
+  cell $not $not$ls180.v:3209$759
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface1_bank_bus_we
-    connect \Y $not$ls180.v:3224$791_Y
+    connect \Y $not$ls180.v:3209$759_Y
   end
-  attribute \src "ls180.v:3232.68-3232.103"
-  cell $not $not$ls180.v:3232$799
+  attribute \src "ls180.v:3217.68-3217.103"
+  cell $not $not$ls180.v:3217$767
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_we
-    connect \Y $not$ls180.v:3232$799_Y
+    connect \Y $not$ls180.v:3217$767_Y
   end
-  attribute \src "ls180.v:3235.67-3235.102"
-  cell $not $not$ls180.v:3235$806
+  attribute \src "ls180.v:3220.67-3220.102"
+  cell $not $not$ls180.v:3220$774
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_we
-    connect \Y $not$ls180.v:3235$806_Y
+    connect \Y $not$ls180.v:3220$774_Y
   end
-  attribute \src "ls180.v:3238.69-3238.104"
-  cell $not $not$ls180.v:3238$813
+  attribute \src "ls180.v:3223.69-3223.104"
+  cell $not $not$ls180.v:3223$781
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface2_bank_bus_we
-    connect \Y $not$ls180.v:3238$813_Y
+    connect \Y $not$ls180.v:3223$781_Y
   end
-  attribute \src "ls180.v:3246.67-3246.102"
-  cell $not $not$ls180.v:3246$821
+  attribute \src "ls180.v:3231.67-3231.102"
+  cell $not $not$ls180.v:3231$789
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_we
-    connect \Y $not$ls180.v:3246$821_Y
+    connect \Y $not$ls180.v:3231$789_Y
   end
-  attribute \src "ls180.v:3249.66-3249.101"
-  cell $not $not$ls180.v:3249$828
+  attribute \src "ls180.v:3234.66-3234.101"
+  cell $not $not$ls180.v:3234$796
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface3_bank_bus_we
-    connect \Y $not$ls180.v:3249$828_Y
+    connect \Y $not$ls180.v:3234$796_Y
   end
-  attribute \src "ls180.v:3260.78-3260.113"
-  cell $not $not$ls180.v:3260$836
+  attribute \src "ls180.v:3245.78-3245.113"
+  cell $not $not$ls180.v:3245$804
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3260$836_Y
+    connect \Y $not$ls180.v:3245$804_Y
   end
-  attribute \src "ls180.v:3263.82-3263.117"
-  cell $not $not$ls180.v:3263$843
+  attribute \src "ls180.v:3248.82-3248.117"
+  cell $not $not$ls180.v:3248$811
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3263$843_Y
+    connect \Y $not$ls180.v:3248$811_Y
   end
-  attribute \src "ls180.v:3266.63-3266.98"
-  cell $not $not$ls180.v:3266$850
+  attribute \src "ls180.v:3251.63-3251.98"
+  cell $not $not$ls180.v:3251$818
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3266$850_Y
+    connect \Y $not$ls180.v:3251$818_Y
   end
-  attribute \src "ls180.v:3269.82-3269.117"
-  cell $not $not$ls180.v:3269$857
+  attribute \src "ls180.v:3254.82-3254.117"
+  cell $not $not$ls180.v:3254$825
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3269$857_Y
+    connect \Y $not$ls180.v:3254$825_Y
   end
-  attribute \src "ls180.v:3272.82-3272.117"
-  cell $not $not$ls180.v:3272$864
+  attribute \src "ls180.v:3257.82-3257.117"
+  cell $not $not$ls180.v:3257$832
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3272$864_Y
+    connect \Y $not$ls180.v:3257$832_Y
   end
-  attribute \src "ls180.v:3275.83-3275.118"
-  cell $not $not$ls180.v:3275$871
+  attribute \src "ls180.v:3260.83-3260.118"
+  cell $not $not$ls180.v:3260$839
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3275$871_Y
+    connect \Y $not$ls180.v:3260$839_Y
   end
-  attribute \src "ls180.v:3278.81-3278.116"
-  cell $not $not$ls180.v:3278$878
+  attribute \src "ls180.v:3263.81-3263.116"
+  cell $not $not$ls180.v:3263$846
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3278$878_Y
+    connect \Y $not$ls180.v:3263$846_Y
   end
-  attribute \src "ls180.v:3281.81-3281.116"
-  cell $not $not$ls180.v:3281$885
+  attribute \src "ls180.v:3266.81-3266.116"
+  cell $not $not$ls180.v:3266$853
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3281$885_Y
+    connect \Y $not$ls180.v:3266$853_Y
   end
-  attribute \src "ls180.v:3284.81-3284.116"
-  cell $not $not$ls180.v:3284$892
+  attribute \src "ls180.v:3269.81-3269.116"
+  cell $not $not$ls180.v:3269$860
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3284$892_Y
+    connect \Y $not$ls180.v:3269$860_Y
   end
-  attribute \src "ls180.v:3287.81-3287.116"
-  cell $not $not$ls180.v:3287$899
+  attribute \src "ls180.v:3272.81-3272.116"
+  cell $not $not$ls180.v:3272$867
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface4_bank_bus_we
-    connect \Y $not$ls180.v:3287$899_Y
+    connect \Y $not$ls180.v:3272$867_Y
   end
-  attribute \src "ls180.v:3305.70-3305.105"
-  cell $not $not$ls180.v:3305$907
+  attribute \src "ls180.v:3290.70-3290.105"
+  cell $not $not$ls180.v:3290$875
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3305$907_Y
+    connect \Y $not$ls180.v:3290$875_Y
   end
-  attribute \src "ls180.v:3308.70-3308.105"
-  cell $not $not$ls180.v:3308$914
+  attribute \src "ls180.v:3293.70-3293.105"
+  cell $not $not$ls180.v:3293$882
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3308$914_Y
+    connect \Y $not$ls180.v:3293$882_Y
   end
-  attribute \src "ls180.v:3311.70-3311.105"
-  cell $not $not$ls180.v:3311$921
+  attribute \src "ls180.v:3296.70-3296.105"
+  cell $not $not$ls180.v:3296$889
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3311$921_Y
+    connect \Y $not$ls180.v:3296$889_Y
   end
-  attribute \src "ls180.v:3314.70-3314.105"
-  cell $not $not$ls180.v:3314$928
+  attribute \src "ls180.v:3299.70-3299.105"
+  cell $not $not$ls180.v:3299$896
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3314$928_Y
+    connect \Y $not$ls180.v:3299$896_Y
   end
-  attribute \src "ls180.v:3317.72-3317.107"
-  cell $not $not$ls180.v:3317$935
+  attribute \src "ls180.v:3302.72-3302.107"
+  cell $not $not$ls180.v:3302$903
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3317$935_Y
+    connect \Y $not$ls180.v:3302$903_Y
   end
-  attribute \src "ls180.v:3320.72-3320.107"
-  cell $not $not$ls180.v:3320$942
+  attribute \src "ls180.v:3305.72-3305.107"
+  cell $not $not$ls180.v:3305$910
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3320$942_Y
+    connect \Y $not$ls180.v:3305$910_Y
   end
-  attribute \src "ls180.v:3323.72-3323.107"
-  cell $not $not$ls180.v:3323$949
+  attribute \src "ls180.v:3308.72-3308.107"
+  cell $not $not$ls180.v:3308$917
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3323$949_Y
+    connect \Y $not$ls180.v:3308$917_Y
   end
-  attribute \src "ls180.v:3326.72-3326.107"
-  cell $not $not$ls180.v:3326$956
+  attribute \src "ls180.v:3311.72-3311.107"
+  cell $not $not$ls180.v:3311$924
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3326$956_Y
+    connect \Y $not$ls180.v:3311$924_Y
   end
-  attribute \src "ls180.v:3329.68-3329.103"
-  cell $not $not$ls180.v:3329$963
+  attribute \src "ls180.v:3314.68-3314.103"
+  cell $not $not$ls180.v:3314$931
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3329$963_Y
+    connect \Y $not$ls180.v:3314$931_Y
   end
-  attribute \src "ls180.v:3332.78-3332.113"
-  cell $not $not$ls180.v:3332$970
+  attribute \src "ls180.v:3317.78-3317.113"
+  cell $not $not$ls180.v:3317$938
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3332$970_Y
+    connect \Y $not$ls180.v:3317$938_Y
   end
-  attribute \src "ls180.v:3335.71-3335.106"
-  cell $not $not$ls180.v:3335$977
+  attribute \src "ls180.v:3320.71-3320.106"
+  cell $not $not$ls180.v:3320$945
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3335$977_Y
+    connect \Y $not$ls180.v:3320$945_Y
   end
-  attribute \src "ls180.v:3338.71-3338.106"
-  cell $not $not$ls180.v:3338$984
+  attribute \src "ls180.v:3323.71-3323.106"
+  cell $not $not$ls180.v:3323$952
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3338$984_Y
+    connect \Y $not$ls180.v:3323$952_Y
   end
-  attribute \src "ls180.v:3341.71-3341.106"
-  cell $not $not$ls180.v:3341$991
+  attribute \src "ls180.v:3326.71-3326.106"
+  cell $not $not$ls180.v:3326$959
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3341$991_Y
+    connect \Y $not$ls180.v:3326$959_Y
   end
-  attribute \src "ls180.v:3344.71-3344.106"
-  cell $not $not$ls180.v:3344$998
+  attribute \src "ls180.v:3329.71-3329.106"
+  cell $not $not$ls180.v:3329$966
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3344$998_Y
+    connect \Y $not$ls180.v:3329$966_Y
   end
-  attribute \src "ls180.v:3347.75-3347.110"
-  cell $not $not$ls180.v:3347$1005
+  attribute \src "ls180.v:3332.75-3332.110"
+  cell $not $not$ls180.v:3332$973
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3347$1005_Y
+    connect \Y $not$ls180.v:3332$973_Y
   end
-  attribute \src "ls180.v:3350.76-3350.111"
-  cell $not $not$ls180.v:3350$1012
+  attribute \src "ls180.v:3335.76-3335.111"
+  cell $not $not$ls180.v:3335$980
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3350$1012_Y
+    connect \Y $not$ls180.v:3335$980_Y
   end
-  attribute \src "ls180.v:3353.75-3353.110"
-  cell $not $not$ls180.v:3353$1019
+  attribute \src "ls180.v:3338.75-3338.110"
+  cell $not $not$ls180.v:3338$987
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface5_bank_bus_we
-    connect \Y $not$ls180.v:3353$1019_Y
+    connect \Y $not$ls180.v:3338$987_Y
   end
-  attribute \src "ls180.v:3373.48-3373.83"
-  cell $not $not$ls180.v:3373$1027
+  attribute \src "ls180.v:3358.48-3358.83"
+  cell $not $not$ls180.v:3358$995
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3373$1027_Y
+    connect \Y $not$ls180.v:3358$995_Y
   end
-  attribute \src "ls180.v:3376.71-3376.106"
-  cell $not $not$ls180.v:3376$1034
+  attribute \src "ls180.v:3361.71-3361.106"
+  cell $not $not$ls180.v:3361$1002
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3376$1034_Y
+    connect \Y $not$ls180.v:3361$1002_Y
   end
-  attribute \src "ls180.v:3379.72-3379.107"
-  cell $not $not$ls180.v:3379$1041
+  attribute \src "ls180.v:3364.72-3364.107"
+  cell $not $not$ls180.v:3364$1009
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3379$1041_Y
+    connect \Y $not$ls180.v:3364$1009_Y
   end
-  attribute \src "ls180.v:3382.63-3382.98"
-  cell $not $not$ls180.v:3382$1048
+  attribute \src "ls180.v:3367.63-3367.98"
+  cell $not $not$ls180.v:3367$1016
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3382$1048_Y
+    connect \Y $not$ls180.v:3367$1016_Y
   end
-  attribute \src "ls180.v:3385.64-3385.99"
-  cell $not $not$ls180.v:3385$1055
+  attribute \src "ls180.v:3370.64-3370.99"
+  cell $not $not$ls180.v:3370$1023
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3385$1055_Y
+    connect \Y $not$ls180.v:3370$1023_Y
   end
-  attribute \src "ls180.v:3388.75-3388.110"
-  cell $not $not$ls180.v:3388$1062
+  attribute \src "ls180.v:3373.75-3373.110"
+  cell $not $not$ls180.v:3373$1030
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3388$1062_Y
+    connect \Y $not$ls180.v:3373$1030_Y
   end
-  attribute \src "ls180.v:3391.72-3391.107"
-  cell $not $not$ls180.v:3391$1069
+  attribute \src "ls180.v:3376.72-3376.107"
+  cell $not $not$ls180.v:3376$1037
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3391$1069_Y
+    connect \Y $not$ls180.v:3376$1037_Y
   end
-  attribute \src "ls180.v:3394.71-3394.106"
-  cell $not $not$ls180.v:3394$1076
+  attribute \src "ls180.v:3379.71-3379.106"
+  cell $not $not$ls180.v:3379$1044
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface6_bank_bus_we
-    connect \Y $not$ls180.v:3394$1076_Y
+    connect \Y $not$ls180.v:3379$1044_Y
   end
-  attribute \src "ls180.v:3407.77-3407.112"
-  cell $not $not$ls180.v:3407$1084
+  attribute \src "ls180.v:3392.77-3392.112"
+  cell $not $not$ls180.v:3392$1052
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_we
-    connect \Y $not$ls180.v:3407$1084_Y
+    connect \Y $not$ls180.v:3392$1052_Y
   end
-  attribute \src "ls180.v:3410.77-3410.112"
-  cell $not $not$ls180.v:3410$1091
+  attribute \src "ls180.v:3395.77-3395.112"
+  cell $not $not$ls180.v:3395$1059
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_we
-    connect \Y $not$ls180.v:3410$1091_Y
+    connect \Y $not$ls180.v:3395$1059_Y
   end
-  attribute \src "ls180.v:3413.77-3413.112"
-  cell $not $not$ls180.v:3413$1098
+  attribute \src "ls180.v:3398.77-3398.112"
+  cell $not $not$ls180.v:3398$1066
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_we
-    connect \Y $not$ls180.v:3413$1098_Y
+    connect \Y $not$ls180.v:3398$1066_Y
   end
-  attribute \src "ls180.v:3416.77-3416.112"
-  cell $not $not$ls180.v:3416$1105
+  attribute \src "ls180.v:3401.77-3401.112"
+  cell $not $not$ls180.v:3401$1073
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_interface7_bank_bus_we
-    connect \Y $not$ls180.v:3416$1105_Y
+    connect \Y $not$ls180.v:3401$1073_Y
   end
-  attribute \src "ls180.v:3776.68-3776.317"
-  cell $not $not$ls180.v:3776$1147
+  attribute \src "ls180.v:3761.68-3761.317"
+  cell $not $not$ls180.v:3761$1115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3776$1146_Y
-    connect \Y $not$ls180.v:3776$1147_Y
+    connect \A $or$ls180.v:3761$1114_Y
+    connect \Y $not$ls180.v:3761$1115_Y
   end
-  attribute \src "ls180.v:3800.68-3800.317"
-  cell $not $not$ls180.v:3800$1163
+  attribute \src "ls180.v:3785.68-3785.317"
+  cell $not $not$ls180.v:3785$1131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3800$1162_Y
-    connect \Y $not$ls180.v:3800$1163_Y
+    connect \A $or$ls180.v:3785$1130_Y
+    connect \Y $not$ls180.v:3785$1131_Y
   end
-  attribute \src "ls180.v:3824.68-3824.317"
-  cell $not $not$ls180.v:3824$1179
+  attribute \src "ls180.v:3809.68-3809.317"
+  cell $not $not$ls180.v:3809$1147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3824$1178_Y
-    connect \Y $not$ls180.v:3824$1179_Y
+    connect \A $or$ls180.v:3809$1146_Y
+    connect \Y $not$ls180.v:3809$1147_Y
   end
-  attribute \src "ls180.v:3848.68-3848.317"
-  cell $not $not$ls180.v:3848$1195
+  attribute \src "ls180.v:3833.68-3833.317"
+  cell $not $not$ls180.v:3833$1163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3848$1194_Y
-    connect \Y $not$ls180.v:3848$1195_Y
+    connect \A $or$ls180.v:3833$1162_Y
+    connect \Y $not$ls180.v:3833$1163_Y
   end
-  attribute \src "ls180.v:4376.62-4376.86"
-  cell $not $not$ls180.v:4376$1290
+  attribute \src "ls180.v:4361.62-4361.86"
+  cell $not $not$ls180.v:4361$1258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_ack
-    connect \Y $not$ls180.v:4376$1290_Y
+    connect \Y $not$ls180.v:4361$1258_Y
   end
-  attribute \src "ls180.v:4395.8-4395.33"
-  cell $not $not$ls180.v:4395$1294
+  attribute \src "ls180.v:4380.8-4380.33"
+  cell $not $not$ls180.v:4380$1262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_zero_trigger
-    connect \Y $not$ls180.v:4395$1294_Y
+    connect \Y $not$ls180.v:4380$1262_Y
   end
-  attribute \src "ls180.v:4399.54-4399.74"
-  cell $not $not$ls180.v:4399$1297
+  attribute \src "ls180.v:4384.54-4384.74"
+  cell $not $not$ls180.v:4384$1265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ram_bus_ram_bus_ack
-    connect \Y $not$ls180.v:4399$1297_Y
+    connect \Y $not$ls180.v:4384$1265_Y
   end
-  attribute \src "ls180.v:4407.27-4407.45"
-  cell $not $not$ls180.v:4407$1299
+  attribute \src "ls180.v:4392.27-4392.45"
+  cell $not $not$ls180.v:4392$1267
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_timer_done0
-    connect \Y $not$ls180.v:4407$1299_Y
+    connect \Y $not$ls180.v:4392$1267_Y
   end
-  attribute \src "ls180.v:4477.126-4477.174"
-  cell $not $not$ls180.v:4477$1314
+  attribute \src "ls180.v:4462.126-4462.174"
+  cell $not $not$ls180.v:4462$1282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4477$1314_Y
+    connect \Y $not$ls180.v:4462$1282_Y
   end
-  attribute \src "ls180.v:4483.126-4483.174"
-  cell $not $not$ls180.v:4483$1319
+  attribute \src "ls180.v:4468.126-4468.174"
+  cell $not $not$ls180.v:4468$1287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4483$1319_Y
+    connect \Y $not$ls180.v:4468$1287_Y
   end
-  attribute \src "ls180.v:4484.8-4484.56"
-  cell $not $not$ls180.v:4484$1321
+  attribute \src "ls180.v:4469.8-4469.56"
+  cell $not $not$ls180.v:4469$1289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:4484$1321_Y
+    connect \Y $not$ls180.v:4469$1289_Y
   end
-  attribute \src "ls180.v:4492.8-4492.51"
-  cell $not $not$ls180.v:4492$1324
+  attribute \src "ls180.v:4477.8-4477.51"
+  cell $not $not$ls180.v:4477$1292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:4492$1324_Y
+    connect \Y $not$ls180.v:4477$1292_Y
   end
-  attribute \src "ls180.v:4507.8-4507.41"
-  cell $not $not$ls180.v:4507$1326
+  attribute \src "ls180.v:4492.8-4492.41"
+  cell $not $not$ls180.v:4492$1294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_twtpcon_ready
-    connect \Y $not$ls180.v:4507$1326_Y
+    connect \Y $not$ls180.v:4492$1294_Y
   end
-  attribute \src "ls180.v:4523.126-4523.174"
-  cell $not $not$ls180.v:4523$1330
+  attribute \src "ls180.v:4508.126-4508.174"
+  cell $not $not$ls180.v:4508$1298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4523$1330_Y
+    connect \Y $not$ls180.v:4508$1298_Y
   end
-  attribute \src "ls180.v:4529.126-4529.174"
-  cell $not $not$ls180.v:4529$1335
+  attribute \src "ls180.v:4514.126-4514.174"
+  cell $not $not$ls180.v:4514$1303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4529$1335_Y
+    connect \Y $not$ls180.v:4514$1303_Y
   end
-  attribute \src "ls180.v:4530.8-4530.56"
-  cell $not $not$ls180.v:4530$1337
+  attribute \src "ls180.v:4515.8-4515.56"
+  cell $not $not$ls180.v:4515$1305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:4530$1337_Y
+    connect \Y $not$ls180.v:4515$1305_Y
   end
-  attribute \src "ls180.v:4538.8-4538.51"
-  cell $not $not$ls180.v:4538$1340
+  attribute \src "ls180.v:4523.8-4523.51"
+  cell $not $not$ls180.v:4523$1308
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:4538$1340_Y
+    connect \Y $not$ls180.v:4523$1308_Y
   end
-  attribute \src "ls180.v:4553.8-4553.41"
-  cell $not $not$ls180.v:4553$1342
+  attribute \src "ls180.v:4538.8-4538.41"
+  cell $not $not$ls180.v:4538$1310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_twtpcon_ready
-    connect \Y $not$ls180.v:4553$1342_Y
+    connect \Y $not$ls180.v:4538$1310_Y
   end
-  attribute \src "ls180.v:4569.126-4569.174"
-  cell $not $not$ls180.v:4569$1346
+  attribute \src "ls180.v:4554.126-4554.174"
+  cell $not $not$ls180.v:4554$1314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4569$1346_Y
+    connect \Y $not$ls180.v:4554$1314_Y
   end
-  attribute \src "ls180.v:4575.126-4575.174"
-  cell $not $not$ls180.v:4575$1351
+  attribute \src "ls180.v:4560.126-4560.174"
+  cell $not $not$ls180.v:4560$1319
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4575$1351_Y
+    connect \Y $not$ls180.v:4560$1319_Y
   end
-  attribute \src "ls180.v:4576.8-4576.56"
-  cell $not $not$ls180.v:4576$1353
+  attribute \src "ls180.v:4561.8-4561.56"
+  cell $not $not$ls180.v:4561$1321
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:4576$1353_Y
+    connect \Y $not$ls180.v:4561$1321_Y
   end
-  attribute \src "ls180.v:4584.8-4584.51"
-  cell $not $not$ls180.v:4584$1356
+  attribute \src "ls180.v:4569.8-4569.51"
+  cell $not $not$ls180.v:4569$1324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:4584$1356_Y
+    connect \Y $not$ls180.v:4569$1324_Y
   end
-  attribute \src "ls180.v:4599.8-4599.41"
-  cell $not $not$ls180.v:4599$1358
+  attribute \src "ls180.v:4584.8-4584.41"
+  cell $not $not$ls180.v:4584$1326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_twtpcon_ready
-    connect \Y $not$ls180.v:4599$1358_Y
+    connect \Y $not$ls180.v:4584$1326_Y
   end
-  attribute \src "ls180.v:4615.126-4615.174"
-  cell $not $not$ls180.v:4615$1362
+  attribute \src "ls180.v:4600.126-4600.174"
+  cell $not $not$ls180.v:4600$1330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4615$1362_Y
+    connect \Y $not$ls180.v:4600$1330_Y
   end
-  attribute \src "ls180.v:4621.126-4621.174"
-  cell $not $not$ls180.v:4621$1367
+  attribute \src "ls180.v:4606.126-4606.174"
+  cell $not $not$ls180.v:4606$1335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $not$ls180.v:4621$1367_Y
+    connect \Y $not$ls180.v:4606$1335_Y
   end
-  attribute \src "ls180.v:4622.8-4622.56"
-  cell $not $not$ls180.v:4622$1369
+  attribute \src "ls180.v:4607.8-4607.56"
+  cell $not $not$ls180.v:4607$1337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read
-    connect \Y $not$ls180.v:4622$1369_Y
+    connect \Y $not$ls180.v:4607$1337_Y
   end
-  attribute \src "ls180.v:4630.8-4630.51"
-  cell $not $not$ls180.v:4630$1372
+  attribute \src "ls180.v:4615.8-4615.51"
+  cell $not $not$ls180.v:4615$1340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $not$ls180.v:4630$1372_Y
+    connect \Y $not$ls180.v:4615$1340_Y
   end
-  attribute \src "ls180.v:4645.8-4645.41"
-  cell $not $not$ls180.v:4645$1374
+  attribute \src "ls180.v:4630.8-4630.41"
+  cell $not $not$ls180.v:4630$1342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_twtpcon_ready
-    connect \Y $not$ls180.v:4645$1374_Y
+    connect \Y $not$ls180.v:4630$1342_Y
   end
-  attribute \src "ls180.v:4653.7-4653.17"
-  cell $not $not$ls180.v:4653$1377
+  attribute \src "ls180.v:4638.7-4638.17"
+  cell $not $not$ls180.v:4638$1345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_en0
-    connect \Y $not$ls180.v:4653$1377_Y
+    connect \Y $not$ls180.v:4638$1345_Y
   end
-  attribute \src "ls180.v:4656.8-4656.24"
-  cell $not $not$ls180.v:4656$1378
+  attribute \src "ls180.v:4641.8-4641.24"
+  cell $not $not$ls180.v:4641$1346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_max_time0
-    connect \Y $not$ls180.v:4656$1378_Y
+    connect \Y $not$ls180.v:4641$1346_Y
   end
-  attribute \src "ls180.v:4660.7-4660.17"
-  cell $not $not$ls180.v:4660$1380
+  attribute \src "ls180.v:4645.7-4645.17"
+  cell $not $not$ls180.v:4645$1348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_en1
-    connect \Y $not$ls180.v:4660$1380_Y
+    connect \Y $not$ls180.v:4645$1348_Y
   end
-  attribute \src "ls180.v:4663.8-4663.24"
-  cell $not $not$ls180.v:4663$1381
+  attribute \src "ls180.v:4648.8-4648.24"
+  cell $not $not$ls180.v:4648$1349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_max_time1
-    connect \Y $not$ls180.v:4663$1381_Y
+    connect \Y $not$ls180.v:4648$1349_Y
   end
-  attribute \src "ls180.v:4782.25-4782.38"
-  cell $not $not$ls180.v:4782$1383
+  attribute \src "ls180.v:4767.25-4767.38"
+  cell $not $not$ls180.v:4767$1351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \array_muxed2
-    connect \Y $not$ls180.v:4782$1383_Y
+    connect \Y $not$ls180.v:4767$1351_Y
   end
-  attribute \src "ls180.v:4783.25-4783.38"
-  cell $not $not$ls180.v:4783$1384
+  attribute \src "ls180.v:4768.25-4768.38"
+  cell $not $not$ls180.v:4768$1352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \array_muxed3
-    connect \Y $not$ls180.v:4783$1384_Y
+    connect \Y $not$ls180.v:4768$1352_Y
   end
-  attribute \src "ls180.v:4784.24-4784.37"
-  cell $not $not$ls180.v:4784$1385
+  attribute \src "ls180.v:4769.24-4769.37"
+  cell $not $not$ls180.v:4769$1353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \array_muxed4
-    connect \Y $not$ls180.v:4784$1385_Y
+    connect \Y $not$ls180.v:4769$1353_Y
   end
-  attribute \src "ls180.v:4795.8-4795.28"
-  cell $not $not$ls180.v:4795$1386
+  attribute \src "ls180.v:4780.8-4780.28"
+  cell $not $not$ls180.v:4780$1354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_tccdcon_ready
-    connect \Y $not$ls180.v:4795$1386_Y
+    connect \Y $not$ls180.v:4780$1354_Y
   end
-  attribute \src "ls180.v:4810.8-4810.28"
-  cell $not $not$ls180.v:4810$1389
+  attribute \src "ls180.v:4795.8-4795.28"
+  cell $not $not$ls180.v:4795$1357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_twtrcon_ready
-    connect \Y $not$ls180.v:4810$1389_Y
+    connect \Y $not$ls180.v:4795$1357_Y
   end
-  attribute \src "ls180.v:4846.31-4846.48"
-  cell $not $not$ls180.v:4846$1419
+  attribute \src "ls180.v:4831.31-4831.48"
+  cell $not $not$ls180.v:4831$1387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \uart_phy_tx_busy
-    connect \Y $not$ls180.v:4846$1419_Y
+    connect \Y $not$ls180.v:4831$1387_Y
   end
-  attribute \src "ls180.v:4846.54-4846.74"
-  cell $not $not$ls180.v:4846$1421
+  attribute \src "ls180.v:4831.54-4831.74"
+  cell $not $not$ls180.v:4831$1389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \uart_phy_sink_ready
-    connect \Y $not$ls180.v:4846$1421_Y
+    connect \Y $not$ls180.v:4831$1389_Y
   end
-  attribute \src "ls180.v:4875.7-4875.24"
-  cell $not $not$ls180.v:4875$1428
+  attribute \src "ls180.v:4860.7-4860.24"
+  cell $not $not$ls180.v:4860$1396
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \uart_phy_rx_busy
-    connect \Y $not$ls180.v:4875$1428_Y
+    connect \Y $not$ls180.v:4860$1396_Y
   end
-  attribute \src "ls180.v:4876.9-4876.21"
-  cell $not $not$ls180.v:4876$1429
+  attribute \src "ls180.v:4861.9-4861.21"
+  cell $not $not$ls180.v:4861$1397
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \uart_phy_rx
-    connect \Y $not$ls180.v:4876$1429_Y
+    connect \Y $not$ls180.v:4861$1397_Y
   end
-  attribute \src "ls180.v:4909.8-4909.19"
-  cell $not $not$ls180.v:4909$1435
+  attribute \src "ls180.v:4894.8-4894.19"
+  cell $not $not$ls180.v:4894$1403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_trigger
-    connect \Y $not$ls180.v:4909$1435_Y
+    connect \Y $not$ls180.v:4894$1403_Y
   end
-  attribute \src "ls180.v:4916.8-4916.19"
-  cell $not $not$ls180.v:4916$1437
+  attribute \src "ls180.v:4901.8-4901.19"
+  cell $not $not$ls180.v:4901$1405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_trigger
-    connect \Y $not$ls180.v:4916$1437_Y
+    connect \Y $not$ls180.v:4901$1405_Y
   end
-  attribute \src "ls180.v:4926.60-4926.76"
-  cell $not $not$ls180.v:4926$1440
+  attribute \src "ls180.v:4911.60-4911.76"
+  cell $not $not$ls180.v:4911$1408
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_replace
-    connect \Y $not$ls180.v:4926$1440_Y
+    connect \Y $not$ls180.v:4911$1408_Y
   end
-  attribute \src "ls180.v:4932.60-4932.76"
-  cell $not $not$ls180.v:4932$1445
+  attribute \src "ls180.v:4917.60-4917.76"
+  cell $not $not$ls180.v:4917$1413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_replace
-    connect \Y $not$ls180.v:4932$1445_Y
+    connect \Y $not$ls180.v:4917$1413_Y
   end
-  attribute \src "ls180.v:4933.8-4933.24"
-  cell $not $not$ls180.v:4933$1447
+  attribute \src "ls180.v:4918.8-4918.24"
+  cell $not $not$ls180.v:4918$1415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_do_read
-    connect \Y $not$ls180.v:4933$1447_Y
+    connect \Y $not$ls180.v:4918$1415_Y
   end
-  attribute \src "ls180.v:4948.60-4948.76"
-  cell $not $not$ls180.v:4948$1451
+  attribute \src "ls180.v:4933.60-4933.76"
+  cell $not $not$ls180.v:4933$1419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_replace
-    connect \Y $not$ls180.v:4948$1451_Y
+    connect \Y $not$ls180.v:4933$1419_Y
   end
-  attribute \src "ls180.v:4954.60-4954.76"
-  cell $not $not$ls180.v:4954$1456
+  attribute \src "ls180.v:4939.60-4939.76"
+  cell $not $not$ls180.v:4939$1424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_replace
-    connect \Y $not$ls180.v:4954$1456_Y
+    connect \Y $not$ls180.v:4939$1424_Y
   end
-  attribute \src "ls180.v:4955.8-4955.24"
-  cell $not $not$ls180.v:4955$1458
+  attribute \src "ls180.v:4940.8-4940.24"
+  cell $not $not$ls180.v:4940$1426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_do_read
-    connect \Y $not$ls180.v:4955$1458_Y
+    connect \Y $not$ls180.v:4940$1426_Y
   end
-  attribute \src "ls180.v:4989.9-4989.32"
-  cell $not $not$ls180.v:4989$1461
+  attribute \src "ls180.v:4974.9-4974.32"
+  cell $not $not$ls180.v:4974$1429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_request [0]
-    connect \Y $not$ls180.v:4989$1461_Y
+    connect \Y $not$ls180.v:4974$1429_Y
   end
-  attribute \src "ls180.v:5000.9-5000.32"
-  cell $not $not$ls180.v:5000$1462
+  attribute \src "ls180.v:4985.9-4985.32"
+  cell $not $not$ls180.v:4985$1430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_request [1]
-    connect \Y $not$ls180.v:5000$1462_Y
+    connect \Y $not$ls180.v:4985$1430_Y
   end
-  attribute \src "ls180.v:5011.9-5011.32"
-  cell $not $not$ls180.v:5011$1463
+  attribute \src "ls180.v:4996.9-4996.32"
+  cell $not $not$ls180.v:4996$1431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_request [2]
-    connect \Y $not$ls180.v:5011$1463_Y
+    connect \Y $not$ls180.v:4996$1431_Y
   end
-  attribute \src "ls180.v:5024.8-5024.25"
-  cell $not $not$ls180.v:5024$1464
+  attribute \src "ls180.v:5009.8-5009.25"
+  cell $not $not$ls180.v:5009$1432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \libresocsim_done
-    connect \Y $not$ls180.v:5024$1464_Y
+    connect \Y $not$ls180.v:5009$1432_Y
   end
-  attribute \src "ls180.v:1567.10-1567.61"
-  cell $or $or$ls180.v:1567$32
+  attribute \src "ls180.v:1560.10-1560.86"
+  cell $or $or$ls180.v:1560$24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_icp_ack
-    connect \B \converter0_skip
-    connect \Y $or$ls180.v:1567$32_Y
+    connect \A \libresocsim_interface0_converted_interface_ack
+    connect \B \libresocsim_converter0_skip
+    connect \Y $or$ls180.v:1560$24_Y
   end
-  attribute \src "ls180.v:1627.10-1627.61"
-  cell $or $or$ls180.v:1627$43
+  attribute \src "ls180.v:1620.10-1620.86"
+  cell $or $or$ls180.v:1620$35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_ics_ack
-    connect \B \converter1_skip
-    connect \Y $or$ls180.v:1627$43_Y
+    connect \A \libresocsim_interface1_converted_interface_ack
+    connect \B \libresocsim_converter1_skip
+    connect \Y $or$ls180.v:1620$35_Y
   end
-  attribute \src "ls180.v:1687.10-1687.43"
-  cell $or $or$ls180.v:1687$54
+  attribute \src "ls180.v:1680.10-1680.86"
+  cell $or $or$ls180.v:1680$46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wb_sdram_ack
-    connect \B \socbushandler_skip
-    connect \Y $or$ls180.v:1687$54_Y
+    connect \A \libresocsim_interface2_converted_interface_ack
+    connect \B \libresocsim_converter2_skip
+    connect \Y $or$ls180.v:1680$46_Y
   end
-  attribute \src "ls180.v:1897.34-1897.90"
-  cell $or $or$ls180.v:1897$123
+  attribute \src "ls180.v:1882.34-1882.90"
+  cell $or $or$ls180.v:1882$91
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_start0
-    connect \B $ne$ls180.v:1897$122_Y
-    connect \Y $or$ls180.v:1897$123_Y
+    connect \B $ne$ls180.v:1882$90_Y
+    connect \Y $or$ls180.v:1882$91_Y
   end
-  attribute \src "ls180.v:1940.54-1940.125"
-  cell $or $or$ls180.v:1940$127
+  attribute \src "ls180.v:1925.54-1925.125"
+  cell $or $or$ls180.v:1925$95
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258820,10 +258336,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_req_wdata_ready
     connect \B \sdram_bankmachine0_req_rdata_valid
-    connect \Y $or$ls180.v:1940$127_Y
+    connect \Y $or$ls180.v:1925$95_Y
   end
-  attribute \src "ls180.v:1941.39-1941.136"
-  cell $or $or$ls180.v:1941$128
+  attribute \src "ls180.v:1926.39-1926.136"
+  cell $or $or$ls180.v:1926$96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258831,21 +258347,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine0_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:1941$128_Y
+    connect \Y $or$ls180.v:1926$96_Y
   end
-  attribute \src "ls180.v:1949.40-1949.155"
-  cell $or $or$ls180.v:1949$132
+  attribute \src "ls180.v:1934.40-1934.155"
+  cell $or $or$ls180.v:1934$100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:1949$131_Y
+    connect \A $sshl$ls180.v:1934$99_Y
     connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:1949$132_Y
+    connect \Y $or$ls180.v:1934$100_Y
   end
-  attribute \src "ls180.v:1986.117-1986.225"
-  cell $or $or$ls180.v:1986$145
+  attribute \src "ls180.v:1971.117-1971.225"
+  cell $or $or$ls180.v:1971$113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258853,21 +258369,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
     connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:1986$145_Y
+    connect \Y $or$ls180.v:1971$113_Y
   end
-  attribute \src "ls180.v:1992.52-1992.142"
-  cell $or $or$ls180.v:1992$151
+  attribute \src "ls180.v:1977.52-1977.142"
+  cell $or $or$ls180.v:1977$119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:1992$150_Y
+    connect \A $not$ls180.v:1977$118_Y
     connect \B \sdram_bankmachine0_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:1992$151_Y
+    connect \Y $or$ls180.v:1977$119_Y
   end
-  attribute \src "ls180.v:2097.54-2097.125"
-  cell $or $or$ls180.v:2097$157
+  attribute \src "ls180.v:2082.54-2082.125"
+  cell $or $or$ls180.v:2082$125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258875,10 +258391,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_req_wdata_ready
     connect \B \sdram_bankmachine1_req_rdata_valid
-    connect \Y $or$ls180.v:2097$157_Y
+    connect \Y $or$ls180.v:2082$125_Y
   end
-  attribute \src "ls180.v:2098.39-2098.136"
-  cell $or $or$ls180.v:2098$158
+  attribute \src "ls180.v:2083.39-2083.136"
+  cell $or $or$ls180.v:2083$126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258886,21 +258402,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine1_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:2098$158_Y
+    connect \Y $or$ls180.v:2083$126_Y
   end
-  attribute \src "ls180.v:2106.40-2106.155"
-  cell $or $or$ls180.v:2106$162
+  attribute \src "ls180.v:2091.40-2091.155"
+  cell $or $or$ls180.v:2091$130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:2106$161_Y
+    connect \A $sshl$ls180.v:2091$129_Y
     connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:2106$162_Y
+    connect \Y $or$ls180.v:2091$130_Y
   end
-  attribute \src "ls180.v:2143.117-2143.225"
-  cell $or $or$ls180.v:2143$175
+  attribute \src "ls180.v:2128.117-2128.225"
+  cell $or $or$ls180.v:2128$143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258908,21 +258424,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
     connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:2143$175_Y
+    connect \Y $or$ls180.v:2128$143_Y
   end
-  attribute \src "ls180.v:2149.52-2149.142"
-  cell $or $or$ls180.v:2149$181
+  attribute \src "ls180.v:2134.52-2134.142"
+  cell $or $or$ls180.v:2134$149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2149$180_Y
+    connect \A $not$ls180.v:2134$148_Y
     connect \B \sdram_bankmachine1_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:2149$181_Y
+    connect \Y $or$ls180.v:2134$149_Y
   end
-  attribute \src "ls180.v:2254.54-2254.125"
-  cell $or $or$ls180.v:2254$187
+  attribute \src "ls180.v:2239.54-2239.125"
+  cell $or $or$ls180.v:2239$155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258930,10 +258446,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_req_wdata_ready
     connect \B \sdram_bankmachine2_req_rdata_valid
-    connect \Y $or$ls180.v:2254$187_Y
+    connect \Y $or$ls180.v:2239$155_Y
   end
-  attribute \src "ls180.v:2255.39-2255.136"
-  cell $or $or$ls180.v:2255$188
+  attribute \src "ls180.v:2240.39-2240.136"
+  cell $or $or$ls180.v:2240$156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258941,21 +258457,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine2_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:2255$188_Y
+    connect \Y $or$ls180.v:2240$156_Y
   end
-  attribute \src "ls180.v:2263.40-2263.155"
-  cell $or $or$ls180.v:2263$192
+  attribute \src "ls180.v:2248.40-2248.155"
+  cell $or $or$ls180.v:2248$160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:2263$191_Y
+    connect \A $sshl$ls180.v:2248$159_Y
     connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:2263$192_Y
+    connect \Y $or$ls180.v:2248$160_Y
   end
-  attribute \src "ls180.v:2300.117-2300.225"
-  cell $or $or$ls180.v:2300$205
+  attribute \src "ls180.v:2285.117-2285.225"
+  cell $or $or$ls180.v:2285$173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258963,21 +258479,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
     connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:2300$205_Y
+    connect \Y $or$ls180.v:2285$173_Y
   end
-  attribute \src "ls180.v:2306.52-2306.142"
-  cell $or $or$ls180.v:2306$211
+  attribute \src "ls180.v:2291.52-2291.142"
+  cell $or $or$ls180.v:2291$179
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2306$210_Y
+    connect \A $not$ls180.v:2291$178_Y
     connect \B \sdram_bankmachine2_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:2306$211_Y
+    connect \Y $or$ls180.v:2291$179_Y
   end
-  attribute \src "ls180.v:2411.54-2411.125"
-  cell $or $or$ls180.v:2411$217
+  attribute \src "ls180.v:2396.54-2396.125"
+  cell $or $or$ls180.v:2396$185
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258985,10 +258501,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_req_wdata_ready
     connect \B \sdram_bankmachine3_req_rdata_valid
-    connect \Y $or$ls180.v:2411$217_Y
+    connect \Y $or$ls180.v:2396$185_Y
   end
-  attribute \src "ls180.v:2412.39-2412.136"
-  cell $or $or$ls180.v:2412$218
+  attribute \src "ls180.v:2397.39-2397.136"
+  cell $or $or$ls180.v:2397$186
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -258996,21 +258512,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
     connect \B \sdram_bankmachine3_cmd_buffer_source_valid
-    connect \Y $or$ls180.v:2412$218_Y
+    connect \Y $or$ls180.v:2397$186_Y
   end
-  attribute \src "ls180.v:2420.40-2420.155"
-  cell $or $or$ls180.v:2420$222
+  attribute \src "ls180.v:2405.40-2405.155"
+  cell $or $or$ls180.v:2405$190
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 13
     parameter \Y_WIDTH 13
-    connect \A $sshl$ls180.v:2420$221_Y
+    connect \A $sshl$ls180.v:2405$189_Y
     connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
-    connect \Y $or$ls180.v:2420$222_Y
+    connect \Y $or$ls180.v:2405$190_Y
   end
-  attribute \src "ls180.v:2457.117-2457.225"
-  cell $or $or$ls180.v:2457$235
+  attribute \src "ls180.v:2442.117-2442.225"
+  cell $or $or$ls180.v:2442$203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259018,21 +258534,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
     connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace
-    connect \Y $or$ls180.v:2457$235_Y
+    connect \Y $or$ls180.v:2442$203_Y
   end
-  attribute \src "ls180.v:2463.52-2463.142"
-  cell $or $or$ls180.v:2463$241
+  attribute \src "ls180.v:2448.52-2448.142"
+  cell $or $or$ls180.v:2448$209
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2463$240_Y
+    connect \A $not$ls180.v:2448$208_Y
     connect \B \sdram_bankmachine3_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:2463$241_Y
+    connect \Y $or$ls180.v:2448$209_Y
   end
-  attribute \src "ls180.v:2562.92-2562.168"
-  cell $or $or$ls180.v:2562$261
+  attribute \src "ls180.v:2547.92-2547.168"
+  cell $or $or$ls180.v:2547$229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259040,626 +258556,626 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_payload_is_write
     connect \B \sdram_choose_req_cmd_payload_is_read
-    connect \Y $or$ls180.v:2562$261_Y
+    connect \Y $or$ls180.v:2547$229_Y
   end
-  attribute \src "ls180.v:2565.34-2565.179"
-  cell $or $or$ls180.v:2565$267
+  attribute \src "ls180.v:2550.34-2550.179"
+  cell $or $or$ls180.v:2550$235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2565$265_Y
-    connect \B $and$ls180.v:2565$266_Y
-    connect \Y $or$ls180.v:2565$267_Y
+    connect \A $and$ls180.v:2550$233_Y
+    connect \B $and$ls180.v:2550$234_Y
+    connect \Y $or$ls180.v:2550$235_Y
   end
-  attribute \src "ls180.v:2565.33-2565.254"
-  cell $or $or$ls180.v:2565$269
+  attribute \src "ls180.v:2550.33-2550.254"
+  cell $or $or$ls180.v:2550$237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2565$267_Y
-    connect \B $and$ls180.v:2565$268_Y
-    connect \Y $or$ls180.v:2565$269_Y
+    connect \A $or$ls180.v:2550$235_Y
+    connect \B $and$ls180.v:2550$236_Y
+    connect \Y $or$ls180.v:2550$237_Y
   end
-  attribute \src "ls180.v:2565.32-2565.329"
-  cell $or $or$ls180.v:2565$271
+  attribute \src "ls180.v:2550.32-2550.329"
+  cell $or $or$ls180.v:2550$239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2565$269_Y
-    connect \B $and$ls180.v:2565$270_Y
-    connect \Y $or$ls180.v:2565$271_Y
+    connect \A $or$ls180.v:2550$237_Y
+    connect \B $and$ls180.v:2550$238_Y
+    connect \Y $or$ls180.v:2550$239_Y
   end
-  attribute \src "ls180.v:2566.35-2566.182"
-  cell $or $or$ls180.v:2566$274
+  attribute \src "ls180.v:2551.35-2551.182"
+  cell $or $or$ls180.v:2551$242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2566$272_Y
-    connect \B $and$ls180.v:2566$273_Y
-    connect \Y $or$ls180.v:2566$274_Y
+    connect \A $and$ls180.v:2551$240_Y
+    connect \B $and$ls180.v:2551$241_Y
+    connect \Y $or$ls180.v:2551$242_Y
   end
-  attribute \src "ls180.v:2566.34-2566.258"
-  cell $or $or$ls180.v:2566$276
+  attribute \src "ls180.v:2551.34-2551.258"
+  cell $or $or$ls180.v:2551$244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2566$274_Y
-    connect \B $and$ls180.v:2566$275_Y
-    connect \Y $or$ls180.v:2566$276_Y
+    connect \A $or$ls180.v:2551$242_Y
+    connect \B $and$ls180.v:2551$243_Y
+    connect \Y $or$ls180.v:2551$244_Y
   end
-  attribute \src "ls180.v:2566.33-2566.334"
-  cell $or $or$ls180.v:2566$278
+  attribute \src "ls180.v:2551.33-2551.334"
+  cell $or $or$ls180.v:2551$246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2566$276_Y
-    connect \B $and$ls180.v:2566$277_Y
-    connect \Y $or$ls180.v:2566$278_Y
+    connect \A $or$ls180.v:2551$244_Y
+    connect \B $and$ls180.v:2551$245_Y
+    connect \Y $or$ls180.v:2551$246_Y
   end
-  attribute \src "ls180.v:2579.138-2579.292"
-  cell $or $or$ls180.v:2579$292
+  attribute \src "ls180.v:2564.138-2564.292"
+  cell $or $or$ls180.v:2564$260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2579$291_Y
+    connect \A $not$ls180.v:2564$259_Y
     connect \B \sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:2579$292_Y
+    connect \Y $or$ls180.v:2564$260_Y
   end
-  attribute \src "ls180.v:2579.65-2579.446"
-  cell $or $or$ls180.v:2579$297
+  attribute \src "ls180.v:2564.65-2564.446"
+  cell $or $or$ls180.v:2564$265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2579$293_Y
-    connect \B $and$ls180.v:2579$296_Y
-    connect \Y $or$ls180.v:2579$297_Y
+    connect \A $and$ls180.v:2564$261_Y
+    connect \B $and$ls180.v:2564$264_Y
+    connect \Y $or$ls180.v:2564$265_Y
   end
-  attribute \src "ls180.v:2580.138-2580.292"
-  cell $or $or$ls180.v:2580$305
+  attribute \src "ls180.v:2565.138-2565.292"
+  cell $or $or$ls180.v:2565$273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2580$304_Y
+    connect \A $not$ls180.v:2565$272_Y
     connect \B \sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:2580$305_Y
+    connect \Y $or$ls180.v:2565$273_Y
   end
-  attribute \src "ls180.v:2580.65-2580.446"
-  cell $or $or$ls180.v:2580$310
+  attribute \src "ls180.v:2565.65-2565.446"
+  cell $or $or$ls180.v:2565$278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2580$306_Y
-    connect \B $and$ls180.v:2580$309_Y
-    connect \Y $or$ls180.v:2580$310_Y
+    connect \A $and$ls180.v:2565$274_Y
+    connect \B $and$ls180.v:2565$277_Y
+    connect \Y $or$ls180.v:2565$278_Y
   end
-  attribute \src "ls180.v:2581.138-2581.292"
-  cell $or $or$ls180.v:2581$318
+  attribute \src "ls180.v:2566.138-2566.292"
+  cell $or $or$ls180.v:2566$286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2581$317_Y
+    connect \A $not$ls180.v:2566$285_Y
     connect \B \sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:2581$318_Y
+    connect \Y $or$ls180.v:2566$286_Y
   end
-  attribute \src "ls180.v:2581.65-2581.446"
-  cell $or $or$ls180.v:2581$323
+  attribute \src "ls180.v:2566.65-2566.446"
+  cell $or $or$ls180.v:2566$291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2581$319_Y
-    connect \B $and$ls180.v:2581$322_Y
-    connect \Y $or$ls180.v:2581$323_Y
+    connect \A $and$ls180.v:2566$287_Y
+    connect \B $and$ls180.v:2566$290_Y
+    connect \Y $or$ls180.v:2566$291_Y
   end
-  attribute \src "ls180.v:2582.138-2582.292"
-  cell $or $or$ls180.v:2582$331
+  attribute \src "ls180.v:2567.138-2567.292"
+  cell $or $or$ls180.v:2567$299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2582$330_Y
+    connect \A $not$ls180.v:2567$298_Y
     connect \B \sdram_choose_cmd_want_activates
-    connect \Y $or$ls180.v:2582$331_Y
+    connect \Y $or$ls180.v:2567$299_Y
   end
-  attribute \src "ls180.v:2582.65-2582.446"
-  cell $or $or$ls180.v:2582$336
+  attribute \src "ls180.v:2567.65-2567.446"
+  cell $or $or$ls180.v:2567$304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2582$332_Y
-    connect \B $and$ls180.v:2582$335_Y
-    connect \Y $or$ls180.v:2582$336_Y
+    connect \A $and$ls180.v:2567$300_Y
+    connect \B $and$ls180.v:2567$303_Y
+    connect \Y $or$ls180.v:2567$304_Y
   end
-  attribute \src "ls180.v:2609.31-2609.89"
-  cell $or $or$ls180.v:2609$342
+  attribute \src "ls180.v:2594.31-2594.89"
+  cell $or $or$ls180.v:2594$310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_cmd_cmd_ready
-    connect \B $not$ls180.v:2609$341_Y
-    connect \Y $or$ls180.v:2609$342_Y
+    connect \B $not$ls180.v:2594$309_Y
+    connect \Y $or$ls180.v:2594$310_Y
   end
-  attribute \src "ls180.v:2612.138-2612.292"
-  cell $or $or$ls180.v:2612$350
+  attribute \src "ls180.v:2597.138-2597.292"
+  cell $or $or$ls180.v:2597$318
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2612$349_Y
+    connect \A $not$ls180.v:2597$317_Y
     connect \B \sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:2612$350_Y
+    connect \Y $or$ls180.v:2597$318_Y
   end
-  attribute \src "ls180.v:2612.65-2612.446"
-  cell $or $or$ls180.v:2612$355
+  attribute \src "ls180.v:2597.65-2597.446"
+  cell $or $or$ls180.v:2597$323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2612$351_Y
-    connect \B $and$ls180.v:2612$354_Y
-    connect \Y $or$ls180.v:2612$355_Y
+    connect \A $and$ls180.v:2597$319_Y
+    connect \B $and$ls180.v:2597$322_Y
+    connect \Y $or$ls180.v:2597$323_Y
   end
-  attribute \src "ls180.v:2613.138-2613.292"
-  cell $or $or$ls180.v:2613$363
+  attribute \src "ls180.v:2598.138-2598.292"
+  cell $or $or$ls180.v:2598$331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2613$362_Y
+    connect \A $not$ls180.v:2598$330_Y
     connect \B \sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:2613$363_Y
+    connect \Y $or$ls180.v:2598$331_Y
   end
-  attribute \src "ls180.v:2613.65-2613.446"
-  cell $or $or$ls180.v:2613$368
+  attribute \src "ls180.v:2598.65-2598.446"
+  cell $or $or$ls180.v:2598$336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2613$364_Y
-    connect \B $and$ls180.v:2613$367_Y
-    connect \Y $or$ls180.v:2613$368_Y
+    connect \A $and$ls180.v:2598$332_Y
+    connect \B $and$ls180.v:2598$335_Y
+    connect \Y $or$ls180.v:2598$336_Y
   end
-  attribute \src "ls180.v:2614.138-2614.292"
-  cell $or $or$ls180.v:2614$376
+  attribute \src "ls180.v:2599.138-2599.292"
+  cell $or $or$ls180.v:2599$344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2614$375_Y
+    connect \A $not$ls180.v:2599$343_Y
     connect \B \sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:2614$376_Y
+    connect \Y $or$ls180.v:2599$344_Y
   end
-  attribute \src "ls180.v:2614.65-2614.446"
-  cell $or $or$ls180.v:2614$381
+  attribute \src "ls180.v:2599.65-2599.446"
+  cell $or $or$ls180.v:2599$349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2614$377_Y
-    connect \B $and$ls180.v:2614$380_Y
-    connect \Y $or$ls180.v:2614$381_Y
+    connect \A $and$ls180.v:2599$345_Y
+    connect \B $and$ls180.v:2599$348_Y
+    connect \Y $or$ls180.v:2599$349_Y
   end
-  attribute \src "ls180.v:2615.138-2615.292"
-  cell $or $or$ls180.v:2615$389
+  attribute \src "ls180.v:2600.138-2600.292"
+  cell $or $or$ls180.v:2600$357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2615$388_Y
+    connect \A $not$ls180.v:2600$356_Y
     connect \B \sdram_choose_req_want_activates
-    connect \Y $or$ls180.v:2615$389_Y
+    connect \Y $or$ls180.v:2600$357_Y
   end
-  attribute \src "ls180.v:2615.65-2615.446"
-  cell $or $or$ls180.v:2615$394
+  attribute \src "ls180.v:2600.65-2600.446"
+  cell $or $or$ls180.v:2600$362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2615$390_Y
-    connect \B $and$ls180.v:2615$393_Y
-    connect \Y $or$ls180.v:2615$394_Y
+    connect \A $and$ls180.v:2600$358_Y
+    connect \B $and$ls180.v:2600$361_Y
+    connect \Y $or$ls180.v:2600$362_Y
   end
-  attribute \src "ls180.v:2678.31-2678.89"
-  cell $or $or$ls180.v:2678$428
+  attribute \src "ls180.v:2663.31-2663.89"
+  cell $or $or$ls180.v:2663$396
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \sdram_choose_req_cmd_ready
-    connect \B $not$ls180.v:2678$427_Y
-    connect \Y $or$ls180.v:2678$428_Y
+    connect \B $not$ls180.v:2663$395_Y
+    connect \Y $or$ls180.v:2663$396_Y
   end
-  attribute \src "ls180.v:2699.57-2699.191"
-  cell $or $or$ls180.v:2699$435
+  attribute \src "ls180.v:2684.57-2684.191"
+  cell $or $or$ls180.v:2684$403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2699$434_Y
+    connect \A $not$ls180.v:2684$402_Y
     connect \B \sdram_ras_allowed
-    connect \Y $or$ls180.v:2699$435_Y
+    connect \Y $or$ls180.v:2684$403_Y
   end
-  attribute \src "ls180.v:2707.10-2707.52"
-  cell $or $or$ls180.v:2707$438
+  attribute \src "ls180.v:2692.10-2692.52"
+  cell $or $or$ls180.v:2692$406
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2707$437_Y
+    connect \A $not$ls180.v:2692$405_Y
     connect \B \sdram_max_time1
-    connect \Y $or$ls180.v:2707$438_Y
+    connect \Y $or$ls180.v:2692$406_Y
   end
-  attribute \src "ls180.v:2737.57-2737.191"
-  cell $or $or$ls180.v:2737$444
+  attribute \src "ls180.v:2722.57-2722.191"
+  cell $or $or$ls180.v:2722$412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2737$443_Y
+    connect \A $not$ls180.v:2722$411_Y
     connect \B \sdram_ras_allowed
-    connect \Y $or$ls180.v:2737$444_Y
+    connect \Y $or$ls180.v:2722$412_Y
   end
-  attribute \src "ls180.v:2745.10-2745.51"
-  cell $or $or$ls180.v:2745$447
+  attribute \src "ls180.v:2730.10-2730.51"
+  cell $or $or$ls180.v:2730$415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2745$446_Y
+    connect \A $not$ls180.v:2730$414_Y
     connect \B \sdram_max_time0
-    connect \Y $or$ls180.v:2745$447_Y
+    connect \Y $or$ls180.v:2730$415_Y
   end
-  attribute \src "ls180.v:2755.91-2755.185"
-  cell $or $or$ls180.v:2755$451
+  attribute \src "ls180.v:2740.91-2740.185"
+  cell $or $or$ls180.v:2740$419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked0
-    connect \B $and$ls180.v:2755$450_Y
-    connect \Y $or$ls180.v:2755$451_Y
+    connect \B $and$ls180.v:2740$418_Y
+    connect \Y $or$ls180.v:2740$419_Y
   end
-  attribute \src "ls180.v:2755.90-2755.260"
-  cell $or $or$ls180.v:2755$454
+  attribute \src "ls180.v:2740.90-2740.260"
+  cell $or $or$ls180.v:2740$422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2755$451_Y
-    connect \B $and$ls180.v:2755$453_Y
-    connect \Y $or$ls180.v:2755$454_Y
+    connect \A $or$ls180.v:2740$419_Y
+    connect \B $and$ls180.v:2740$421_Y
+    connect \Y $or$ls180.v:2740$422_Y
   end
-  attribute \src "ls180.v:2755.89-2755.335"
-  cell $or $or$ls180.v:2755$457
+  attribute \src "ls180.v:2740.89-2740.335"
+  cell $or $or$ls180.v:2740$425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2755$454_Y
-    connect \B $and$ls180.v:2755$456_Y
-    connect \Y $or$ls180.v:2755$457_Y
+    connect \A $or$ls180.v:2740$422_Y
+    connect \B $and$ls180.v:2740$424_Y
+    connect \Y $or$ls180.v:2740$425_Y
   end
-  attribute \src "ls180.v:2760.91-2760.185"
-  cell $or $or$ls180.v:2760$467
+  attribute \src "ls180.v:2745.91-2745.185"
+  cell $or $or$ls180.v:2745$435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked1
-    connect \B $and$ls180.v:2760$466_Y
-    connect \Y $or$ls180.v:2760$467_Y
+    connect \B $and$ls180.v:2745$434_Y
+    connect \Y $or$ls180.v:2745$435_Y
   end
-  attribute \src "ls180.v:2760.90-2760.260"
-  cell $or $or$ls180.v:2760$470
+  attribute \src "ls180.v:2745.90-2745.260"
+  cell $or $or$ls180.v:2745$438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2760$467_Y
-    connect \B $and$ls180.v:2760$469_Y
-    connect \Y $or$ls180.v:2760$470_Y
+    connect \A $or$ls180.v:2745$435_Y
+    connect \B $and$ls180.v:2745$437_Y
+    connect \Y $or$ls180.v:2745$438_Y
   end
-  attribute \src "ls180.v:2760.89-2760.335"
-  cell $or $or$ls180.v:2760$473
+  attribute \src "ls180.v:2745.89-2745.335"
+  cell $or $or$ls180.v:2745$441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2760$470_Y
-    connect \B $and$ls180.v:2760$472_Y
-    connect \Y $or$ls180.v:2760$473_Y
+    connect \A $or$ls180.v:2745$438_Y
+    connect \B $and$ls180.v:2745$440_Y
+    connect \Y $or$ls180.v:2745$441_Y
   end
-  attribute \src "ls180.v:2765.91-2765.185"
-  cell $or $or$ls180.v:2765$483
+  attribute \src "ls180.v:2750.91-2750.185"
+  cell $or $or$ls180.v:2750$451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked2
-    connect \B $and$ls180.v:2765$482_Y
-    connect \Y $or$ls180.v:2765$483_Y
+    connect \B $and$ls180.v:2750$450_Y
+    connect \Y $or$ls180.v:2750$451_Y
   end
-  attribute \src "ls180.v:2765.90-2765.260"
-  cell $or $or$ls180.v:2765$486
+  attribute \src "ls180.v:2750.90-2750.260"
+  cell $or $or$ls180.v:2750$454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2765$483_Y
-    connect \B $and$ls180.v:2765$485_Y
-    connect \Y $or$ls180.v:2765$486_Y
+    connect \A $or$ls180.v:2750$451_Y
+    connect \B $and$ls180.v:2750$453_Y
+    connect \Y $or$ls180.v:2750$454_Y
   end
-  attribute \src "ls180.v:2765.89-2765.335"
-  cell $or $or$ls180.v:2765$489
+  attribute \src "ls180.v:2750.89-2750.335"
+  cell $or $or$ls180.v:2750$457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2765$486_Y
-    connect \B $and$ls180.v:2765$488_Y
-    connect \Y $or$ls180.v:2765$489_Y
+    connect \A $or$ls180.v:2750$454_Y
+    connect \B $and$ls180.v:2750$456_Y
+    connect \Y $or$ls180.v:2750$457_Y
   end
-  attribute \src "ls180.v:2770.91-2770.185"
-  cell $or $or$ls180.v:2770$499
+  attribute \src "ls180.v:2755.91-2755.185"
+  cell $or $or$ls180.v:2755$467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked3
-    connect \B $and$ls180.v:2770$498_Y
-    connect \Y $or$ls180.v:2770$499_Y
+    connect \B $and$ls180.v:2755$466_Y
+    connect \Y $or$ls180.v:2755$467_Y
   end
-  attribute \src "ls180.v:2770.90-2770.260"
-  cell $or $or$ls180.v:2770$502
+  attribute \src "ls180.v:2755.90-2755.260"
+  cell $or $or$ls180.v:2755$470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2770$499_Y
-    connect \B $and$ls180.v:2770$501_Y
-    connect \Y $or$ls180.v:2770$502_Y
+    connect \A $or$ls180.v:2755$467_Y
+    connect \B $and$ls180.v:2755$469_Y
+    connect \Y $or$ls180.v:2755$470_Y
   end
-  attribute \src "ls180.v:2770.89-2770.335"
-  cell $or $or$ls180.v:2770$505
+  attribute \src "ls180.v:2755.89-2755.335"
+  cell $or $or$ls180.v:2755$473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2770$502_Y
-    connect \B $and$ls180.v:2770$504_Y
-    connect \Y $or$ls180.v:2770$505_Y
+    connect \A $or$ls180.v:2755$470_Y
+    connect \B $and$ls180.v:2755$472_Y
+    connect \Y $or$ls180.v:2755$473_Y
   end
-  attribute \src "ls180.v:2775.127-2775.221"
-  cell $or $or$ls180.v:2775$516
+  attribute \src "ls180.v:2760.127-2760.221"
+  cell $or $or$ls180.v:2760$484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked0
-    connect \B $and$ls180.v:2775$515_Y
-    connect \Y $or$ls180.v:2775$516_Y
+    connect \B $and$ls180.v:2760$483_Y
+    connect \Y $or$ls180.v:2760$484_Y
   end
-  attribute \src "ls180.v:2775.126-2775.296"
-  cell $or $or$ls180.v:2775$519
+  attribute \src "ls180.v:2760.126-2760.296"
+  cell $or $or$ls180.v:2760$487
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$516_Y
-    connect \B $and$ls180.v:2775$518_Y
-    connect \Y $or$ls180.v:2775$519_Y
+    connect \A $or$ls180.v:2760$484_Y
+    connect \B $and$ls180.v:2760$486_Y
+    connect \Y $or$ls180.v:2760$487_Y
   end
-  attribute \src "ls180.v:2775.125-2775.371"
-  cell $or $or$ls180.v:2775$522
+  attribute \src "ls180.v:2760.125-2760.371"
+  cell $or $or$ls180.v:2760$490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$519_Y
-    connect \B $and$ls180.v:2775$521_Y
-    connect \Y $or$ls180.v:2775$522_Y
+    connect \A $or$ls180.v:2760$487_Y
+    connect \B $and$ls180.v:2760$489_Y
+    connect \Y $or$ls180.v:2760$490_Y
   end
-  attribute \src "ls180.v:2775.29-2775.406"
-  cell $or $or$ls180.v:2775$527
+  attribute \src "ls180.v:2760.29-2760.406"
+  cell $or $or$ls180.v:2760$495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:2775$526_Y
-    connect \Y $or$ls180.v:2775$527_Y
+    connect \B $and$ls180.v:2760$494_Y
+    connect \Y $or$ls180.v:2760$495_Y
   end
-  attribute \src "ls180.v:2775.501-2775.595"
-  cell $or $or$ls180.v:2775$532
+  attribute \src "ls180.v:2760.501-2760.595"
+  cell $or $or$ls180.v:2760$500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked1
-    connect \B $and$ls180.v:2775$531_Y
-    connect \Y $or$ls180.v:2775$532_Y
+    connect \B $and$ls180.v:2760$499_Y
+    connect \Y $or$ls180.v:2760$500_Y
   end
-  attribute \src "ls180.v:2775.500-2775.670"
-  cell $or $or$ls180.v:2775$535
+  attribute \src "ls180.v:2760.500-2760.670"
+  cell $or $or$ls180.v:2760$503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$532_Y
-    connect \B $and$ls180.v:2775$534_Y
-    connect \Y $or$ls180.v:2775$535_Y
+    connect \A $or$ls180.v:2760$500_Y
+    connect \B $and$ls180.v:2760$502_Y
+    connect \Y $or$ls180.v:2760$503_Y
   end
-  attribute \src "ls180.v:2775.499-2775.745"
-  cell $or $or$ls180.v:2775$538
+  attribute \src "ls180.v:2760.499-2760.745"
+  cell $or $or$ls180.v:2760$506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$535_Y
-    connect \B $and$ls180.v:2775$537_Y
-    connect \Y $or$ls180.v:2775$538_Y
+    connect \A $or$ls180.v:2760$503_Y
+    connect \B $and$ls180.v:2760$505_Y
+    connect \Y $or$ls180.v:2760$506_Y
   end
-  attribute \src "ls180.v:2775.28-2775.780"
-  cell $or $or$ls180.v:2775$543
+  attribute \src "ls180.v:2760.28-2760.780"
+  cell $or $or$ls180.v:2760$511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$527_Y
-    connect \B $and$ls180.v:2775$542_Y
-    connect \Y $or$ls180.v:2775$543_Y
+    connect \A $or$ls180.v:2760$495_Y
+    connect \B $and$ls180.v:2760$510_Y
+    connect \Y $or$ls180.v:2760$511_Y
   end
-  attribute \src "ls180.v:2775.875-2775.969"
-  cell $or $or$ls180.v:2775$548
+  attribute \src "ls180.v:2760.875-2760.969"
+  cell $or $or$ls180.v:2760$516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked2
-    connect \B $and$ls180.v:2775$547_Y
-    connect \Y $or$ls180.v:2775$548_Y
+    connect \B $and$ls180.v:2760$515_Y
+    connect \Y $or$ls180.v:2760$516_Y
   end
-  attribute \src "ls180.v:2775.874-2775.1044"
-  cell $or $or$ls180.v:2775$551
+  attribute \src "ls180.v:2760.874-2760.1044"
+  cell $or $or$ls180.v:2760$519
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$548_Y
-    connect \B $and$ls180.v:2775$550_Y
-    connect \Y $or$ls180.v:2775$551_Y
+    connect \A $or$ls180.v:2760$516_Y
+    connect \B $and$ls180.v:2760$518_Y
+    connect \Y $or$ls180.v:2760$519_Y
   end
-  attribute \src "ls180.v:2775.873-2775.1119"
-  cell $or $or$ls180.v:2775$554
+  attribute \src "ls180.v:2760.873-2760.1119"
+  cell $or $or$ls180.v:2760$522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$551_Y
-    connect \B $and$ls180.v:2775$553_Y
-    connect \Y $or$ls180.v:2775$554_Y
+    connect \A $or$ls180.v:2760$519_Y
+    connect \B $and$ls180.v:2760$521_Y
+    connect \Y $or$ls180.v:2760$522_Y
   end
-  attribute \src "ls180.v:2775.27-2775.1154"
-  cell $or $or$ls180.v:2775$559
+  attribute \src "ls180.v:2760.27-2760.1154"
+  cell $or $or$ls180.v:2760$527
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$543_Y
-    connect \B $and$ls180.v:2775$558_Y
-    connect \Y $or$ls180.v:2775$559_Y
+    connect \A $or$ls180.v:2760$511_Y
+    connect \B $and$ls180.v:2760$526_Y
+    connect \Y $or$ls180.v:2760$527_Y
   end
-  attribute \src "ls180.v:2775.1249-2775.1343"
-  cell $or $or$ls180.v:2775$564
+  attribute \src "ls180.v:2760.1249-2760.1343"
+  cell $or $or$ls180.v:2760$532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked3
-    connect \B $and$ls180.v:2775$563_Y
-    connect \Y $or$ls180.v:2775$564_Y
+    connect \B $and$ls180.v:2760$531_Y
+    connect \Y $or$ls180.v:2760$532_Y
   end
-  attribute \src "ls180.v:2775.1248-2775.1418"
-  cell $or $or$ls180.v:2775$567
+  attribute \src "ls180.v:2760.1248-2760.1418"
+  cell $or $or$ls180.v:2760$535
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$564_Y
-    connect \B $and$ls180.v:2775$566_Y
-    connect \Y $or$ls180.v:2775$567_Y
+    connect \A $or$ls180.v:2760$532_Y
+    connect \B $and$ls180.v:2760$534_Y
+    connect \Y $or$ls180.v:2760$535_Y
   end
-  attribute \src "ls180.v:2775.1247-2775.1493"
-  cell $or $or$ls180.v:2775$570
+  attribute \src "ls180.v:2760.1247-2760.1493"
+  cell $or $or$ls180.v:2760$538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$567_Y
-    connect \B $and$ls180.v:2775$569_Y
-    connect \Y $or$ls180.v:2775$570_Y
+    connect \A $or$ls180.v:2760$535_Y
+    connect \B $and$ls180.v:2760$537_Y
+    connect \Y $or$ls180.v:2760$538_Y
   end
-  attribute \src "ls180.v:2775.26-2775.1528"
-  cell $or $or$ls180.v:2775$575
+  attribute \src "ls180.v:2760.26-2760.1528"
+  cell $or $or$ls180.v:2760$543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:2775$559_Y
-    connect \B $and$ls180.v:2775$574_Y
-    connect \Y $or$ls180.v:2775$575_Y
+    connect \A $or$ls180.v:2760$527_Y
+    connect \B $and$ls180.v:2760$542_Y
+    connect \Y $or$ls180.v:2760$543_Y
   end
-  attribute \src "ls180.v:2838.10-2838.42"
-  cell $or $or$ls180.v:2838$584
+  attribute \src "ls180.v:2823.10-2823.42"
+  cell $or $or$ls180.v:2823$552
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259667,10 +259183,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_ack
     connect \B \converter_skip
-    connect \Y $or$ls180.v:2838$584_Y
+    connect \Y $or$ls180.v:2823$552_Y
   end
-  attribute \src "ls180.v:2865.30-2865.59"
-  cell $or $or$ls180.v:2865$594
+  attribute \src "ls180.v:2850.30-2850.59"
+  cell $or $or$ls180.v:2850$562
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259678,10 +259194,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_valid
     connect \B \cmd_consumed
-    connect \Y $or$ls180.v:2865$594_Y
+    connect \Y $or$ls180.v:2850$562_Y
   end
-  attribute \src "ls180.v:2866.29-2866.58"
-  cell $or $or$ls180.v:2866$598
+  attribute \src "ls180.v:2851.29-2851.58"
+  cell $or $or$ls180.v:2851$566
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259689,76 +259205,76 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \port_cmd_valid
     connect \B \cmd_consumed
-    connect \Y $or$ls180.v:2866$598_Y
+    connect \Y $or$ls180.v:2851$566_Y
   end
-  attribute \src "ls180.v:2867.38-2867.100"
-  cell $or $or$ls180.v:2867$604
+  attribute \src "ls180.v:2852.38-2852.100"
+  cell $or $or$ls180.v:2852$572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2867$601_Y
-    connect \B $and$ls180.v:2867$603_Y
-    connect \Y $or$ls180.v:2867$604_Y
+    connect \A $and$ls180.v:2852$569_Y
+    connect \B $and$ls180.v:2852$571_Y
+    connect \Y $or$ls180.v:2852$572_Y
   end
-  attribute \src "ls180.v:2868.19-2868.67"
-  cell $or $or$ls180.v:2868$607
+  attribute \src "ls180.v:2853.19-2853.67"
+  cell $or $or$ls180.v:2853$575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2868$606_Y
+    connect \A $and$ls180.v:2853$574_Y
     connect \B \cmd_consumed
-    connect \Y $or$ls180.v:2868$607_Y
+    connect \Y $or$ls180.v:2853$575_Y
   end
-  attribute \src "ls180.v:2869.21-2869.75"
-  cell $or $or$ls180.v:2869$609
+  attribute \src "ls180.v:2854.21-2854.75"
+  cell $or $or$ls180.v:2854$577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2869$608_Y
+    connect \A $and$ls180.v:2854$576_Y
     connect \B \wdata_consumed
-    connect \Y $or$ls180.v:2869$609_Y
+    connect \Y $or$ls180.v:2854$577_Y
   end
-  attribute \src "ls180.v:2899.32-2899.59"
-  cell $or $or$ls180.v:2899$617
+  attribute \src "ls180.v:2884.32-2884.59"
+  cell $or $or$ls180.v:2884$585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rx_clear
-    connect \B $and$ls180.v:2899$616_Y
-    connect \Y $or$ls180.v:2899$617_Y
+    connect \B $and$ls180.v:2884$584_Y
+    connect \Y $or$ls180.v:2884$585_Y
   end
-  attribute \src "ls180.v:2923.15-2923.124"
-  cell $or $or$ls180.v:2923$627
+  attribute \src "ls180.v:2908.15-2908.124"
+  cell $or $or$ls180.v:2908$595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $and$ls180.v:2923$625_Y
-    connect \B $and$ls180.v:2923$626_Y
-    connect \Y $or$ls180.v:2923$627_Y
+    connect \A $and$ls180.v:2908$593_Y
+    connect \B $and$ls180.v:2908$594_Y
+    connect \Y $or$ls180.v:2908$595_Y
   end
-  attribute \src "ls180.v:2938.60-2938.92"
-  cell $or $or$ls180.v:2938$629
+  attribute \src "ls180.v:2923.60-2923.92"
+  cell $or $or$ls180.v:2923$597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2938$628_Y
+    connect \A $not$ls180.v:2923$596_Y
     connect \B \tx_fifo_re
-    connect \Y $or$ls180.v:2938$629_Y
+    connect \Y $or$ls180.v:2923$597_Y
   end
-  attribute \src "ls180.v:2949.52-2949.95"
-  cell $or $or$ls180.v:2949$634
+  attribute \src "ls180.v:2934.52-2934.95"
+  cell $or $or$ls180.v:2934$602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259766,21 +259282,21 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \tx_fifo_syncfifo_writable
     connect \B \tx_fifo_replace
-    connect \Y $or$ls180.v:2949$634_Y
+    connect \Y $or$ls180.v:2934$602_Y
   end
-  attribute \src "ls180.v:2968.60-2968.92"
-  cell $or $or$ls180.v:2968$640
+  attribute \src "ls180.v:2953.60-2953.92"
+  cell $or $or$ls180.v:2953$608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:2968$639_Y
+    connect \A $not$ls180.v:2953$607_Y
     connect \B \rx_fifo_re
-    connect \Y $or$ls180.v:2968$640_Y
+    connect \Y $or$ls180.v:2953$608_Y
   end
-  attribute \src "ls180.v:2979.52-2979.95"
-  cell $or $or$ls180.v:2979$645
+  attribute \src "ls180.v:2964.52-2964.95"
+  cell $or $or$ls180.v:2964$613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259788,10 +259304,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \rx_fifo_syncfifo_writable
     connect \B \rx_fifo_replace
-    connect \Y $or$ls180.v:2979$645_Y
+    connect \Y $or$ls180.v:2964$613_Y
   end
-  attribute \src "ls180.v:3162.38-3162.83"
-  cell $or $or$ls180.v:3162$683
+  attribute \src "ls180.v:3147.38-3147.83"
+  cell $or $or$ls180.v:3147$651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259799,54 +259315,54 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_err
     connect \B \ram_bus_ram_bus_err
-    connect \Y $or$ls180.v:3162$683_Y
+    connect \Y $or$ls180.v:3147$651_Y
   end
-  attribute \src "ls180.v:3162.37-3162.121"
-  cell $or $or$ls180.v:3162$684
+  attribute \src "ls180.v:3147.37-3147.120"
+  cell $or $or$ls180.v:3147$652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3162$683_Y
-    connect \B \interface0_converted_interface_err
-    connect \Y $or$ls180.v:3162$684_Y
+    connect \A $or$ls180.v:3147$651_Y
+    connect \B \libresocsim_libresoc_xics_icp_err
+    connect \Y $or$ls180.v:3147$652_Y
   end
-  attribute \src "ls180.v:3162.36-3162.159"
-  cell $or $or$ls180.v:3162$685
+  attribute \src "ls180.v:3147.36-3147.157"
+  cell $or $or$ls180.v:3147$653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3162$684_Y
-    connect \B \interface1_converted_interface_err
-    connect \Y $or$ls180.v:3162$685_Y
+    connect \A $or$ls180.v:3147$652_Y
+    connect \B \libresocsim_libresoc_xics_ics_err
+    connect \Y $or$ls180.v:3147$653_Y
   end
-  attribute \src "ls180.v:3162.35-3162.200"
-  cell $or $or$ls180.v:3162$686
+  attribute \src "ls180.v:3147.35-3147.173"
+  cell $or $or$ls180.v:3147$654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3162$685_Y
-    connect \B \socbushandler_converted_interface_err
-    connect \Y $or$ls180.v:3162$686_Y
+    connect \A $or$ls180.v:3147$653_Y
+    connect \B \wb_sdram_err
+    connect \Y $or$ls180.v:3147$654_Y
   end
-  attribute \src "ls180.v:3162.34-3162.251"
-  cell $or $or$ls180.v:3162$687
+  attribute \src "ls180.v:3147.34-3147.213"
+  cell $or $or$ls180.v:3147$655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3162$686_Y
-    connect \B \libresocsim_libresocsim_converted_interface_err
-    connect \Y $or$ls180.v:3162$687_Y
+    connect \A $or$ls180.v:3147$654_Y
+    connect \B \libresocsim_libresocsim_wishbone_err
+    connect \Y $or$ls180.v:3147$655_Y
   end
-  attribute \src "ls180.v:3168.33-3168.78"
-  cell $or $or$ls180.v:3168$692
+  attribute \src "ls180.v:3153.33-3153.78"
+  cell $or $or$ls180.v:3153$660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -259854,109 +259370,109 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \libresocsim_ram_bus_ack
     connect \B \ram_bus_ram_bus_ack
-    connect \Y $or$ls180.v:3168$692_Y
+    connect \Y $or$ls180.v:3153$660_Y
   end
-  attribute \src "ls180.v:3168.32-3168.116"
-  cell $or $or$ls180.v:3168$693
+  attribute \src "ls180.v:3153.32-3153.115"
+  cell $or $or$ls180.v:3153$661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3168$692_Y
-    connect \B \interface0_converted_interface_ack
-    connect \Y $or$ls180.v:3168$693_Y
+    connect \A $or$ls180.v:3153$660_Y
+    connect \B \libresocsim_libresoc_xics_icp_ack
+    connect \Y $or$ls180.v:3153$661_Y
   end
-  attribute \src "ls180.v:3168.31-3168.154"
-  cell $or $or$ls180.v:3168$694
+  attribute \src "ls180.v:3153.31-3153.152"
+  cell $or $or$ls180.v:3153$662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3168$693_Y
-    connect \B \interface1_converted_interface_ack
-    connect \Y $or$ls180.v:3168$694_Y
+    connect \A $or$ls180.v:3153$661_Y
+    connect \B \libresocsim_libresoc_xics_ics_ack
+    connect \Y $or$ls180.v:3153$662_Y
   end
-  attribute \src "ls180.v:3168.30-3168.195"
-  cell $or $or$ls180.v:3168$695
+  attribute \src "ls180.v:3153.30-3153.168"
+  cell $or $or$ls180.v:3153$663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3168$694_Y
-    connect \B \socbushandler_converted_interface_ack
-    connect \Y $or$ls180.v:3168$695_Y
+    connect \A $or$ls180.v:3153$662_Y
+    connect \B \wb_sdram_ack
+    connect \Y $or$ls180.v:3153$663_Y
   end
-  attribute \src "ls180.v:3168.29-3168.246"
-  cell $or $or$ls180.v:3168$696
+  attribute \src "ls180.v:3153.29-3153.208"
+  cell $or $or$ls180.v:3153$664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3168$695_Y
-    connect \B \libresocsim_libresocsim_converted_interface_ack
-    connect \Y $or$ls180.v:3168$696_Y
+    connect \A $or$ls180.v:3153$663_Y
+    connect \B \libresocsim_libresocsim_wishbone_ack
+    connect \Y $or$ls180.v:3153$664_Y
   end
-  attribute \src "ls180.v:3169.35-3169.158"
-  cell $or $or$ls180.v:3169$699
+  attribute \src "ls180.v:3154.35-3154.158"
+  cell $or $or$ls180.v:3154$667
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $and$ls180.v:3169$697_Y
-    connect \B $and$ls180.v:3169$698_Y
-    connect \Y $or$ls180.v:3169$699_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $and$ls180.v:3154$665_Y
+    connect \B $and$ls180.v:3154$666_Y
+    connect \Y $or$ls180.v:3154$667_Y
   end
-  attribute \src "ls180.v:3169.34-3169.235"
-  cell $or $or$ls180.v:3169$701
+  attribute \src "ls180.v:3154.34-3154.234"
+  cell $or $or$ls180.v:3154$669
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $or$ls180.v:3169$699_Y
-    connect \B $and$ls180.v:3169$700_Y
-    connect \Y $or$ls180.v:3169$701_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:3154$667_Y
+    connect \B $and$ls180.v:3154$668_Y
+    connect \Y $or$ls180.v:3154$669_Y
   end
-  attribute \src "ls180.v:3169.33-3169.312"
-  cell $or $or$ls180.v:3169$703
+  attribute \src "ls180.v:3154.33-3154.310"
+  cell $or $or$ls180.v:3154$671
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $or$ls180.v:3169$701_Y
-    connect \B $and$ls180.v:3169$702_Y
-    connect \Y $or$ls180.v:3169$703_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:3154$669_Y
+    connect \B $and$ls180.v:3154$670_Y
+    connect \Y $or$ls180.v:3154$671_Y
   end
-  attribute \src "ls180.v:3169.32-3169.392"
-  cell $or $or$ls180.v:3169$705
+  attribute \src "ls180.v:3154.32-3154.365"
+  cell $or $or$ls180.v:3154$673
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $or$ls180.v:3169$703_Y
-    connect \B $and$ls180.v:3169$704_Y
-    connect \Y $or$ls180.v:3169$705_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:3154$671_Y
+    connect \B $and$ls180.v:3154$672_Y
+    connect \Y $or$ls180.v:3154$673_Y
   end
-  attribute \src "ls180.v:3169.31-3169.482"
-  cell $or $or$ls180.v:3169$707
+  attribute \src "ls180.v:3154.31-3154.444"
+  cell $or $or$ls180.v:3154$675
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 32
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $or$ls180.v:3169$705_Y
-    connect \B $and$ls180.v:3169$706_Y
-    connect \Y $or$ls180.v:3169$707_Y
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A $or$ls180.v:3154$673_Y
+    connect \B $and$ls180.v:3154$674_Y
+    connect \Y $or$ls180.v:3154$675_Y
   end
-  attribute \src "ls180.v:3449.52-3449.129"
-  cell $or $or$ls180.v:3449$1109
+  attribute \src "ls180.v:3434.52-3434.129"
+  cell $or $or$ls180.v:3434$1077
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -259964,208 +259480,208 @@ module \ls180
     parameter \Y_WIDTH 8
     connect \A \libresocsim_interface0_bank_bus_dat_r
     connect \B \libresocsim_interface1_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1109_Y
+    connect \Y $or$ls180.v:3434$1077_Y
   end
-  attribute \src "ls180.v:3449.51-3449.170"
-  cell $or $or$ls180.v:3449$1110
+  attribute \src "ls180.v:3434.51-3434.170"
+  cell $or $or$ls180.v:3434$1078
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1109_Y
+    connect \A $or$ls180.v:3434$1077_Y
     connect \B \libresocsim_interface2_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1110_Y
+    connect \Y $or$ls180.v:3434$1078_Y
   end
-  attribute \src "ls180.v:3449.50-3449.211"
-  cell $or $or$ls180.v:3449$1111
+  attribute \src "ls180.v:3434.50-3434.211"
+  cell $or $or$ls180.v:3434$1079
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1110_Y
+    connect \A $or$ls180.v:3434$1078_Y
     connect \B \libresocsim_interface3_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1111_Y
+    connect \Y $or$ls180.v:3434$1079_Y
   end
-  attribute \src "ls180.v:3449.49-3449.252"
-  cell $or $or$ls180.v:3449$1112
+  attribute \src "ls180.v:3434.49-3434.252"
+  cell $or $or$ls180.v:3434$1080
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1111_Y
+    connect \A $or$ls180.v:3434$1079_Y
     connect \B \libresocsim_interface4_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1112_Y
+    connect \Y $or$ls180.v:3434$1080_Y
   end
-  attribute \src "ls180.v:3449.48-3449.293"
-  cell $or $or$ls180.v:3449$1113
+  attribute \src "ls180.v:3434.48-3434.293"
+  cell $or $or$ls180.v:3434$1081
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1112_Y
+    connect \A $or$ls180.v:3434$1080_Y
     connect \B \libresocsim_interface5_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1113_Y
+    connect \Y $or$ls180.v:3434$1081_Y
   end
-  attribute \src "ls180.v:3449.47-3449.334"
-  cell $or $or$ls180.v:3449$1114
+  attribute \src "ls180.v:3434.47-3434.334"
+  cell $or $or$ls180.v:3434$1082
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1113_Y
+    connect \A $or$ls180.v:3434$1081_Y
     connect \B \libresocsim_interface6_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1114_Y
+    connect \Y $or$ls180.v:3434$1082_Y
   end
-  attribute \src "ls180.v:3449.46-3449.375"
-  cell $or $or$ls180.v:3449$1115
+  attribute \src "ls180.v:3434.46-3434.375"
+  cell $or $or$ls180.v:3434$1083
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A $or$ls180.v:3449$1114_Y
+    connect \A $or$ls180.v:3434$1082_Y
     connect \B \libresocsim_interface7_bank_bus_dat_r
-    connect \Y $or$ls180.v:3449$1115_Y
+    connect \Y $or$ls180.v:3434$1083_Y
   end
-  attribute \src "ls180.v:3776.72-3776.166"
-  cell $or $or$ls180.v:3776$1140
+  attribute \src "ls180.v:3761.72-3761.166"
+  cell $or $or$ls180.v:3761$1108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked0
-    connect \B $and$ls180.v:3776$1139_Y
-    connect \Y $or$ls180.v:3776$1140_Y
+    connect \B $and$ls180.v:3761$1107_Y
+    connect \Y $or$ls180.v:3761$1108_Y
   end
-  attribute \src "ls180.v:3776.71-3776.241"
-  cell $or $or$ls180.v:3776$1143
+  attribute \src "ls180.v:3761.71-3761.241"
+  cell $or $or$ls180.v:3761$1111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3776$1140_Y
-    connect \B $and$ls180.v:3776$1142_Y
-    connect \Y $or$ls180.v:3776$1143_Y
+    connect \A $or$ls180.v:3761$1108_Y
+    connect \B $and$ls180.v:3761$1110_Y
+    connect \Y $or$ls180.v:3761$1111_Y
   end
-  attribute \src "ls180.v:3776.70-3776.316"
-  cell $or $or$ls180.v:3776$1146
+  attribute \src "ls180.v:3761.70-3761.316"
+  cell $or $or$ls180.v:3761$1114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3776$1143_Y
-    connect \B $and$ls180.v:3776$1145_Y
-    connect \Y $or$ls180.v:3776$1146_Y
+    connect \A $or$ls180.v:3761$1111_Y
+    connect \B $and$ls180.v:3761$1113_Y
+    connect \Y $or$ls180.v:3761$1114_Y
   end
-  attribute \src "ls180.v:3800.72-3800.166"
-  cell $or $or$ls180.v:3800$1156
+  attribute \src "ls180.v:3785.72-3785.166"
+  cell $or $or$ls180.v:3785$1124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked1
-    connect \B $and$ls180.v:3800$1155_Y
-    connect \Y $or$ls180.v:3800$1156_Y
+    connect \B $and$ls180.v:3785$1123_Y
+    connect \Y $or$ls180.v:3785$1124_Y
   end
-  attribute \src "ls180.v:3800.71-3800.241"
-  cell $or $or$ls180.v:3800$1159
+  attribute \src "ls180.v:3785.71-3785.241"
+  cell $or $or$ls180.v:3785$1127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3800$1156_Y
-    connect \B $and$ls180.v:3800$1158_Y
-    connect \Y $or$ls180.v:3800$1159_Y
+    connect \A $or$ls180.v:3785$1124_Y
+    connect \B $and$ls180.v:3785$1126_Y
+    connect \Y $or$ls180.v:3785$1127_Y
   end
-  attribute \src "ls180.v:3800.70-3800.316"
-  cell $or $or$ls180.v:3800$1162
+  attribute \src "ls180.v:3785.70-3785.316"
+  cell $or $or$ls180.v:3785$1130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3800$1159_Y
-    connect \B $and$ls180.v:3800$1161_Y
-    connect \Y $or$ls180.v:3800$1162_Y
+    connect \A $or$ls180.v:3785$1127_Y
+    connect \B $and$ls180.v:3785$1129_Y
+    connect \Y $or$ls180.v:3785$1130_Y
   end
-  attribute \src "ls180.v:3824.72-3824.166"
-  cell $or $or$ls180.v:3824$1172
+  attribute \src "ls180.v:3809.72-3809.166"
+  cell $or $or$ls180.v:3809$1140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked2
-    connect \B $and$ls180.v:3824$1171_Y
-    connect \Y $or$ls180.v:3824$1172_Y
+    connect \B $and$ls180.v:3809$1139_Y
+    connect \Y $or$ls180.v:3809$1140_Y
   end
-  attribute \src "ls180.v:3824.71-3824.241"
-  cell $or $or$ls180.v:3824$1175
+  attribute \src "ls180.v:3809.71-3809.241"
+  cell $or $or$ls180.v:3809$1143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3824$1172_Y
-    connect \B $and$ls180.v:3824$1174_Y
-    connect \Y $or$ls180.v:3824$1175_Y
+    connect \A $or$ls180.v:3809$1140_Y
+    connect \B $and$ls180.v:3809$1142_Y
+    connect \Y $or$ls180.v:3809$1143_Y
   end
-  attribute \src "ls180.v:3824.70-3824.316"
-  cell $or $or$ls180.v:3824$1178
+  attribute \src "ls180.v:3809.70-3809.316"
+  cell $or $or$ls180.v:3809$1146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3824$1175_Y
-    connect \B $and$ls180.v:3824$1177_Y
-    connect \Y $or$ls180.v:3824$1178_Y
+    connect \A $or$ls180.v:3809$1143_Y
+    connect \B $and$ls180.v:3809$1145_Y
+    connect \Y $or$ls180.v:3809$1146_Y
   end
-  attribute \src "ls180.v:3848.72-3848.166"
-  cell $or $or$ls180.v:3848$1188
+  attribute \src "ls180.v:3833.72-3833.166"
+  cell $or $or$ls180.v:3833$1156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \subfragments_locked3
-    connect \B $and$ls180.v:3848$1187_Y
-    connect \Y $or$ls180.v:3848$1188_Y
+    connect \B $and$ls180.v:3833$1155_Y
+    connect \Y $or$ls180.v:3833$1156_Y
   end
-  attribute \src "ls180.v:3848.71-3848.241"
-  cell $or $or$ls180.v:3848$1191
+  attribute \src "ls180.v:3833.71-3833.241"
+  cell $or $or$ls180.v:3833$1159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3848$1188_Y
-    connect \B $and$ls180.v:3848$1190_Y
-    connect \Y $or$ls180.v:3848$1191_Y
+    connect \A $or$ls180.v:3833$1156_Y
+    connect \B $and$ls180.v:3833$1158_Y
+    connect \Y $or$ls180.v:3833$1159_Y
   end
-  attribute \src "ls180.v:3848.70-3848.316"
-  cell $or $or$ls180.v:3848$1194
+  attribute \src "ls180.v:3833.70-3833.316"
+  cell $or $or$ls180.v:3833$1162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:3848$1191_Y
-    connect \B $and$ls180.v:3848$1193_Y
-    connect \Y $or$ls180.v:3848$1194_Y
+    connect \A $or$ls180.v:3833$1159_Y
+    connect \B $and$ls180.v:3833$1161_Y
+    connect \Y $or$ls180.v:3833$1162_Y
   end
-  attribute \src "ls180.v:4301.15-4301.58"
-  cell $or $or$ls180.v:4301$1248
+  attribute \src "ls180.v:4286.15-4286.58"
+  cell $or $or$ls180.v:4286$1216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260173,10 +259689,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [0]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4301$1248_Y
+    connect \Y $or$ls180.v:4286$1216_Y
   end
-  attribute \src "ls180.v:4302.15-4302.58"
-  cell $or $or$ls180.v:4302$1249
+  attribute \src "ls180.v:4287.15-4287.58"
+  cell $or $or$ls180.v:4287$1217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260184,10 +259700,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [1]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4302$1249_Y
+    connect \Y $or$ls180.v:4287$1217_Y
   end
-  attribute \src "ls180.v:4303.15-4303.58"
-  cell $or $or$ls180.v:4303$1250
+  attribute \src "ls180.v:4288.15-4288.58"
+  cell $or $or$ls180.v:4288$1218
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260195,10 +259711,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [2]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4303$1250_Y
+    connect \Y $or$ls180.v:4288$1218_Y
   end
-  attribute \src "ls180.v:4304.15-4304.58"
-  cell $or $or$ls180.v:4304$1251
+  attribute \src "ls180.v:4289.15-4289.58"
+  cell $or $or$ls180.v:4289$1219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260206,10 +259722,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [3]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4304$1251_Y
+    connect \Y $or$ls180.v:4289$1219_Y
   end
-  attribute \src "ls180.v:4305.15-4305.58"
-  cell $or $or$ls180.v:4305$1252
+  attribute \src "ls180.v:4290.15-4290.58"
+  cell $or $or$ls180.v:4290$1220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260217,10 +259733,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [4]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4305$1252_Y
+    connect \Y $or$ls180.v:4290$1220_Y
   end
-  attribute \src "ls180.v:4306.15-4306.58"
-  cell $or $or$ls180.v:4306$1253
+  attribute \src "ls180.v:4291.15-4291.58"
+  cell $or $or$ls180.v:4291$1221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260228,10 +259744,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [5]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4306$1253_Y
+    connect \Y $or$ls180.v:4291$1221_Y
   end
-  attribute \src "ls180.v:4307.15-4307.58"
-  cell $or $or$ls180.v:4307$1254
+  attribute \src "ls180.v:4292.15-4292.58"
+  cell $or $or$ls180.v:4292$1222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260239,10 +259755,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [6]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4307$1254_Y
+    connect \Y $or$ls180.v:4292$1222_Y
   end
-  attribute \src "ls180.v:4308.15-4308.58"
-  cell $or $or$ls180.v:4308$1255
+  attribute \src "ls180.v:4293.15-4293.58"
+  cell $or $or$ls180.v:4293$1223
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260250,10 +259766,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [7]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4308$1255_Y
+    connect \Y $or$ls180.v:4293$1223_Y
   end
-  attribute \src "ls180.v:4309.15-4309.58"
-  cell $or $or$ls180.v:4309$1256
+  attribute \src "ls180.v:4294.15-4294.58"
+  cell $or $or$ls180.v:4294$1224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260261,10 +259777,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [8]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4309$1256_Y
+    connect \Y $or$ls180.v:4294$1224_Y
   end
-  attribute \src "ls180.v:4310.15-4310.58"
-  cell $or $or$ls180.v:4310$1257
+  attribute \src "ls180.v:4295.15-4295.58"
+  cell $or $or$ls180.v:4295$1225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260272,10 +259788,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [9]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4310$1257_Y
+    connect \Y $or$ls180.v:4295$1225_Y
   end
-  attribute \src "ls180.v:4311.16-4311.60"
-  cell $or $or$ls180.v:4311$1258
+  attribute \src "ls180.v:4296.16-4296.60"
+  cell $or $or$ls180.v:4296$1226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260283,10 +259799,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [10]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4311$1258_Y
+    connect \Y $or$ls180.v:4296$1226_Y
   end
-  attribute \src "ls180.v:4312.16-4312.60"
-  cell $or $or$ls180.v:4312$1259
+  attribute \src "ls180.v:4297.16-4297.60"
+  cell $or $or$ls180.v:4297$1227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260294,10 +259810,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [11]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4312$1259_Y
+    connect \Y $or$ls180.v:4297$1227_Y
   end
-  attribute \src "ls180.v:4313.16-4313.60"
-  cell $or $or$ls180.v:4313$1260
+  attribute \src "ls180.v:4298.16-4298.60"
+  cell $or $or$ls180.v:4298$1228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260305,10 +259821,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [12]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4313$1260_Y
+    connect \Y $or$ls180.v:4298$1228_Y
   end
-  attribute \src "ls180.v:4314.16-4314.60"
-  cell $or $or$ls180.v:4314$1261
+  attribute \src "ls180.v:4299.16-4299.60"
+  cell $or $or$ls180.v:4299$1229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260316,10 +259832,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [13]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4314$1261_Y
+    connect \Y $or$ls180.v:4299$1229_Y
   end
-  attribute \src "ls180.v:4315.16-4315.60"
-  cell $or $or$ls180.v:4315$1262
+  attribute \src "ls180.v:4300.16-4300.60"
+  cell $or $or$ls180.v:4300$1230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260327,10 +259843,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [14]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4315$1262_Y
+    connect \Y $or$ls180.v:4300$1230_Y
   end
-  attribute \src "ls180.v:4316.16-4316.60"
-  cell $or $or$ls180.v:4316$1263
+  attribute \src "ls180.v:4301.16-4301.60"
+  cell $or $or$ls180.v:4301$1231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260338,10 +259854,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [15]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4316$1263_Y
+    connect \Y $or$ls180.v:4301$1231_Y
   end
-  attribute \src "ls180.v:4317.16-4317.60"
-  cell $or $or$ls180.v:4317$1264
+  attribute \src "ls180.v:4302.16-4302.60"
+  cell $or $or$ls180.v:4302$1232
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260349,10 +259865,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [16]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4317$1264_Y
+    connect \Y $or$ls180.v:4302$1232_Y
   end
-  attribute \src "ls180.v:4318.16-4318.60"
-  cell $or $or$ls180.v:4318$1265
+  attribute \src "ls180.v:4303.16-4303.60"
+  cell $or $or$ls180.v:4303$1233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260360,10 +259876,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [17]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4318$1265_Y
+    connect \Y $or$ls180.v:4303$1233_Y
   end
-  attribute \src "ls180.v:4319.16-4319.60"
-  cell $or $or$ls180.v:4319$1266
+  attribute \src "ls180.v:4304.16-4304.60"
+  cell $or $or$ls180.v:4304$1234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260371,10 +259887,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [18]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4319$1266_Y
+    connect \Y $or$ls180.v:4304$1234_Y
   end
-  attribute \src "ls180.v:4320.16-4320.60"
-  cell $or $or$ls180.v:4320$1267
+  attribute \src "ls180.v:4305.16-4305.60"
+  cell $or $or$ls180.v:4305$1235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260382,10 +259898,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [19]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4320$1267_Y
+    connect \Y $or$ls180.v:4305$1235_Y
   end
-  attribute \src "ls180.v:4321.16-4321.60"
-  cell $or $or$ls180.v:4321$1268
+  attribute \src "ls180.v:4306.16-4306.60"
+  cell $or $or$ls180.v:4306$1236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260393,10 +259909,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [20]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4321$1268_Y
+    connect \Y $or$ls180.v:4306$1236_Y
   end
-  attribute \src "ls180.v:4322.16-4322.60"
-  cell $or $or$ls180.v:4322$1269
+  attribute \src "ls180.v:4307.16-4307.60"
+  cell $or $or$ls180.v:4307$1237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260404,10 +259920,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [21]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4322$1269_Y
+    connect \Y $or$ls180.v:4307$1237_Y
   end
-  attribute \src "ls180.v:4323.16-4323.60"
-  cell $or $or$ls180.v:4323$1270
+  attribute \src "ls180.v:4308.16-4308.60"
+  cell $or $or$ls180.v:4308$1238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260415,10 +259931,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [22]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4323$1270_Y
+    connect \Y $or$ls180.v:4308$1238_Y
   end
-  attribute \src "ls180.v:4324.16-4324.60"
-  cell $or $or$ls180.v:4324$1271
+  attribute \src "ls180.v:4309.16-4309.60"
+  cell $or $or$ls180.v:4309$1239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260426,10 +259942,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [23]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4324$1271_Y
+    connect \Y $or$ls180.v:4309$1239_Y
   end
-  attribute \src "ls180.v:4325.16-4325.60"
-  cell $or $or$ls180.v:4325$1272
+  attribute \src "ls180.v:4310.16-4310.60"
+  cell $or $or$ls180.v:4310$1240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260437,10 +259953,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [24]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4325$1272_Y
+    connect \Y $or$ls180.v:4310$1240_Y
   end
-  attribute \src "ls180.v:4326.16-4326.60"
-  cell $or $or$ls180.v:4326$1273
+  attribute \src "ls180.v:4311.16-4311.60"
+  cell $or $or$ls180.v:4311$1241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260448,10 +259964,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [25]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4326$1273_Y
+    connect \Y $or$ls180.v:4311$1241_Y
   end
-  attribute \src "ls180.v:4327.16-4327.60"
-  cell $or $or$ls180.v:4327$1274
+  attribute \src "ls180.v:4312.16-4312.60"
+  cell $or $or$ls180.v:4312$1242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260459,10 +259975,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [26]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4327$1274_Y
+    connect \Y $or$ls180.v:4312$1242_Y
   end
-  attribute \src "ls180.v:4328.16-4328.60"
-  cell $or $or$ls180.v:4328$1275
+  attribute \src "ls180.v:4313.16-4313.60"
+  cell $or $or$ls180.v:4313$1243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260470,10 +259986,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [27]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4328$1275_Y
+    connect \Y $or$ls180.v:4313$1243_Y
   end
-  attribute \src "ls180.v:4329.16-4329.60"
-  cell $or $or$ls180.v:4329$1276
+  attribute \src "ls180.v:4314.16-4314.60"
+  cell $or $or$ls180.v:4314$1244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260481,10 +259997,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [28]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4329$1276_Y
+    connect \Y $or$ls180.v:4314$1244_Y
   end
-  attribute \src "ls180.v:4330.16-4330.60"
-  cell $or $or$ls180.v:4330$1277
+  attribute \src "ls180.v:4315.16-4315.60"
+  cell $or $or$ls180.v:4315$1245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260492,10 +260008,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [29]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4330$1277_Y
+    connect \Y $or$ls180.v:4315$1245_Y
   end
-  attribute \src "ls180.v:4331.16-4331.60"
-  cell $or $or$ls180.v:4331$1278
+  attribute \src "ls180.v:4316.16-4316.60"
+  cell $or $or$ls180.v:4316$1246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260503,10 +260019,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [30]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4331$1278_Y
+    connect \Y $or$ls180.v:4316$1246_Y
   end
-  attribute \src "ls180.v:4332.16-4332.60"
-  cell $or $or$ls180.v:4332$1279
+  attribute \src "ls180.v:4317.16-4317.60"
+  cell $or $or$ls180.v:4317$1247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260514,10 +260030,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [31]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4332$1279_Y
+    connect \Y $or$ls180.v:4317$1247_Y
   end
-  attribute \src "ls180.v:4333.16-4333.60"
-  cell $or $or$ls180.v:4333$1280
+  attribute \src "ls180.v:4318.16-4318.60"
+  cell $or $or$ls180.v:4318$1248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260525,10 +260041,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [32]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4333$1280_Y
+    connect \Y $or$ls180.v:4318$1248_Y
   end
-  attribute \src "ls180.v:4334.16-4334.60"
-  cell $or $or$ls180.v:4334$1281
+  attribute \src "ls180.v:4319.16-4319.60"
+  cell $or $or$ls180.v:4319$1249
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260536,10 +260052,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [33]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4334$1281_Y
+    connect \Y $or$ls180.v:4319$1249_Y
   end
-  attribute \src "ls180.v:4335.16-4335.60"
-  cell $or $or$ls180.v:4335$1282
+  attribute \src "ls180.v:4320.16-4320.60"
+  cell $or $or$ls180.v:4320$1250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260547,10 +260063,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [34]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4335$1282_Y
+    connect \Y $or$ls180.v:4320$1250_Y
   end
-  attribute \src "ls180.v:4336.16-4336.60"
-  cell $or $or$ls180.v:4336$1283
+  attribute \src "ls180.v:4321.16-4321.60"
+  cell $or $or$ls180.v:4321$1251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260558,175 +260074,175 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \nc_1 [35]
     connect \B \libresocsim_libresoc_interrupt [0]
-    connect \Y $or$ls180.v:4336$1283_Y
+    connect \Y $or$ls180.v:4321$1251_Y
   end
-  attribute \src "ls180.v:4337.7-4337.58"
-  cell $or $or$ls180.v:4337$1284
+  attribute \src "ls180.v:4322.7-4322.83"
+  cell $or $or$ls180.v:4322$1252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_icp_ack
-    connect \B \converter0_skip
-    connect \Y $or$ls180.v:4337$1284_Y
+    connect \A \libresocsim_interface0_converted_interface_ack
+    connect \B \libresocsim_converter0_skip
+    connect \Y $or$ls180.v:4322$1252_Y
   end
-  attribute \src "ls180.v:4348.7-4348.58"
-  cell $or $or$ls180.v:4348$1285
+  attribute \src "ls180.v:4333.7-4333.83"
+  cell $or $or$ls180.v:4333$1253
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \libresocsim_libresoc_xics_ics_ack
-    connect \B \converter1_skip
-    connect \Y $or$ls180.v:4348$1285_Y
+    connect \A \libresocsim_interface1_converted_interface_ack
+    connect \B \libresocsim_converter1_skip
+    connect \Y $or$ls180.v:4333$1253_Y
   end
-  attribute \src "ls180.v:4359.7-4359.40"
-  cell $or $or$ls180.v:4359$1286
+  attribute \src "ls180.v:4344.7-4344.83"
+  cell $or $or$ls180.v:4344$1254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wb_sdram_ack
-    connect \B \socbushandler_skip
-    connect \Y $or$ls180.v:4359$1286_Y
+    connect \A \libresocsim_interface2_converted_interface_ack
+    connect \B \libresocsim_converter2_skip
+    connect \Y $or$ls180.v:4344$1254_Y
   end
-  attribute \src "ls180.v:4492.7-4492.97"
-  cell $or $or$ls180.v:4492$1325
+  attribute \src "ls180.v:4477.7-4477.97"
+  cell $or $or$ls180.v:4477$1293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4492$1324_Y
+    connect \A $not$ls180.v:4477$1292_Y
     connect \B \sdram_bankmachine0_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:4492$1325_Y
+    connect \Y $or$ls180.v:4477$1293_Y
   end
-  attribute \src "ls180.v:4538.7-4538.97"
-  cell $or $or$ls180.v:4538$1341
+  attribute \src "ls180.v:4523.7-4523.97"
+  cell $or $or$ls180.v:4523$1309
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4538$1340_Y
+    connect \A $not$ls180.v:4523$1308_Y
     connect \B \sdram_bankmachine1_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:4538$1341_Y
+    connect \Y $or$ls180.v:4523$1309_Y
   end
-  attribute \src "ls180.v:4584.7-4584.97"
-  cell $or $or$ls180.v:4584$1357
+  attribute \src "ls180.v:4569.7-4569.97"
+  cell $or $or$ls180.v:4569$1325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4584$1356_Y
+    connect \A $not$ls180.v:4569$1324_Y
     connect \B \sdram_bankmachine2_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:4584$1357_Y
+    connect \Y $or$ls180.v:4569$1325_Y
   end
-  attribute \src "ls180.v:4630.7-4630.97"
-  cell $or $or$ls180.v:4630$1373
+  attribute \src "ls180.v:4615.7-4615.97"
+  cell $or $or$ls180.v:4615$1341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $not$ls180.v:4630$1372_Y
+    connect \A $not$ls180.v:4615$1340_Y
     connect \B \sdram_bankmachine3_cmd_buffer_source_ready
-    connect \Y $or$ls180.v:4630$1373_Y
+    connect \Y $or$ls180.v:4615$1341_Y
   end
-  attribute \src "ls180.v:4818.45-4818.130"
-  cell $or $or$ls180.v:4818$1394
+  attribute \src "ls180.v:4803.45-4803.130"
+  cell $or $or$ls180.v:4803$1362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:4818$1393_Y
-    connect \Y $or$ls180.v:4818$1394_Y
+    connect \B $and$ls180.v:4803$1361_Y
+    connect \Y $or$ls180.v:4803$1362_Y
   end
-  attribute \src "ls180.v:4818.44-4818.212"
-  cell $or $or$ls180.v:4818$1397
+  attribute \src "ls180.v:4803.44-4803.212"
+  cell $or $or$ls180.v:4803$1365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4818$1394_Y
-    connect \B $and$ls180.v:4818$1396_Y
-    connect \Y $or$ls180.v:4818$1397_Y
+    connect \A $or$ls180.v:4803$1362_Y
+    connect \B $and$ls180.v:4803$1364_Y
+    connect \Y $or$ls180.v:4803$1365_Y
   end
-  attribute \src "ls180.v:4818.43-4818.294"
-  cell $or $or$ls180.v:4818$1400
+  attribute \src "ls180.v:4803.43-4803.294"
+  cell $or $or$ls180.v:4803$1368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4818$1397_Y
-    connect \B $and$ls180.v:4818$1399_Y
-    connect \Y $or$ls180.v:4818$1400_Y
+    connect \A $or$ls180.v:4803$1365_Y
+    connect \B $and$ls180.v:4803$1367_Y
+    connect \Y $or$ls180.v:4803$1368_Y
   end
-  attribute \src "ls180.v:4818.42-4818.376"
-  cell $or $or$ls180.v:4818$1403
+  attribute \src "ls180.v:4803.42-4803.376"
+  cell $or $or$ls180.v:4803$1371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4818$1400_Y
-    connect \B $and$ls180.v:4818$1402_Y
-    connect \Y $or$ls180.v:4818$1403_Y
+    connect \A $or$ls180.v:4803$1368_Y
+    connect \B $and$ls180.v:4803$1370_Y
+    connect \Y $or$ls180.v:4803$1371_Y
   end
-  attribute \src "ls180.v:4819.46-4819.131"
-  cell $or $or$ls180.v:4819$1406
+  attribute \src "ls180.v:4804.46-4804.131"
+  cell $or $or$ls180.v:4804$1374
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A 1'0
-    connect \B $and$ls180.v:4819$1405_Y
-    connect \Y $or$ls180.v:4819$1406_Y
+    connect \B $and$ls180.v:4804$1373_Y
+    connect \Y $or$ls180.v:4804$1374_Y
   end
-  attribute \src "ls180.v:4819.45-4819.213"
-  cell $or $or$ls180.v:4819$1409
+  attribute \src "ls180.v:4804.45-4804.213"
+  cell $or $or$ls180.v:4804$1377
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4819$1406_Y
-    connect \B $and$ls180.v:4819$1408_Y
-    connect \Y $or$ls180.v:4819$1409_Y
+    connect \A $or$ls180.v:4804$1374_Y
+    connect \B $and$ls180.v:4804$1376_Y
+    connect \Y $or$ls180.v:4804$1377_Y
   end
-  attribute \src "ls180.v:4819.44-4819.295"
-  cell $or $or$ls180.v:4819$1412
+  attribute \src "ls180.v:4804.44-4804.295"
+  cell $or $or$ls180.v:4804$1380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4819$1409_Y
-    connect \B $and$ls180.v:4819$1411_Y
-    connect \Y $or$ls180.v:4819$1412_Y
+    connect \A $or$ls180.v:4804$1377_Y
+    connect \B $and$ls180.v:4804$1379_Y
+    connect \Y $or$ls180.v:4804$1380_Y
   end
-  attribute \src "ls180.v:4819.43-4819.377"
-  cell $or $or$ls180.v:4819$1415
+  attribute \src "ls180.v:4804.43-4804.377"
+  cell $or $or$ls180.v:4804$1383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $or$ls180.v:4819$1412_Y
-    connect \B $and$ls180.v:4819$1414_Y
-    connect \Y $or$ls180.v:4819$1415_Y
+    connect \A $or$ls180.v:4804$1380_Y
+    connect \B $and$ls180.v:4804$1382_Y
+    connect \Y $or$ls180.v:4804$1383_Y
   end
-  attribute \src "ls180.v:4823.7-4823.39"
-  cell $or $or$ls180.v:4823$1416
+  attribute \src "ls180.v:4808.7-4808.39"
+  cell $or $or$ls180.v:4808$1384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260734,10 +260250,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \litedram_wb_ack
     connect \B \converter_skip
-    connect \Y $or$ls180.v:4823$1416_Y
+    connect \Y $or$ls180.v:4808$1384_Y
   end
-  attribute \src "ls180.v:5748.8-5748.46"
-  cell $or $or$ls180.v:5748$1626
+  attribute \src "ls180.v:5717.8-5717.46"
+  cell $or $or$ls180.v:5717$1546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260745,10 +260261,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sys_rst_1
     connect \B \libresocsim_libresoc_reset
-    connect \Y $or$ls180.v:5748$1626_Y
+    connect \Y $or$ls180.v:5717$1546_Y
   end
-  attribute \src "ls180.v:1949.41-1949.84"
-  cell $sshl $sshl$ls180.v:1949$131
+  attribute \src "ls180.v:1934.41-1934.84"
+  cell $sshl $sshl$ls180.v:1934$99
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260756,10 +260272,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \sdram_bankmachine0_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:1949$131_Y
+    connect \Y $sshl$ls180.v:1934$99_Y
   end
-  attribute \src "ls180.v:2106.41-2106.84"
-  cell $sshl $sshl$ls180.v:2106$161
+  attribute \src "ls180.v:2091.41-2091.84"
+  cell $sshl $sshl$ls180.v:2091$129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260767,10 +260283,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \sdram_bankmachine1_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:2106$161_Y
+    connect \Y $sshl$ls180.v:2091$129_Y
   end
-  attribute \src "ls180.v:2263.41-2263.84"
-  cell $sshl $sshl$ls180.v:2263$191
+  attribute \src "ls180.v:2248.41-2248.84"
+  cell $sshl $sshl$ls180.v:2248$159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260778,10 +260294,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \sdram_bankmachine2_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:2263$191_Y
+    connect \Y $sshl$ls180.v:2248$159_Y
   end
-  attribute \src "ls180.v:2420.41-2420.84"
-  cell $sshl $sshl$ls180.v:2420$221
+  attribute \src "ls180.v:2405.41-2405.84"
+  cell $sshl $sshl$ls180.v:2405$189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260789,10 +260305,10 @@ module \ls180
     parameter \Y_WIDTH 13
     connect \A \sdram_bankmachine3_auto_precharge
     connect \B 4'1010
-    connect \Y $sshl$ls180.v:2420$221_Y
+    connect \Y $sshl$ls180.v:2405$189_Y
   end
-  attribute \src "ls180.v:1980.58-1980.112"
-  cell $sub $sub$ls180.v:1980$144
+  attribute \src "ls180.v:1965.58-1965.112"
+  cell $sub $sub$ls180.v:1965$112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260800,10 +260316,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:1980$144_Y
+    connect \Y $sub$ls180.v:1965$112_Y
   end
-  attribute \src "ls180.v:2137.58-2137.112"
-  cell $sub $sub$ls180.v:2137$174
+  attribute \src "ls180.v:2122.58-2122.112"
+  cell $sub $sub$ls180.v:2122$142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260811,10 +260327,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:2137$174_Y
+    connect \Y $sub$ls180.v:2122$142_Y
   end
-  attribute \src "ls180.v:2294.58-2294.112"
-  cell $sub $sub$ls180.v:2294$204
+  attribute \src "ls180.v:2279.58-2279.112"
+  cell $sub $sub$ls180.v:2279$172
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260822,10 +260338,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:2294$204_Y
+    connect \Y $sub$ls180.v:2279$172_Y
   end
-  attribute \src "ls180.v:2451.58-2451.112"
-  cell $sub $sub$ls180.v:2451$234
+  attribute \src "ls180.v:2436.58-2436.112"
+  cell $sub $sub$ls180.v:2436$202
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260833,10 +260349,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:2451$234_Y
+    connect \Y $sub$ls180.v:2436$202_Y
   end
-  attribute \src "ls180.v:2857.33-2857.65"
-  cell $sub $sub$ls180.v:2857$588
+  attribute \src "ls180.v:2842.33-2842.65"
+  cell $sub $sub$ls180.v:2842$556
     parameter \A_SIGNED 0
     parameter \A_WIDTH 30
     parameter \B_SIGNED 0
@@ -260844,10 +260360,10 @@ module \ls180
     parameter \Y_WIDTH 31
     connect \A \litedram_wb_adr
     connect \B 31'1001000000000000000000000000000
-    connect \Y $sub$ls180.v:2857$588_Y
+    connect \Y $sub$ls180.v:2842$556_Y
   end
-  attribute \src "ls180.v:2943.26-2943.48"
-  cell $sub $sub$ls180.v:2943$633
+  attribute \src "ls180.v:2928.26-2928.48"
+  cell $sub $sub$ls180.v:2928$601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260855,10 +260371,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \tx_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:2943$633_Y
+    connect \Y $sub$ls180.v:2928$601_Y
   end
-  attribute \src "ls180.v:2973.26-2973.48"
-  cell $sub $sub$ls180.v:2973$644
+  attribute \src "ls180.v:2958.26-2958.48"
+  cell $sub $sub$ls180.v:2958$612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260866,10 +260382,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \rx_fifo_produce
     connect \B 1'1
-    connect \Y $sub$ls180.v:2973$644_Y
+    connect \Y $sub$ls180.v:2958$612_Y
   end
-  attribute \src "ls180.v:4383.26-4383.50"
-  cell $sub $sub$ls180.v:4383$1293
+  attribute \src "ls180.v:4368.26-4368.50"
+  cell $sub $sub$ls180.v:4368$1261
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \B_SIGNED 0
@@ -260877,10 +260393,10 @@ module \ls180
     parameter \Y_WIDTH 32
     connect \A \libresocsim_value
     connect \B 1'1
-    connect \Y $sub$ls180.v:4383$1293_Y
+    connect \Y $sub$ls180.v:4368$1261_Y
   end
-  attribute \src "ls180.v:4408.26-4408.51"
-  cell $sub $sub$ls180.v:4408$1301
+  attribute \src "ls180.v:4393.26-4393.51"
+  cell $sub $sub$ls180.v:4393$1269
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -260888,10 +260404,10 @@ module \ls180
     parameter \Y_WIDTH 10
     connect \A \sdram_timer_count1
     connect \B 1'1
-    connect \Y $sub$ls180.v:4408$1301_Y
+    connect \Y $sub$ls180.v:4393$1269_Y
   end
-  attribute \src "ls180.v:4414.29-4414.57"
-  cell $sub $sub$ls180.v:4414$1302
+  attribute \src "ls180.v:4399.29-4399.57"
+  cell $sub $sub$ls180.v:4399$1270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260899,10 +260415,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_postponer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4414$1302_Y
+    connect \Y $sub$ls180.v:4399$1270_Y
   end
-  attribute \src "ls180.v:4425.31-4425.59"
-  cell $sub $sub$ls180.v:4425$1305
+  attribute \src "ls180.v:4410.31-4410.59"
+  cell $sub $sub$ls180.v:4410$1273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -260910,10 +260426,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_sequencer_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4425$1305_Y
+    connect \Y $sub$ls180.v:4410$1273_Y
   end
-  attribute \src "ls180.v:4489.54-4489.106"
-  cell $sub $sub$ls180.v:4489$1323
+  attribute \src "ls180.v:4474.54-4474.106"
+  cell $sub $sub$ls180.v:4474$1291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260921,10 +260437,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:4489$1323_Y
+    connect \Y $sub$ls180.v:4474$1291_Y
   end
-  attribute \src "ls180.v:4508.41-4508.80"
-  cell $sub $sub$ls180.v:4508$1327
+  attribute \src "ls180.v:4493.41-4493.80"
+  cell $sub $sub$ls180.v:4493$1295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260932,10 +260448,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine0_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4508$1327_Y
+    connect \Y $sub$ls180.v:4493$1295_Y
   end
-  attribute \src "ls180.v:4535.54-4535.106"
-  cell $sub $sub$ls180.v:4535$1339
+  attribute \src "ls180.v:4520.54-4520.106"
+  cell $sub $sub$ls180.v:4520$1307
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260943,10 +260459,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:4535$1339_Y
+    connect \Y $sub$ls180.v:4520$1307_Y
   end
-  attribute \src "ls180.v:4554.41-4554.80"
-  cell $sub $sub$ls180.v:4554$1343
+  attribute \src "ls180.v:4539.41-4539.80"
+  cell $sub $sub$ls180.v:4539$1311
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260954,10 +260470,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine1_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4554$1343_Y
+    connect \Y $sub$ls180.v:4539$1311_Y
   end
-  attribute \src "ls180.v:4581.54-4581.106"
-  cell $sub $sub$ls180.v:4581$1355
+  attribute \src "ls180.v:4566.54-4566.106"
+  cell $sub $sub$ls180.v:4566$1323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260965,10 +260481,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:4581$1355_Y
+    connect \Y $sub$ls180.v:4566$1323_Y
   end
-  attribute \src "ls180.v:4600.41-4600.80"
-  cell $sub $sub$ls180.v:4600$1359
+  attribute \src "ls180.v:4585.41-4585.80"
+  cell $sub $sub$ls180.v:4585$1327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260976,10 +260492,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine2_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4600$1359_Y
+    connect \Y $sub$ls180.v:4585$1327_Y
   end
-  attribute \src "ls180.v:4627.54-4627.106"
-  cell $sub $sub$ls180.v:4627$1371
+  attribute \src "ls180.v:4612.54-4612.106"
+  cell $sub $sub$ls180.v:4612$1339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -260987,10 +260503,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
     connect \B 1'1
-    connect \Y $sub$ls180.v:4627$1371_Y
+    connect \Y $sub$ls180.v:4612$1339_Y
   end
-  attribute \src "ls180.v:4646.41-4646.80"
-  cell $sub $sub$ls180.v:4646$1375
+  attribute \src "ls180.v:4631.41-4631.80"
+  cell $sub $sub$ls180.v:4631$1343
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -260998,10 +260514,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_bankmachine3_twtpcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4646$1375_Y
+    connect \Y $sub$ls180.v:4631$1343_Y
   end
-  attribute \src "ls180.v:4657.20-4657.38"
-  cell $sub $sub$ls180.v:4657$1379
+  attribute \src "ls180.v:4642.20-4642.38"
+  cell $sub $sub$ls180.v:4642$1347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -261009,10 +260525,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \sdram_time0
     connect \B 1'1
-    connect \Y $sub$ls180.v:4657$1379_Y
+    connect \Y $sub$ls180.v:4642$1347_Y
   end
-  attribute \src "ls180.v:4664.20-4664.38"
-  cell $sub $sub$ls180.v:4664$1382
+  attribute \src "ls180.v:4649.20-4649.38"
+  cell $sub $sub$ls180.v:4649$1350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -261020,10 +260536,10 @@ module \ls180
     parameter \Y_WIDTH 4
     connect \A \sdram_time1
     connect \B 1'1
-    connect \Y $sub$ls180.v:4664$1382_Y
+    connect \Y $sub$ls180.v:4649$1350_Y
   end
-  attribute \src "ls180.v:4796.28-4796.54"
-  cell $sub $sub$ls180.v:4796$1387
+  attribute \src "ls180.v:4781.28-4781.54"
+  cell $sub $sub$ls180.v:4781$1355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -261031,10 +260547,10 @@ module \ls180
     parameter \Y_WIDTH 1
     connect \A \sdram_tccdcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4796$1387_Y
+    connect \Y $sub$ls180.v:4781$1355_Y
   end
-  attribute \src "ls180.v:4811.28-4811.54"
-  cell $sub $sub$ls180.v:4811$1390
+  attribute \src "ls180.v:4796.28-4796.54"
+  cell $sub $sub$ls180.v:4796$1358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -261042,10 +260558,10 @@ module \ls180
     parameter \Y_WIDTH 3
     connect \A \sdram_twtrcon_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:4811$1390_Y
+    connect \Y $sub$ls180.v:4796$1358_Y
   end
-  attribute \src "ls180.v:4938.23-4938.44"
-  cell $sub $sub$ls180.v:4938$1449
+  attribute \src "ls180.v:4923.23-4923.44"
+  cell $sub $sub$ls180.v:4923$1417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -261053,10 +260569,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \tx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:4938$1449_Y
+    connect \Y $sub$ls180.v:4923$1417_Y
   end
-  attribute \src "ls180.v:4960.23-4960.44"
-  cell $sub $sub$ls180.v:4960$1460
+  attribute \src "ls180.v:4945.23-4945.44"
+  cell $sub $sub$ls180.v:4945$1428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -261064,10 +260580,10 @@ module \ls180
     parameter \Y_WIDTH 5
     connect \A \rx_fifo_level0
     connect \B 1'1
-    connect \Y $sub$ls180.v:4960$1460_Y
+    connect \Y $sub$ls180.v:4945$1428_Y
   end
-  attribute \src "ls180.v:5025.26-5025.50"
-  cell $sub $sub$ls180.v:5025$1465
+  attribute \src "ls180.v:5010.26-5010.50"
+  cell $sub $sub$ls180.v:5010$1433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
     parameter \B_SIGNED 0
@@ -261075,10 +260591,10 @@ module \ls180
     parameter \Y_WIDTH 20
     connect \A \libresocsim_count
     connect \B 1'1
-    connect \Y $sub$ls180.v:5025$1465_Y
+    connect \Y $sub$ls180.v:5010$1433_Y
   end
   attribute \module_not_derived 1
-  attribute \src "ls180.v:5654.13-5980.2"
+  attribute \src "ls180.v:5623.13-5949.2"
   cell \test_issuer \test_issuer
     connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck
     connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi
@@ -261262,7 +260778,7 @@ module \ls180
     connect \pc_o \libresocsim_libresoc2
     connect \pll_18_o \libresocsim_libresoc_pll_18_o
     connect \pll_lck_o \libresocsim_libresoc_pll_lck_o
-    connect \rst $or$ls180.v:5748$1626_Y
+    connect \rst $or$ls180.v:5717$1546_Y
     connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_sdram_a [0]
     connect \sdr_a_0__pad__o \sdram_a [0]
     connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_sdram_a [10]
@@ -261407,1161 +260923,1137 @@ module \ls180
     connect \sdr_we_n__pad__o \sdram_we_n
   end
   attribute \src "ls180.v:0.0-0.0"
-  process $proc$ls180.v:0$2144
+  process $proc$ls180.v:0$2057
     sync always
     sync init
   end
   attribute \src "ls180.v:0.0-0.0"
-  process $proc$ls180.v:0$2145
+  process $proc$ls180.v:0$2058
     sync always
     sync init
   end
-  attribute \src "ls180.v:1002.11-1002.29"
-  process $proc$ls180.v:1002$2021
+  attribute \src "ls180.v:1003.11-1003.29"
+  process $proc$ls180.v:1003$1942
     assign { } { }
     assign $1\i2c_storage[2:0] 3'000
     sync always
     sync init
       update \i2c_storage $1\i2c_storage[2:0]
   end
-  attribute \src "ls180.v:1003.5-1003.18"
-  process $proc$ls180.v:1003$2022
+  attribute \src "ls180.v:1004.5-1004.18"
+  process $proc$ls180.v:1004$1943
     assign { } { }
     assign $1\i2c_re[0:0] 1'0
     sync always
     sync init
       update \i2c_re $1\i2c_re[0:0]
   end
-  attribute \src "ls180.v:1007.5-1007.41"
-  process $proc$ls180.v:1007$2023
+  attribute \src "ls180.v:1008.5-1008.41"
+  process $proc$ls180.v:1008$1944
     assign { } { }
     assign $1\subfragments_converter0_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter0_state $1\subfragments_converter0_state[0:0]
   end
-  attribute \src "ls180.v:1008.5-1008.46"
-  process $proc$ls180.v:1008$2024
+  attribute \src "ls180.v:1009.5-1009.46"
+  process $proc$ls180.v:1009$1945
     assign { } { }
     assign $1\subfragments_converter0_next_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0]
   end
-  attribute \src "ls180.v:1009.5-1009.65"
-  process $proc$ls180.v:1009$2025
+  attribute \src "ls180.v:1010.5-1010.77"
+  process $proc$ls180.v:1010$1946
     assign { } { }
-    assign $1\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
+    assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0
     sync always
     sync init
-      update \converter0_counter_subfragments_converter0_next_value $1\converter0_counter_subfragments_converter0_next_value[0:0]
+      update \libresocsim_converter0_counter_subfragments_converter0_next_value $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0]
   end
-  attribute \src "ls180.v:1010.5-1010.68"
-  process $proc$ls180.v:1010$2026
+  attribute \src "ls180.v:1011.5-1011.80"
+  process $proc$ls180.v:1011$1947
     assign { } { }
-    assign $1\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
+    assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
     sync always
     sync init
-      update \converter0_counter_subfragments_converter0_next_value_ce $1\converter0_counter_subfragments_converter0_next_value_ce[0:0]
+      update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1011.5-1011.41"
-  process $proc$ls180.v:1011$2027
+  attribute \src "ls180.v:1012.5-1012.41"
+  process $proc$ls180.v:1012$1948
     assign { } { }
     assign $1\subfragments_converter1_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter1_state $1\subfragments_converter1_state[0:0]
   end
-  attribute \src "ls180.v:1012.5-1012.46"
-  process $proc$ls180.v:1012$2028
+  attribute \src "ls180.v:1013.5-1013.46"
+  process $proc$ls180.v:1013$1949
     assign { } { }
     assign $1\subfragments_converter1_next_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0]
   end
-  attribute \src "ls180.v:1013.5-1013.65"
-  process $proc$ls180.v:1013$2029
+  attribute \src "ls180.v:1014.5-1014.77"
+  process $proc$ls180.v:1014$1950
     assign { } { }
-    assign $1\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
+    assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0
     sync always
     sync init
-      update \converter1_counter_subfragments_converter1_next_value $1\converter1_counter_subfragments_converter1_next_value[0:0]
+      update \libresocsim_converter1_counter_subfragments_converter1_next_value $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0]
   end
-  attribute \src "ls180.v:1014.5-1014.68"
-  process $proc$ls180.v:1014$2030
+  attribute \src "ls180.v:1015.5-1015.80"
+  process $proc$ls180.v:1015$1951
     assign { } { }
-    assign $1\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
+    assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
     sync always
     sync init
-      update \converter1_counter_subfragments_converter1_next_value_ce $1\converter1_counter_subfragments_converter1_next_value_ce[0:0]
+      update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1015.5-1015.41"
-  process $proc$ls180.v:1015$2031
+  attribute \src "ls180.v:1016.5-1016.41"
+  process $proc$ls180.v:1016$1952
     assign { } { }
     assign $1\subfragments_converter2_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter2_state $1\subfragments_converter2_state[0:0]
   end
-  attribute \src "ls180.v:1016.5-1016.46"
-  process $proc$ls180.v:1016$2032
+  attribute \src "ls180.v:1017.5-1017.46"
+  process $proc$ls180.v:1017$1953
     assign { } { }
     assign $1\subfragments_converter2_next_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0]
   end
-  attribute \src "ls180.v:1017.5-1017.68"
-  process $proc$ls180.v:1017$2033
+  attribute \src "ls180.v:1018.5-1018.77"
+  process $proc$ls180.v:1018$1954
+    assign { } { }
+    assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_converter2_counter_subfragments_converter2_next_value $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0]
+  end
+  attribute \src "ls180.v:1019.5-1019.80"
+  process $proc$ls180.v:1019$1955
     assign { } { }
-    assign $1\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
+    assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0
     sync always
     sync init
-      update \socbushandler_counter_subfragments_converter2_next_value $1\socbushandler_counter_subfragments_converter2_next_value[0:0]
+      update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1018.5-1018.71"
-  process $proc$ls180.v:1018$2034
+  attribute \src "ls180.v:102.5-102.44"
+  process $proc$ls180.v:102$1557
     assign { } { }
-    assign $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0
+    assign $1\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
     sync always
     sync init
-      update \socbushandler_counter_subfragments_converter2_next_value_ce $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
+      update \libresocsim_libresoc_jtag_wb_ack $1\libresocsim_libresoc_jtag_wb_ack[0:0]
   end
-  attribute \src "ls180.v:1019.11-1019.46"
-  process $proc$ls180.v:1019$2035
+  attribute \src "ls180.v:1020.11-1020.46"
+  process $proc$ls180.v:1020$1956
     assign { } { }
     assign $1\subfragments_refresher_state[1:0] 2'00
     sync always
     sync init
       update \subfragments_refresher_state $1\subfragments_refresher_state[1:0]
   end
-  attribute \src "ls180.v:1020.11-1020.51"
-  process $proc$ls180.v:1020$2036
+  attribute \src "ls180.v:1021.11-1021.51"
+  process $proc$ls180.v:1021$1957
     assign { } { }
     assign $1\subfragments_refresher_next_state[1:0] 2'00
     sync always
     sync init
       update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0]
   end
-  attribute \src "ls180.v:1021.11-1021.49"
-  process $proc$ls180.v:1021$2037
+  attribute \src "ls180.v:1022.11-1022.49"
+  process $proc$ls180.v:1022$1958
     assign { } { }
     assign $1\subfragments_bankmachine0_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0]
   end
-  attribute \src "ls180.v:1022.11-1022.54"
-  process $proc$ls180.v:1022$2038
+  attribute \src "ls180.v:1023.11-1023.54"
+  process $proc$ls180.v:1023$1959
     assign { } { }
     assign $1\subfragments_bankmachine0_next_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0]
   end
-  attribute \src "ls180.v:1023.11-1023.49"
-  process $proc$ls180.v:1023$2039
+  attribute \src "ls180.v:1024.11-1024.49"
+  process $proc$ls180.v:1024$1960
     assign { } { }
     assign $1\subfragments_bankmachine1_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0]
   end
-  attribute \src "ls180.v:1024.11-1024.54"
-  process $proc$ls180.v:1024$2040
+  attribute \src "ls180.v:1025.11-1025.54"
+  process $proc$ls180.v:1025$1961
     assign { } { }
     assign $1\subfragments_bankmachine1_next_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0]
   end
-  attribute \src "ls180.v:1025.11-1025.49"
-  process $proc$ls180.v:1025$2041
+  attribute \src "ls180.v:1026.11-1026.49"
+  process $proc$ls180.v:1026$1962
     assign { } { }
     assign $1\subfragments_bankmachine2_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0]
   end
-  attribute \src "ls180.v:1026.11-1026.54"
-  process $proc$ls180.v:1026$2042
+  attribute \src "ls180.v:1027.11-1027.54"
+  process $proc$ls180.v:1027$1963
     assign { } { }
     assign $1\subfragments_bankmachine2_next_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0]
   end
-  attribute \src "ls180.v:1027.11-1027.49"
-  process $proc$ls180.v:1027$2043
+  attribute \src "ls180.v:1028.11-1028.49"
+  process $proc$ls180.v:1028$1964
     assign { } { }
     assign $1\subfragments_bankmachine3_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0]
   end
-  attribute \src "ls180.v:1028.11-1028.54"
-  process $proc$ls180.v:1028$2044
+  attribute \src "ls180.v:1029.11-1029.54"
+  process $proc$ls180.v:1029$1965
     assign { } { }
     assign $1\subfragments_bankmachine3_next_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0]
   end
-  attribute \src "ls180.v:1029.11-1029.48"
-  process $proc$ls180.v:1029$2045
+  attribute \src "ls180.v:1030.11-1030.48"
+  process $proc$ls180.v:1030$1966
     assign { } { }
     assign $1\subfragments_multiplexer_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0]
   end
-  attribute \src "ls180.v:1030.11-1030.53"
-  process $proc$ls180.v:1030$2046
+  attribute \src "ls180.v:1031.11-1031.53"
+  process $proc$ls180.v:1031$1967
     assign { } { }
     assign $1\subfragments_multiplexer_next_state[2:0] 3'000
     sync always
     sync init
       update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0]
   end
-  attribute \src "ls180.v:104.11-104.50"
-  process $proc$ls180.v:104$1649
+  attribute \src "ls180.v:104.5-104.44"
+  process $proc$ls180.v:104$1558
     assign { } { }
-    assign $0\libresocsim_libresoc_jtag_wb_cti[2:0] 3'000
+    assign $0\libresocsim_libresoc_jtag_wb_err[0:0] 1'0
     sync always
-      update \libresocsim_libresoc_jtag_wb_cti $0\libresocsim_libresoc_jtag_wb_cti[2:0]
+      update \libresocsim_libresoc_jtag_wb_err $0\libresocsim_libresoc_jtag_wb_err[0:0]
     sync init
   end
-  attribute \src "ls180.v:1043.5-1043.32"
-  process $proc$ls180.v:1043$2047
+  attribute \src "ls180.v:1044.5-1044.32"
+  process $proc$ls180.v:1044$1968
     assign { } { }
     assign $0\subfragments_locked0[0:0] 1'0
     sync always
       update \subfragments_locked0 $0\subfragments_locked0[0:0]
     sync init
   end
-  attribute \src "ls180.v:1044.5-1044.32"
-  process $proc$ls180.v:1044$2048
+  attribute \src "ls180.v:1045.5-1045.32"
+  process $proc$ls180.v:1045$1969
     assign { } { }
     assign $0\subfragments_locked1[0:0] 1'0
     sync always
       update \subfragments_locked1 $0\subfragments_locked1[0:0]
     sync init
   end
-  attribute \src "ls180.v:1045.5-1045.32"
-  process $proc$ls180.v:1045$2049
+  attribute \src "ls180.v:1046.5-1046.32"
+  process $proc$ls180.v:1046$1970
     assign { } { }
     assign $0\subfragments_locked2[0:0] 1'0
     sync always
       update \subfragments_locked2 $0\subfragments_locked2[0:0]
     sync init
   end
-  attribute \src "ls180.v:1046.5-1046.32"
-  process $proc$ls180.v:1046$2050
+  attribute \src "ls180.v:1047.5-1047.32"
+  process $proc$ls180.v:1047$1971
     assign { } { }
     assign $0\subfragments_locked3[0:0] 1'0
     sync always
       update \subfragments_locked3 $0\subfragments_locked3[0:0]
     sync init
   end
-  attribute \src "ls180.v:1047.5-1047.47"
-  process $proc$ls180.v:1047$2051
+  attribute \src "ls180.v:1048.5-1048.47"
+  process $proc$ls180.v:1048$1972
     assign { } { }
     assign $1\subfragments_new_master_wdata_ready[0:0] 1'0
     sync always
     sync init
       update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:1048.5-1048.48"
-  process $proc$ls180.v:1048$2052
+  attribute \src "ls180.v:1049.5-1049.48"
+  process $proc$ls180.v:1049$1973
     assign { } { }
     assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0
     sync always
     sync init
       update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0]
   end
-  attribute \src "ls180.v:1049.5-1049.48"
-  process $proc$ls180.v:1049$2053
+  attribute \src "ls180.v:1050.5-1050.48"
+  process $proc$ls180.v:1050$1974
     assign { } { }
     assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0
     sync always
     sync init
       update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0]
   end
-  attribute \src "ls180.v:105.11-105.50"
-  process $proc$ls180.v:105$1650
-    assign { } { }
-    assign $0\libresocsim_libresoc_jtag_wb_bte[1:0] 2'00
-    sync always
-      update \libresocsim_libresoc_jtag_wb_bte $0\libresocsim_libresoc_jtag_wb_bte[1:0]
-    sync init
-  end
-  attribute \src "ls180.v:1050.5-1050.48"
-  process $proc$ls180.v:1050$2054
+  attribute \src "ls180.v:1051.5-1051.48"
+  process $proc$ls180.v:1051$1975
     assign { } { }
     assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0
     sync always
     sync init
       update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0]
   end
-  attribute \src "ls180.v:1051.5-1051.48"
-  process $proc$ls180.v:1051$2055
+  attribute \src "ls180.v:1052.5-1052.48"
+  process $proc$ls180.v:1052$1976
     assign { } { }
     assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0
     sync always
     sync init
       update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0]
   end
-  attribute \src "ls180.v:1052.5-1052.30"
-  process $proc$ls180.v:1052$2056
+  attribute \src "ls180.v:1053.5-1053.30"
+  process $proc$ls180.v:1053$1977
     assign { } { }
     assign $1\subfragments_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_state $1\subfragments_state[0:0]
   end
-  attribute \src "ls180.v:1053.5-1053.35"
-  process $proc$ls180.v:1053$2057
+  attribute \src "ls180.v:1054.5-1054.35"
+  process $proc$ls180.v:1054$1978
     assign { } { }
     assign $1\subfragments_next_state[0:0] 1'0
     sync always
     sync init
       update \subfragments_next_state $1\subfragments_next_state[0:0]
   end
-  attribute \src "ls180.v:1054.5-1054.53"
-  process $proc$ls180.v:1054$2058
+  attribute \src "ls180.v:1055.5-1055.53"
+  process $proc$ls180.v:1055$1979
     assign { } { }
     assign $1\converter_counter_subfragments_next_value[0:0] 1'0
     sync always
     sync init
       update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0]
   end
-  attribute \src "ls180.v:1055.5-1055.56"
-  process $proc$ls180.v:1055$2059
+  attribute \src "ls180.v:1056.5-1056.56"
+  process $proc$ls180.v:1056$1980
     assign { } { }
     assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0
     sync always
     sync init
       update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:1056.12-1056.47"
-  process $proc$ls180.v:1056$2060
+  attribute \src "ls180.v:1057.12-1057.47"
+  process $proc$ls180.v:1057$1981
     assign { } { }
     assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000
     sync always
     sync init
       update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0]
   end
-  attribute \src "ls180.v:1057.5-1057.38"
-  process $proc$ls180.v:1057$2061
+  attribute \src "ls180.v:1058.5-1058.38"
+  process $proc$ls180.v:1058$1982
     assign { } { }
     assign $1\libresocsim_libresocsim_we[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0]
   end
-  attribute \src "ls180.v:1058.11-1058.47"
-  process $proc$ls180.v:1058$2062
+  attribute \src "ls180.v:1059.11-1059.47"
+  process $proc$ls180.v:1059$1983
     assign { } { }
     assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0]
   end
-  attribute \src "ls180.v:1060.12-1060.56"
-  process $proc$ls180.v:1060$2063
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000
-    sync always
-      update \libresocsim_libresocsim_wishbone_adr $0\libresocsim_libresocsim_wishbone_adr[29:0]
-    sync init
-  end
-  attribute \src "ls180.v:1061.12-1061.58"
-  process $proc$ls180.v:1061$2064
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_dat_w[31:0] 0
-    sync always
-      update \libresocsim_libresocsim_wishbone_dat_w $0\libresocsim_libresocsim_wishbone_dat_w[31:0]
-    sync init
-  end
-  attribute \src "ls180.v:1062.12-1062.58"
-  process $proc$ls180.v:1062$2065
+  attribute \src "ls180.v:1063.12-1063.58"
+  process $proc$ls180.v:1063$1984
     assign { } { }
     assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0
     sync always
     sync init
       update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0]
   end
-  attribute \src "ls180.v:1063.11-1063.54"
-  process $proc$ls180.v:1063$2066
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_sel[3:0] 4'0000
-    sync always
-      update \libresocsim_libresocsim_wishbone_sel $0\libresocsim_libresocsim_wishbone_sel[3:0]
-    sync init
-  end
-  attribute \src "ls180.v:1064.5-1064.48"
-  process $proc$ls180.v:1064$2067
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_cyc[0:0] 1'0
-    sync always
-      update \libresocsim_libresocsim_wishbone_cyc $0\libresocsim_libresocsim_wishbone_cyc[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1065.5-1065.48"
-  process $proc$ls180.v:1065$2068
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_stb[0:0] 1'0
-    sync always
-      update \libresocsim_libresocsim_wishbone_stb $0\libresocsim_libresocsim_wishbone_stb[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1066.5-1066.48"
-  process $proc$ls180.v:1066$2069
+  attribute \src "ls180.v:1067.5-1067.48"
+  process $proc$ls180.v:1067$1985
     assign { } { }
     assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0]
   end
-  attribute \src "ls180.v:1067.5-1067.47"
-  process $proc$ls180.v:1067$2070
-    assign { } { }
-    assign $0\libresocsim_libresocsim_wishbone_we[0:0] 1'0
-    sync always
-      update \libresocsim_libresocsim_wishbone_we $0\libresocsim_libresocsim_wishbone_we[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1070.12-1070.69"
-  process $proc$ls180.v:1070$2071
-    assign { } { }
-    assign $0\libresocsim_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync always
-      update \libresocsim_libresocsim_converted_interface_dat_r $0\libresocsim_libresocsim_converted_interface_dat_r[63:0]
-    sync init
-  end
-  attribute \src "ls180.v:1074.5-1074.59"
-  process $proc$ls180.v:1074$2072
-    assign { } { }
-    assign $0\libresocsim_libresocsim_converted_interface_ack[0:0] 1'0
-    sync always
-      update \libresocsim_libresocsim_converted_interface_ack $0\libresocsim_libresocsim_converted_interface_ack[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1078.5-1078.59"
-  process $proc$ls180.v:1078$2073
+  attribute \src "ls180.v:1071.5-1071.48"
+  process $proc$ls180.v:1071$1986
     assign { } { }
-    assign $0\libresocsim_libresocsim_converted_interface_err[0:0] 1'0
+    assign $0\libresocsim_libresocsim_wishbone_err[0:0] 1'0
     sync always
-      update \libresocsim_libresocsim_converted_interface_err $0\libresocsim_libresocsim_converted_interface_err[0:0]
+      update \libresocsim_libresocsim_wishbone_err $0\libresocsim_libresocsim_wishbone_err[0:0]
     sync init
   end
-  attribute \src "ls180.v:1081.12-1081.44"
-  process $proc$ls180.v:1081$2074
+  attribute \src "ls180.v:1074.12-1074.44"
+  process $proc$ls180.v:1074$1987
     assign { } { }
     assign $1\libresocsim_shared_dat_r[31:0] 0
     sync always
     sync init
       update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0]
   end
-  attribute \src "ls180.v:1085.5-1085.34"
-  process $proc$ls180.v:1085$2075
+  attribute \src "ls180.v:1078.5-1078.34"
+  process $proc$ls180.v:1078$1988
     assign { } { }
     assign $1\libresocsim_shared_ack[0:0] 1'0
     sync always
     sync init
       update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0]
   end
-  attribute \src "ls180.v:1091.11-1091.35"
-  process $proc$ls180.v:1091$2076
+  attribute \src "ls180.v:1084.11-1084.35"
+  process $proc$ls180.v:1084$1989
     assign { } { }
     assign $1\libresocsim_grant[1:0] 2'00
     sync always
     sync init
       update \libresocsim_grant $1\libresocsim_grant[1:0]
   end
-  attribute \src "ls180.v:1092.11-1092.39"
-  process $proc$ls180.v:1092$2077
+  attribute \src "ls180.v:1085.11-1085.39"
+  process $proc$ls180.v:1085$1990
     assign { } { }
     assign $1\libresocsim_slave_sel[5:0] 6'000000
     sync always
     sync init
       update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0]
   end
-  attribute \src "ls180.v:1093.11-1093.41"
-  process $proc$ls180.v:1093$2078
+  attribute \src "ls180.v:1086.11-1086.41"
+  process $proc$ls180.v:1086$1991
     assign { } { }
     assign $1\libresocsim_slave_sel_r[5:0] 6'000000
     sync always
     sync init
       update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0]
   end
-  attribute \src "ls180.v:1094.5-1094.29"
-  process $proc$ls180.v:1094$2079
+  attribute \src "ls180.v:1087.5-1087.29"
+  process $proc$ls180.v:1087$1992
     assign { } { }
     assign $1\libresocsim_error[0:0] 1'0
     sync always
     sync init
       update \libresocsim_error $1\libresocsim_error[0:0]
   end
-  attribute \src "ls180.v:1097.12-1097.43"
-  process $proc$ls180.v:1097$2080
+  attribute \src "ls180.v:1090.12-1090.43"
+  process $proc$ls180.v:1090$1993
     assign { } { }
     assign $1\libresocsim_count[19:0] 20'11110100001001000000
     sync always
     sync init
       update \libresocsim_count $1\libresocsim_count[19:0]
   end
-  attribute \src "ls180.v:1101.11-1101.55"
-  process $proc$ls180.v:1101$2081
+  attribute \src "ls180.v:1094.11-1094.55"
+  process $proc$ls180.v:1094$1994
     assign { } { }
     assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1142.11-1142.55"
-  process $proc$ls180.v:1142$2082
+  attribute \src "ls180.v:1135.11-1135.55"
+  process $proc$ls180.v:1135$1995
     assign { } { }
     assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1159.11-1159.55"
-  process $proc$ls180.v:1159$2083
+  attribute \src "ls180.v:115.5-115.58"
+  process $proc$ls180.v:115$1559
+    assign { } { }
+    assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+    sync always
+    sync init
+      update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+  end
+  attribute \src "ls180.v:1152.11-1152.55"
+  process $proc$ls180.v:1152$1996
     assign { } { }
     assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1176.11-1176.55"
-  process $proc$ls180.v:1176$2084
+  attribute \src "ls180.v:116.5-116.58"
+  process $proc$ls180.v:116$1560
     assign { } { }
-    assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000
+    assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
     sync always
+      update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
     sync init
-      update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:118.12-118.65"
-  process $proc$ls180.v:118$1651
+  attribute \src "ls180.v:1169.11-1169.55"
+  process $proc$ls180.v:1169$1997
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
+    assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+      update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1189.11-1189.55"
-  process $proc$ls180.v:1189$2085
+  attribute \src "ls180.v:1182.11-1182.55"
+  process $proc$ls180.v:1182$1998
     assign { } { }
     assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:119.12-119.66"
-  process $proc$ls180.v:119$1652
+  attribute \src "ls180.v:120.12-120.66"
+  process $proc$ls180.v:120$1561
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
   end
-  attribute \src "ls180.v:120.5-120.58"
-  process $proc$ls180.v:120$1653
+  attribute \src "ls180.v:122.12-122.69"
+  process $proc$ls180.v:122$1562
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
   end
-  attribute \src "ls180.v:121.5-121.58"
-  process $proc$ls180.v:121$1654
+  attribute \src "ls180.v:1223.11-1223.55"
+  process $proc$ls180.v:1223$1999
     assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
+    assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000
     sync always
-      update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
     sync init
+      update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:122.12-122.66"
-  process $proc$ls180.v:122$1655
+  attribute \src "ls180.v:123.5-123.62"
+  process $proc$ls180.v:123$1563
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
   end
-  attribute \src "ls180.v:1230.11-1230.55"
-  process $proc$ls180.v:1230$2086
+  attribute \src "ls180.v:124.5-124.61"
+  process $proc$ls180.v:124$1564
     assign { } { }
-    assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
-  end
-  attribute \src "ls180.v:124.12-124.69"
-  process $proc$ls180.v:124$1656
-    assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
   end
   attribute \src "ls180.v:125.5-125.62"
-  process $proc$ls180.v:125$1657
-    assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
-  end
-  attribute \src "ls180.v:126.5-126.61"
-  process $proc$ls180.v:126$1658
-    assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
-  end
-  attribute \src "ls180.v:127.5-127.62"
-  process $proc$ls180.v:127$1659
+  process $proc$ls180.v:125$1565
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
   end
-  attribute \src "ls180.v:128.5-128.62"
-  process $proc$ls180.v:128$1660
+  attribute \src "ls180.v:126.5-126.62"
+  process $proc$ls180.v:126$1566
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
   end
-  attribute \src "ls180.v:129.5-129.61"
-  process $proc$ls180.v:129$1661
+  attribute \src "ls180.v:127.5-127.61"
+  process $proc$ls180.v:127$1567
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
   end
-  attribute \src "ls180.v:1295.11-1295.55"
-  process $proc$ls180.v:1295$2087
+  attribute \src "ls180.v:128.5-128.60"
+  process $proc$ls180.v:128$1568
     assign { } { }
-    assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
   end
-  attribute \src "ls180.v:130.5-130.60"
-  process $proc$ls180.v:130$1662
+  attribute \src "ls180.v:1288.11-1288.55"
+  process $proc$ls180.v:1288$2000
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
+    assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
+      update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:131.11-131.65"
-  process $proc$ls180.v:131$1663
+  attribute \src "ls180.v:129.11-129.65"
+  process $proc$ls180.v:129$1569
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
   end
-  attribute \src "ls180.v:132.11-132.65"
-  process $proc$ls180.v:132$1664
+  attribute \src "ls180.v:130.11-130.65"
+  process $proc$ls180.v:130$1570
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
   end
-  attribute \src "ls180.v:1320.11-1320.55"
-  process $proc$ls180.v:1320$2088
-    assign { } { }
-    assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000
-    sync always
-    sync init
-      update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0]
-  end
-  attribute \src "ls180.v:133.5-133.62"
-  process $proc$ls180.v:133$1665
+  attribute \src "ls180.v:131.5-131.62"
+  process $proc$ls180.v:131$1571
     assign { } { }
     assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
   end
-  attribute \src "ls180.v:134.5-134.64"
-  process $proc$ls180.v:134$1666
+  attribute \src "ls180.v:1313.11-1313.55"
+  process $proc$ls180.v:1313$2001
     assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
+    assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000
     sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
     sync init
+      update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1342.11-1342.35"
-  process $proc$ls180.v:1342$2089
+  attribute \src "ls180.v:1335.11-1335.35"
+  process $proc$ls180.v:1335$2002
     assign { } { }
     assign $1\libresocsim_state[1:0] 2'00
     sync always
     sync init
       update \libresocsim_state $1\libresocsim_state[1:0]
   end
-  attribute \src "ls180.v:1343.11-1343.40"
-  process $proc$ls180.v:1343$2090
+  attribute \src "ls180.v:1336.11-1336.40"
+  process $proc$ls180.v:1336$2003
     assign { } { }
     assign $1\libresocsim_next_state[1:0] 2'00
     sync always
     sync init
       update \libresocsim_next_state $1\libresocsim_next_state[1:0]
   end
-  attribute \src "ls180.v:1344.11-1344.71"
-  process $proc$ls180.v:1344$2091
+  attribute \src "ls180.v:1337.11-1337.71"
+  process $proc$ls180.v:1337$2004
     assign { } { }
     assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000
     sync always
     sync init
       update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
   end
-  attribute \src "ls180.v:1345.5-1345.68"
-  process $proc$ls180.v:1345$2092
+  attribute \src "ls180.v:1338.5-1338.68"
+  process $proc$ls180.v:1338$2005
     assign { } { }
     assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
   end
-  attribute \src "ls180.v:1346.12-1346.71"
-  process $proc$ls180.v:1346$2093
+  attribute \src "ls180.v:1339.12-1339.71"
+  process $proc$ls180.v:1339$2006
     assign { } { }
     assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000
     sync always
     sync init
       update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
   end
-  attribute \src "ls180.v:1347.5-1347.66"
-  process $proc$ls180.v:1347$2094
+  attribute \src "ls180.v:1340.5-1340.66"
+  process $proc$ls180.v:1340$2007
     assign { } { }
     assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
   end
-  attribute \src "ls180.v:1348.5-1348.62"
-  process $proc$ls180.v:1348$2095
+  attribute \src "ls180.v:1341.5-1341.62"
+  process $proc$ls180.v:1341$2008
     assign { } { }
     assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
   end
-  attribute \src "ls180.v:1349.5-1349.65"
-  process $proc$ls180.v:1349$2096
+  attribute \src "ls180.v:1342.5-1342.65"
+  process $proc$ls180.v:1342$2009
     assign { } { }
     assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0
     sync always
     sync init
       update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:135.5-135.65"
-  process $proc$ls180.v:135$1667
-    assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
-    sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1350.5-1350.28"
-  process $proc$ls180.v:1350$2097
+  attribute \src "ls180.v:1343.5-1343.28"
+  process $proc$ls180.v:1343$2010
     assign { } { }
     assign $1\rhs_array_muxed0[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:1351.12-1351.36"
-  process $proc$ls180.v:1351$2098
+  attribute \src "ls180.v:1344.12-1344.36"
+  process $proc$ls180.v:1344$2011
     assign { } { }
     assign $1\rhs_array_muxed1[12:0] 13'0000000000000
     sync always
     sync init
       update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:1352.11-1352.34"
-  process $proc$ls180.v:1352$2099
+  attribute \src "ls180.v:1345.11-1345.34"
+  process $proc$ls180.v:1345$2012
     assign { } { }
     assign $1\rhs_array_muxed2[1:0] 2'00
     sync always
     sync init
       update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0]
   end
-  attribute \src "ls180.v:1353.5-1353.28"
-  process $proc$ls180.v:1353$2100
+  attribute \src "ls180.v:1346.5-1346.28"
+  process $proc$ls180.v:1346$2013
     assign { } { }
     assign $1\rhs_array_muxed3[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:1354.5-1354.28"
-  process $proc$ls180.v:1354$2101
+  attribute \src "ls180.v:1347.5-1347.28"
+  process $proc$ls180.v:1347$2014
     assign { } { }
     assign $1\rhs_array_muxed4[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:1355.5-1355.28"
-  process $proc$ls180.v:1355$2102
+  attribute \src "ls180.v:1348.5-1348.28"
+  process $proc$ls180.v:1348$2015
     assign { } { }
     assign $1\rhs_array_muxed5[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:1356.5-1356.26"
-  process $proc$ls180.v:1356$2103
+  attribute \src "ls180.v:1349.5-1349.26"
+  process $proc$ls180.v:1349$2016
     assign { } { }
     assign $1\t_array_muxed0[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed0 $1\t_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:1357.5-1357.26"
-  process $proc$ls180.v:1357$2104
+  attribute \src "ls180.v:1350.5-1350.26"
+  process $proc$ls180.v:1350$2017
     assign { } { }
     assign $1\t_array_muxed1[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed1 $1\t_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:1358.5-1358.26"
-  process $proc$ls180.v:1358$2105
+  attribute \src "ls180.v:1351.5-1351.26"
+  process $proc$ls180.v:1351$2018
     assign { } { }
     assign $1\t_array_muxed2[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed2 $1\t_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:1359.5-1359.28"
-  process $proc$ls180.v:1359$2106
+  attribute \src "ls180.v:1352.5-1352.28"
+  process $proc$ls180.v:1352$2019
     assign { } { }
     assign $1\rhs_array_muxed6[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:136.5-136.65"
-  process $proc$ls180.v:136$1668
-    assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
-    sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1360.12-1360.36"
-  process $proc$ls180.v:1360$2107
+  attribute \src "ls180.v:1353.12-1353.36"
+  process $proc$ls180.v:1353$2020
     assign { } { }
     assign $1\rhs_array_muxed7[12:0] 13'0000000000000
     sync always
     sync init
       update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0]
   end
-  attribute \src "ls180.v:1361.11-1361.34"
-  process $proc$ls180.v:1361$2108
+  attribute \src "ls180.v:1354.11-1354.34"
+  process $proc$ls180.v:1354$2021
     assign { } { }
     assign $1\rhs_array_muxed8[1:0] 2'00
     sync always
     sync init
       update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0]
   end
-  attribute \src "ls180.v:1362.5-1362.28"
-  process $proc$ls180.v:1362$2109
+  attribute \src "ls180.v:1355.5-1355.28"
+  process $proc$ls180.v:1355$2022
     assign { } { }
     assign $1\rhs_array_muxed9[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0]
   end
-  attribute \src "ls180.v:1363.5-1363.29"
-  process $proc$ls180.v:1363$2110
+  attribute \src "ls180.v:1356.5-1356.29"
+  process $proc$ls180.v:1356$2023
     assign { } { }
     assign $1\rhs_array_muxed10[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0]
   end
-  attribute \src "ls180.v:1364.5-1364.29"
-  process $proc$ls180.v:1364$2111
+  attribute \src "ls180.v:1357.5-1357.29"
+  process $proc$ls180.v:1357$2024
     assign { } { }
     assign $1\rhs_array_muxed11[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0]
   end
-  attribute \src "ls180.v:1365.5-1365.26"
-  process $proc$ls180.v:1365$2112
+  attribute \src "ls180.v:1358.5-1358.26"
+  process $proc$ls180.v:1358$2025
     assign { } { }
     assign $1\t_array_muxed3[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed3 $1\t_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:1366.5-1366.26"
-  process $proc$ls180.v:1366$2113
+  attribute \src "ls180.v:1359.5-1359.26"
+  process $proc$ls180.v:1359$2026
     assign { } { }
     assign $1\t_array_muxed4[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed4 $1\t_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:1367.5-1367.26"
-  process $proc$ls180.v:1367$2114
+  attribute \src "ls180.v:136.5-136.64"
+  process $proc$ls180.v:136$1572
+    assign { } { }
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:1360.5-1360.26"
+  process $proc$ls180.v:1360$2027
     assign { } { }
     assign $1\t_array_muxed5[0:0] 1'0
     sync always
     sync init
       update \t_array_muxed5 $1\t_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:1368.12-1368.37"
-  process $proc$ls180.v:1368$2115
+  attribute \src "ls180.v:1361.12-1361.37"
+  process $proc$ls180.v:1361$2028
     assign { } { }
     assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0]
   end
-  attribute \src "ls180.v:1369.5-1369.29"
-  process $proc$ls180.v:1369$2116
+  attribute \src "ls180.v:1362.5-1362.29"
+  process $proc$ls180.v:1362$2029
     assign { } { }
     assign $1\rhs_array_muxed13[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0]
   end
-  attribute \src "ls180.v:1370.5-1370.29"
-  process $proc$ls180.v:1370$2117
+  attribute \src "ls180.v:1363.5-1363.29"
+  process $proc$ls180.v:1363$2030
     assign { } { }
     assign $1\rhs_array_muxed14[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0]
   end
-  attribute \src "ls180.v:1371.12-1371.37"
-  process $proc$ls180.v:1371$2118
+  attribute \src "ls180.v:1364.12-1364.37"
+  process $proc$ls180.v:1364$2031
     assign { } { }
     assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0]
   end
-  attribute \src "ls180.v:1372.5-1372.29"
-  process $proc$ls180.v:1372$2119
+  attribute \src "ls180.v:1365.5-1365.29"
+  process $proc$ls180.v:1365$2032
     assign { } { }
     assign $1\rhs_array_muxed16[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0]
   end
-  attribute \src "ls180.v:1373.5-1373.29"
-  process $proc$ls180.v:1373$2120
+  attribute \src "ls180.v:1366.5-1366.29"
+  process $proc$ls180.v:1366$2033
     assign { } { }
     assign $1\rhs_array_muxed17[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0]
   end
-  attribute \src "ls180.v:1374.12-1374.37"
-  process $proc$ls180.v:1374$2121
+  attribute \src "ls180.v:1367.12-1367.37"
+  process $proc$ls180.v:1367$2034
     assign { } { }
     assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0]
   end
-  attribute \src "ls180.v:1375.5-1375.29"
-  process $proc$ls180.v:1375$2122
+  attribute \src "ls180.v:1368.5-1368.29"
+  process $proc$ls180.v:1368$2035
     assign { } { }
     assign $1\rhs_array_muxed19[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0]
   end
-  attribute \src "ls180.v:1376.5-1376.29"
-  process $proc$ls180.v:1376$2123
+  attribute \src "ls180.v:1369.5-1369.29"
+  process $proc$ls180.v:1369$2036
     assign { } { }
     assign $1\rhs_array_muxed20[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0]
   end
-  attribute \src "ls180.v:1377.12-1377.37"
-  process $proc$ls180.v:1377$2124
+  attribute \src "ls180.v:137.5-137.65"
+  process $proc$ls180.v:137$1573
+    assign { } { }
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:1370.12-1370.37"
+  process $proc$ls180.v:1370$2037
     assign { } { }
     assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0]
   end
-  attribute \src "ls180.v:1378.5-1378.29"
-  process $proc$ls180.v:1378$2125
+  attribute \src "ls180.v:1371.5-1371.29"
+  process $proc$ls180.v:1371$2038
     assign { } { }
     assign $1\rhs_array_muxed22[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0]
   end
-  attribute \src "ls180.v:1379.5-1379.29"
-  process $proc$ls180.v:1379$2126
+  attribute \src "ls180.v:1372.5-1372.29"
+  process $proc$ls180.v:1372$2039
     assign { } { }
     assign $1\rhs_array_muxed23[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0]
   end
-  attribute \src "ls180.v:1380.12-1380.37"
-  process $proc$ls180.v:1380$2127
+  attribute \src "ls180.v:1373.12-1373.37"
+  process $proc$ls180.v:1373$2040
     assign { } { }
-    assign $1\rhs_array_muxed24[28:0] 29'00000000000000000000000000000
+    assign $1\rhs_array_muxed24[29:0] 30'000000000000000000000000000000
     sync always
     sync init
-      update \rhs_array_muxed24 $1\rhs_array_muxed24[28:0]
+      update \rhs_array_muxed24 $1\rhs_array_muxed24[29:0]
   end
-  attribute \src "ls180.v:1381.12-1381.37"
-  process $proc$ls180.v:1381$2128
+  attribute \src "ls180.v:1374.12-1374.37"
+  process $proc$ls180.v:1374$2041
     assign { } { }
-    assign $1\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign $1\rhs_array_muxed25[31:0] 0
     sync always
     sync init
-      update \rhs_array_muxed25 $1\rhs_array_muxed25[63:0]
+      update \rhs_array_muxed25 $1\rhs_array_muxed25[31:0]
   end
-  attribute \src "ls180.v:1382.11-1382.35"
-  process $proc$ls180.v:1382$2129
+  attribute \src "ls180.v:1375.11-1375.35"
+  process $proc$ls180.v:1375$2042
     assign { } { }
-    assign $1\rhs_array_muxed26[7:0] 8'00000000
+    assign $1\rhs_array_muxed26[3:0] 4'0000
     sync always
     sync init
-      update \rhs_array_muxed26 $1\rhs_array_muxed26[7:0]
+      update \rhs_array_muxed26 $1\rhs_array_muxed26[3:0]
   end
-  attribute \src "ls180.v:1383.5-1383.29"
-  process $proc$ls180.v:1383$2130
+  attribute \src "ls180.v:1376.5-1376.29"
+  process $proc$ls180.v:1376$2043
     assign { } { }
     assign $1\rhs_array_muxed27[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0]
   end
-  attribute \src "ls180.v:1384.5-1384.29"
-  process $proc$ls180.v:1384$2131
+  attribute \src "ls180.v:1377.5-1377.29"
+  process $proc$ls180.v:1377$2044
     assign { } { }
     assign $1\rhs_array_muxed28[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0]
   end
-  attribute \src "ls180.v:1385.5-1385.29"
-  process $proc$ls180.v:1385$2132
+  attribute \src "ls180.v:1378.5-1378.29"
+  process $proc$ls180.v:1378$2045
     assign { } { }
     assign $1\rhs_array_muxed29[0:0] 1'0
     sync always
     sync init
       update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0]
   end
-  attribute \src "ls180.v:1386.11-1386.35"
-  process $proc$ls180.v:1386$2133
+  attribute \src "ls180.v:1379.11-1379.35"
+  process $proc$ls180.v:1379$2046
     assign { } { }
     assign $1\rhs_array_muxed30[2:0] 3'000
     sync always
     sync init
       update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0]
   end
-  attribute \src "ls180.v:1387.11-1387.35"
-  process $proc$ls180.v:1387$2134
+  attribute \src "ls180.v:138.5-138.65"
+  process $proc$ls180.v:138$1574
+    assign { } { }
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:1380.11-1380.35"
+  process $proc$ls180.v:1380$2047
     assign { } { }
     assign $1\rhs_array_muxed31[1:0] 2'00
     sync always
     sync init
       update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0]
   end
-  attribute \src "ls180.v:1388.11-1388.30"
-  process $proc$ls180.v:1388$2135
+  attribute \src "ls180.v:1381.11-1381.30"
+  process $proc$ls180.v:1381$2048
     assign { } { }
     assign $1\array_muxed0[1:0] 2'00
     sync always
     sync init
       update \array_muxed0 $1\array_muxed0[1:0]
   end
-  attribute \src "ls180.v:1389.12-1389.32"
-  process $proc$ls180.v:1389$2136
+  attribute \src "ls180.v:1382.12-1382.32"
+  process $proc$ls180.v:1382$2049
     assign { } { }
     assign $1\array_muxed1[12:0] 13'0000000000000
     sync always
     sync init
       update \array_muxed1 $1\array_muxed1[12:0]
   end
-  attribute \src "ls180.v:1390.5-1390.24"
-  process $proc$ls180.v:1390$2137
+  attribute \src "ls180.v:1383.5-1383.24"
+  process $proc$ls180.v:1383$2050
     assign { } { }
     assign $1\array_muxed2[0:0] 1'0
     sync always
     sync init
       update \array_muxed2 $1\array_muxed2[0:0]
   end
-  attribute \src "ls180.v:1391.5-1391.24"
-  process $proc$ls180.v:1391$2138
+  attribute \src "ls180.v:1384.5-1384.24"
+  process $proc$ls180.v:1384$2051
     assign { } { }
     assign $1\array_muxed3[0:0] 1'0
     sync always
     sync init
       update \array_muxed3 $1\array_muxed3[0:0]
   end
-  attribute \src "ls180.v:1392.5-1392.24"
-  process $proc$ls180.v:1392$2139
+  attribute \src "ls180.v:1385.5-1385.24"
+  process $proc$ls180.v:1385$2052
     assign { } { }
     assign $1\array_muxed4[0:0] 1'0
     sync always
     sync init
       update \array_muxed4 $1\array_muxed4[0:0]
   end
-  attribute \src "ls180.v:1393.5-1393.24"
-  process $proc$ls180.v:1393$2140
+  attribute \src "ls180.v:1386.5-1386.24"
+  process $proc$ls180.v:1386$2053
     assign { } { }
     assign $1\array_muxed5[0:0] 1'0
     sync always
     sync init
       update \array_muxed5 $1\array_muxed5[0:0]
   end
-  attribute \src "ls180.v:1394.5-1394.24"
-  process $proc$ls180.v:1394$2141
+  attribute \src "ls180.v:1387.5-1387.24"
+  process $proc$ls180.v:1387$2054
     assign { } { }
     assign $1\array_muxed6[0:0] 1'0
     sync always
     sync init
       update \array_muxed6 $1\array_muxed6[0:0]
   end
-  attribute \src "ls180.v:1451.32-1451.44"
-  process $proc$ls180.v:1451$2142
+  attribute \src "ls180.v:141.12-141.65"
+  process $proc$ls180.v:141$1575
+    assign { } { }
+    assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+  end
+  attribute \src "ls180.v:142.12-142.66"
+  process $proc$ls180.v:142$1576
+    assign { } { }
+    assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+  end
+  attribute \src "ls180.v:143.12-143.66"
+  process $proc$ls180.v:143$1577
+    assign { } { }
+    assign $1\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    sync always
+    sync init
+      update \libresocsim_interface0_converted_interface_adr $1\libresocsim_interface0_converted_interface_adr[29:0]
+  end
+  attribute \src "ls180.v:144.12-144.68"
+  process $proc$ls180.v:144$1578
+    assign { } { }
+    assign $1\libresocsim_interface0_converted_interface_dat_w[31:0] 0
+    sync always
+    sync init
+      update \libresocsim_interface0_converted_interface_dat_w $1\libresocsim_interface0_converted_interface_dat_w[31:0]
+  end
+  attribute \src "ls180.v:1444.32-1444.44"
+  process $proc$ls180.v:1444$2055
     assign { } { }
     assign $1\regs0[0:0] 1'0
     sync always
     sync init
       update \regs0 $1\regs0[0:0]
   end
-  attribute \src "ls180.v:1452.32-1452.44"
-  process $proc$ls180.v:1452$2143
+  attribute \src "ls180.v:1445.32-1445.44"
+  process $proc$ls180.v:1445$2056
     assign { } { }
     assign $1\regs1[0:0] 1'0
     sync always
     sync init
       update \regs1 $1\regs1[0:0]
   end
-  attribute \src "ls180.v:1506.1-1511.4"
-  process $proc$ls180.v:1506$23
+  attribute \src "ls180.v:146.11-146.64"
+  process $proc$ls180.v:146$1579
+    assign { } { }
+    assign $1\libresocsim_interface0_converted_interface_sel[3:0] 4'0000
+    sync always
+    sync init
+      update \libresocsim_interface0_converted_interface_sel $1\libresocsim_interface0_converted_interface_sel[3:0]
+  end
+  attribute \src "ls180.v:147.5-147.58"
+  process $proc$ls180.v:147$1580
+    assign { } { }
+    assign $1\libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_interface0_converted_interface_cyc $1\libresocsim_interface0_converted_interface_cyc[0:0]
+  end
+  attribute \src "ls180.v:148.5-148.58"
+  process $proc$ls180.v:148$1581
+    assign { } { }
+    assign $1\libresocsim_interface0_converted_interface_stb[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_interface0_converted_interface_stb $1\libresocsim_interface0_converted_interface_stb[0:0]
+  end
+  attribute \src "ls180.v:1499.1-1504.4"
+  process $proc$ls180.v:1499$15
     assign { } { }
     assign { } { }
     assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0
@@ -262570,16 +262062,24 @@ module \ls180
     sync always
       update \eint_tmp $0\eint_tmp[2:0]
   end
-  attribute \src "ls180.v:151.5-151.35"
-  process $proc$ls180.v:151$1669
+  attribute \src "ls180.v:150.5-150.57"
+  process $proc$ls180.v:150$1582
     assign { } { }
-    assign $1\libresocsim_ram_bus_ack[0:0] 1'0
+    assign $1\libresocsim_interface0_converted_interface_we[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0]
+      update \libresocsim_interface0_converted_interface_we $1\libresocsim_interface0_converted_interface_we[0:0]
+  end
+  attribute \src "ls180.v:151.11-151.64"
+  process $proc$ls180.v:151$1583
+    assign { } { }
+    assign $0\libresocsim_interface0_converted_interface_cti[2:0] 3'000
+    sync always
+      update \libresocsim_interface0_converted_interface_cti $0\libresocsim_interface0_converted_interface_cti[2:0]
+    sync init
   end
-  attribute \src "ls180.v:1518.1-1525.4"
-  process $proc$ls180.v:1518$24
+  attribute \src "ls180.v:1511.1-1518.4"
+  process $proc$ls180.v:1511$16
     assign { } { }
     assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000
     assign $0\libresocsim_libresoc_interrupt[15:0] [13] \eint_tmp [0]
@@ -262590,25 +262090,33 @@ module \ls180
     sync always
       update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0]
   end
-  attribute \src "ls180.v:1527.1-1537.4"
-  process $proc$ls180.v:1527$26
+  attribute \src "ls180.v:152.11-152.64"
+  process $proc$ls180.v:152$1584
     assign { } { }
-    assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
-    attribute \src "ls180.v:1529.2-1536.9"
-    switch \converter0_counter
+    assign $0\libresocsim_interface0_converted_interface_bte[1:0] 2'00
+    sync always
+      update \libresocsim_interface0_converted_interface_bte $0\libresocsim_interface0_converted_interface_bte[1:0]
+    sync init
+  end
+  attribute \src "ls180.v:1520.1-1530.4"
+  process $proc$ls180.v:1520$18
+    assign { } { }
+    assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] 0
+    attribute \src "ls180.v:1522.2-1529.9"
+    switch \libresocsim_converter0_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
-        assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] \interface0_converted_interface_dat_w [31:0]
+        assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [31:0]
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] \interface0_converted_interface_dat_w [63:32]
+        assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [63:32]
       case 
     end
     sync always
-      update \libresocsim_libresoc_xics_icp_dat_w $0\libresocsim_libresoc_xics_icp_dat_w[31:0]
+      update \libresocsim_interface0_converted_interface_dat_w $0\libresocsim_interface0_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:1539.1-1585.4"
-  process $proc$ls180.v:1539$27
+  attribute \src "ls180.v:1532.1-1578.4"
+  process $proc$ls180.v:1532$19
     assign { } { }
     assign { } { }
     assign { } { }
@@ -262619,51 +262127,51 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'0
+    assign $0\libresocsim_interface0_converted_interface_sel[3:0] 4'0000
+    assign $0\libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+    assign $0\libresocsim_interface0_converted_interface_stb[0:0] 1'0
+    assign $0\libresocsim_interface0_converted_interface_we[0:0] 1'0
+    assign $0\libresocsim_converter0_skip[0:0] 1'0
     assign { } { }
-    assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
-    assign $0\converter0_skip[0:0] 1'0
-    assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000
-    assign $0\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000
-    assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_icp_stb[0:0] 1'0
-    assign $0\interface0_converted_interface_ack[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_icp_we[0:0] 1'0
+    assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0
+    assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
+    assign $0\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
     assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state
-    attribute \src "ls180.v:1551.2-1584.9"
+    attribute \src "ls180.v:1544.2-1577.9"
     switch \subfragments_converter0_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\libresocsim_libresoc_xics_icp_adr[29:0] { \interface0_converted_interface_adr [28:0] \converter0_counter }
-        attribute \src "ls180.v:1554.4-1561.11"
-        switch \converter0_counter
+        assign $0\libresocsim_interface0_converted_interface_adr[29:0] { \libresocsim_libresoc_ibus_adr \libresocsim_converter0_counter }
+        attribute \src "ls180.v:1547.4-1554.11"
+        switch \libresocsim_converter0_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
-            assign $0\libresocsim_libresoc_xics_icp_sel[3:0] \interface0_converted_interface_sel [3:0]
+            assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'1
-            assign $0\libresocsim_libresoc_xics_icp_sel[3:0] \interface0_converted_interface_sel [7:4]
+            assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:1562.4-1575.7"
-        switch $and$ls180.v:1562$28_Y
-          attribute \src "ls180.v:1562.8-1562.81"
+        attribute \src "ls180.v:1555.4-1568.7"
+        switch $and$ls180.v:1555$20_Y
+          attribute \src "ls180.v:1555.8-1555.71"
           case 1'1
-            assign $0\converter0_skip[0:0] $eq$ls180.v:1563$29_Y
-            assign $0\libresocsim_libresoc_xics_icp_we[0:0] \interface0_converted_interface_we
-            assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:1565$30_Y
-            assign $0\libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:1566$31_Y
-            attribute \src "ls180.v:1567.5-1574.8"
-            switch $or$ls180.v:1567$32_Y
-              attribute \src "ls180.v:1567.9-1567.62"
+            assign $0\libresocsim_converter0_skip[0:0] $eq$ls180.v:1556$21_Y
+            assign $0\libresocsim_interface0_converted_interface_we[0:0] \libresocsim_libresoc_ibus_we
+            assign $0\libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:1558$22_Y
+            assign $0\libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:1559$23_Y
+            attribute \src "ls180.v:1560.5-1567.8"
+            switch $or$ls180.v:1560$24_Y
+              attribute \src "ls180.v:1560.9-1560.87"
               case 1'1
-                assign $0\converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1568$33_Y
-                assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:1570.6-1573.9"
-                switch $eq$ls180.v:1570$34_Y
-                  attribute \src "ls180.v:1570.10-1570.38"
+                assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1561$25_Y
+                assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
+                attribute \src "ls180.v:1563.6-1566.9"
+                switch $eq$ls180.v:1563$26_Y
+                  attribute \src "ls180.v:1563.10-1563.50"
                   case 1'1
-                    assign $0\interface0_converted_interface_ack[0:0] 1'1
+                    assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'1
                     assign $0\subfragments_converter0_next_state[0:0] 1'0
                   case 
                 end
@@ -262673,63 +262181,87 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
-        assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:1580.4-1582.7"
-        switch $and$ls180.v:1580$35_Y
-          attribute \src "ls180.v:1580.8-1580.81"
+        assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0
+        assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
+        attribute \src "ls180.v:1573.4-1575.7"
+        switch $and$ls180.v:1573$27_Y
+          attribute \src "ls180.v:1573.8-1573.71"
           case 1'1
             assign $0\subfragments_converter0_next_state[0:0] 1'1
           case 
         end
     end
     sync always
-      update \libresocsim_libresoc_xics_icp_adr $0\libresocsim_libresoc_xics_icp_adr[29:0]
-      update \libresocsim_libresoc_xics_icp_sel $0\libresocsim_libresoc_xics_icp_sel[3:0]
-      update \libresocsim_libresoc_xics_icp_cyc $0\libresocsim_libresoc_xics_icp_cyc[0:0]
-      update \libresocsim_libresoc_xics_icp_stb $0\libresocsim_libresoc_xics_icp_stb[0:0]
-      update \libresocsim_libresoc_xics_icp_we $0\libresocsim_libresoc_xics_icp_we[0:0]
-      update \interface0_converted_interface_ack $0\interface0_converted_interface_ack[0:0]
-      update \converter0_skip $0\converter0_skip[0:0]
+      update \libresocsim_libresoc_ibus_ack $0\libresocsim_libresoc_ibus_ack[0:0]
+      update \libresocsim_interface0_converted_interface_adr $0\libresocsim_interface0_converted_interface_adr[29:0]
+      update \libresocsim_interface0_converted_interface_sel $0\libresocsim_interface0_converted_interface_sel[3:0]
+      update \libresocsim_interface0_converted_interface_cyc $0\libresocsim_interface0_converted_interface_cyc[0:0]
+      update \libresocsim_interface0_converted_interface_stb $0\libresocsim_interface0_converted_interface_stb[0:0]
+      update \libresocsim_interface0_converted_interface_we $0\libresocsim_interface0_converted_interface_we[0:0]
+      update \libresocsim_converter0_skip $0\libresocsim_converter0_skip[0:0]
       update \subfragments_converter0_next_state $0\subfragments_converter0_next_state[0:0]
-      update \converter0_counter_subfragments_converter0_next_value $0\converter0_counter_subfragments_converter0_next_value[0:0]
-      update \converter0_counter_subfragments_converter0_next_value_ce $0\converter0_counter_subfragments_converter0_next_value_ce[0:0]
+      update \libresocsim_converter0_counter_subfragments_converter0_next_value $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0]
+      update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:155.5-155.35"
-  process $proc$ls180.v:155$1670
+  attribute \src "ls180.v:154.5-154.39"
+  process $proc$ls180.v:154$1585
     assign { } { }
-    assign $0\libresocsim_ram_bus_err[0:0] 1'0
+    assign $1\libresocsim_converter0_skip[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_converter0_skip $1\libresocsim_converter0_skip[0:0]
+  end
+  attribute \src "ls180.v:155.5-155.42"
+  process $proc$ls180.v:155$1586
+    assign { } { }
+    assign $1\libresocsim_converter0_counter[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_converter0_counter $1\libresocsim_converter0_counter[0:0]
+  end
+  attribute \src "ls180.v:157.12-157.48"
+  process $proc$ls180.v:157$1587
+    assign { } { }
+    assign $1\libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
-      update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0]
     sync init
+      update \libresocsim_converter0_dat_r $1\libresocsim_converter0_dat_r[63:0]
   end
-  attribute \src "ls180.v:158.11-158.32"
-  process $proc$ls180.v:158$1671
+  attribute \src "ls180.v:158.12-158.66"
+  process $proc$ls180.v:158$1588
     assign { } { }
-    assign $1\libresocsim_we[7:0] 8'00000000
+    assign $1\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
     sync init
-      update \libresocsim_we $1\libresocsim_we[7:0]
+      update \libresocsim_interface1_converted_interface_adr $1\libresocsim_interface1_converted_interface_adr[29:0]
   end
-  attribute \src "ls180.v:1587.1-1597.4"
-  process $proc$ls180.v:1587$37
+  attribute \src "ls180.v:1580.1-1590.4"
+  process $proc$ls180.v:1580$29
     assign { } { }
-    assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] 0
-    attribute \src "ls180.v:1589.2-1596.9"
-    switch \converter1_counter
+    assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] 0
+    attribute \src "ls180.v:1582.2-1589.9"
+    switch \libresocsim_converter1_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
-        assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] \interface1_converted_interface_dat_w [31:0]
+        assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [31:0]
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] \interface1_converted_interface_dat_w [63:32]
+        assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [63:32]
       case 
     end
     sync always
-      update \libresocsim_libresoc_xics_ics_dat_w $0\libresocsim_libresoc_xics_ics_dat_w[31:0]
+      update \libresocsim_interface1_converted_interface_dat_w $0\libresocsim_interface1_converted_interface_dat_w[31:0]
+  end
+  attribute \src "ls180.v:159.12-159.68"
+  process $proc$ls180.v:159$1589
+    assign { } { }
+    assign $1\libresocsim_interface1_converted_interface_dat_w[31:0] 0
+    sync always
+    sync init
+      update \libresocsim_interface1_converted_interface_dat_w $1\libresocsim_interface1_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:1599.1-1645.4"
-  process $proc$ls180.v:1599$38
+  attribute \src "ls180.v:1592.1-1638.4"
+  process $proc$ls180.v:1592$30
     assign { } { }
     assign { } { }
     assign { } { }
@@ -262740,51 +262272,51 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000
-    assign $0\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000
-    assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_ics_stb[0:0] 1'0
-    assign $0\interface1_converted_interface_ack[0:0] 1'0
-    assign $0\libresocsim_libresoc_xics_ics_we[0:0] 1'0
-    assign $0\converter1_skip[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_stb[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_we[0:0] 1'0
+    assign $0\libresocsim_converter1_skip[0:0] 1'0
+    assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'0
     assign { } { }
-    assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+    assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0
+    assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_sel[3:0] 4'0000
+    assign $0\libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state
-    attribute \src "ls180.v:1611.2-1644.9"
+    attribute \src "ls180.v:1604.2-1637.9"
     switch \subfragments_converter1_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\libresocsim_libresoc_xics_ics_adr[29:0] { \interface1_converted_interface_adr [28:0] \converter1_counter }
-        attribute \src "ls180.v:1614.4-1621.11"
-        switch \converter1_counter
+        assign $0\libresocsim_interface1_converted_interface_adr[29:0] { \libresocsim_libresoc_dbus_adr \libresocsim_converter1_counter }
+        attribute \src "ls180.v:1607.4-1614.11"
+        switch \libresocsim_converter1_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
-            assign $0\libresocsim_libresoc_xics_ics_sel[3:0] \interface1_converted_interface_sel [3:0]
+            assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'1
-            assign $0\libresocsim_libresoc_xics_ics_sel[3:0] \interface1_converted_interface_sel [7:4]
+            assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:1622.4-1635.7"
-        switch $and$ls180.v:1622$39_Y
-          attribute \src "ls180.v:1622.8-1622.81"
+        attribute \src "ls180.v:1615.4-1628.7"
+        switch $and$ls180.v:1615$31_Y
+          attribute \src "ls180.v:1615.8-1615.71"
           case 1'1
-            assign $0\converter1_skip[0:0] $eq$ls180.v:1623$40_Y
-            assign $0\libresocsim_libresoc_xics_ics_we[0:0] \interface1_converted_interface_we
-            assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:1625$41_Y
-            assign $0\libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:1626$42_Y
-            attribute \src "ls180.v:1627.5-1634.8"
-            switch $or$ls180.v:1627$43_Y
-              attribute \src "ls180.v:1627.9-1627.62"
+            assign $0\libresocsim_converter1_skip[0:0] $eq$ls180.v:1616$32_Y
+            assign $0\libresocsim_interface1_converted_interface_we[0:0] \libresocsim_libresoc_dbus_we
+            assign $0\libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:1618$33_Y
+            assign $0\libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:1619$34_Y
+            attribute \src "ls180.v:1620.5-1627.8"
+            switch $or$ls180.v:1620$35_Y
+              attribute \src "ls180.v:1620.9-1620.87"
               case 1'1
-                assign $0\converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1628$44_Y
-                assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:1630.6-1633.9"
-                switch $eq$ls180.v:1630$45_Y
-                  attribute \src "ls180.v:1630.10-1630.38"
+                assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1621$36_Y
+                assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
+                attribute \src "ls180.v:1623.6-1626.9"
+                switch $eq$ls180.v:1623$37_Y
+                  attribute \src "ls180.v:1623.10-1623.50"
                   case 1'1
-                    assign $0\interface1_converted_interface_ack[0:0] 1'1
+                    assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'1
                     assign $0\subfragments_converter1_next_state[0:0] 1'0
                   case 
                 end
@@ -262794,95 +262326,79 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
-        assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:1640.4-1642.7"
-        switch $and$ls180.v:1640$46_Y
-          attribute \src "ls180.v:1640.8-1640.81"
+        assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0
+        assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
+        attribute \src "ls180.v:1633.4-1635.7"
+        switch $and$ls180.v:1633$38_Y
+          attribute \src "ls180.v:1633.8-1633.71"
           case 1'1
             assign $0\subfragments_converter1_next_state[0:0] 1'1
           case 
         end
     end
     sync always
-      update \libresocsim_libresoc_xics_ics_adr $0\libresocsim_libresoc_xics_ics_adr[29:0]
-      update \libresocsim_libresoc_xics_ics_sel $0\libresocsim_libresoc_xics_ics_sel[3:0]
-      update \libresocsim_libresoc_xics_ics_cyc $0\libresocsim_libresoc_xics_ics_cyc[0:0]
-      update \libresocsim_libresoc_xics_ics_stb $0\libresocsim_libresoc_xics_ics_stb[0:0]
-      update \libresocsim_libresoc_xics_ics_we $0\libresocsim_libresoc_xics_ics_we[0:0]
-      update \interface1_converted_interface_ack $0\interface1_converted_interface_ack[0:0]
-      update \converter1_skip $0\converter1_skip[0:0]
+      update \libresocsim_libresoc_dbus_ack $0\libresocsim_libresoc_dbus_ack[0:0]
+      update \libresocsim_interface1_converted_interface_adr $0\libresocsim_interface1_converted_interface_adr[29:0]
+      update \libresocsim_interface1_converted_interface_sel $0\libresocsim_interface1_converted_interface_sel[3:0]
+      update \libresocsim_interface1_converted_interface_cyc $0\libresocsim_interface1_converted_interface_cyc[0:0]
+      update \libresocsim_interface1_converted_interface_stb $0\libresocsim_interface1_converted_interface_stb[0:0]
+      update \libresocsim_interface1_converted_interface_we $0\libresocsim_interface1_converted_interface_we[0:0]
+      update \libresocsim_converter1_skip $0\libresocsim_converter1_skip[0:0]
       update \subfragments_converter1_next_state $0\subfragments_converter1_next_state[0:0]
-      update \converter1_counter_subfragments_converter1_next_value $0\converter1_counter_subfragments_converter1_next_value[0:0]
-      update \converter1_counter_subfragments_converter1_next_value_ce $0\converter1_counter_subfragments_converter1_next_value_ce[0:0]
-  end
-  attribute \src "ls180.v:160.12-160.44"
-  process $proc$ls180.v:160$1672
-    assign { } { }
-    assign $1\libresocsim_load_storage[31:0] 0
-    sync always
-    sync init
-      update \libresocsim_load_storage $1\libresocsim_load_storage[31:0]
-  end
-  attribute \src "ls180.v:161.5-161.31"
-  process $proc$ls180.v:161$1673
-    assign { } { }
-    assign $1\libresocsim_load_re[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_load_re $1\libresocsim_load_re[0:0]
+      update \libresocsim_converter1_counter_subfragments_converter1_next_value $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0]
+      update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:162.12-162.46"
-  process $proc$ls180.v:162$1674
+  attribute \src "ls180.v:161.11-161.64"
+  process $proc$ls180.v:161$1590
     assign { } { }
-    assign $1\libresocsim_reload_storage[31:0] 0
+    assign $1\libresocsim_interface1_converted_interface_sel[3:0] 4'0000
     sync always
     sync init
-      update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0]
+      update \libresocsim_interface1_converted_interface_sel $1\libresocsim_interface1_converted_interface_sel[3:0]
   end
-  attribute \src "ls180.v:163.5-163.33"
-  process $proc$ls180.v:163$1675
+  attribute \src "ls180.v:162.5-162.58"
+  process $proc$ls180.v:162$1591
     assign { } { }
-    assign $1\libresocsim_reload_re[0:0] 1'0
+    assign $1\libresocsim_interface1_converted_interface_cyc[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_reload_re $1\libresocsim_reload_re[0:0]
+      update \libresocsim_interface1_converted_interface_cyc $1\libresocsim_interface1_converted_interface_cyc[0:0]
   end
-  attribute \src "ls180.v:164.5-164.34"
-  process $proc$ls180.v:164$1676
+  attribute \src "ls180.v:163.5-163.58"
+  process $proc$ls180.v:163$1592
     assign { } { }
-    assign $1\libresocsim_en_storage[0:0] 1'0
+    assign $1\libresocsim_interface1_converted_interface_stb[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_en_storage $1\libresocsim_en_storage[0:0]
+      update \libresocsim_interface1_converted_interface_stb $1\libresocsim_interface1_converted_interface_stb[0:0]
   end
-  attribute \src "ls180.v:1647.1-1657.4"
-  process $proc$ls180.v:1647$48
+  attribute \src "ls180.v:1640.1-1650.4"
+  process $proc$ls180.v:1640$40
     assign { } { }
-    assign $0\wb_sdram_dat_w[31:0] 0
-    attribute \src "ls180.v:1649.2-1656.9"
-    switch \socbushandler_counter
+    assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] 0
+    attribute \src "ls180.v:1642.2-1649.9"
+    switch \libresocsim_converter2_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
-        assign $0\wb_sdram_dat_w[31:0] \socbushandler_converted_interface_dat_w [31:0]
+        assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [31:0]
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\wb_sdram_dat_w[31:0] \socbushandler_converted_interface_dat_w [63:32]
+        assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [63:32]
       case 
     end
     sync always
-      update \wb_sdram_dat_w $0\wb_sdram_dat_w[31:0]
+      update \libresocsim_interface2_converted_interface_dat_w $0\libresocsim_interface2_converted_interface_dat_w[31:0]
   end
-  attribute \src "ls180.v:165.5-165.29"
-  process $proc$ls180.v:165$1677
+  attribute \src "ls180.v:165.5-165.57"
+  process $proc$ls180.v:165$1593
     assign { } { }
-    assign $1\libresocsim_en_re[0:0] 1'0
+    assign $1\libresocsim_interface1_converted_interface_we[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_en_re $1\libresocsim_en_re[0:0]
+      update \libresocsim_interface1_converted_interface_we $1\libresocsim_interface1_converted_interface_we[0:0]
   end
-  attribute \src "ls180.v:1659.1-1705.4"
-  process $proc$ls180.v:1659$49
+  attribute \src "ls180.v:1652.1-1698.4"
+  process $proc$ls180.v:1652$41
     assign { } { }
     assign { } { }
     assign { } { }
@@ -262893,51 +262409,51 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\wb_sdram_sel[3:0] 4'0000
-    assign $0\wb_sdram_cyc[0:0] 1'0
-    assign $0\wb_sdram_stb[0:0] 1'0
-    assign $0\socbushandler_skip[0:0] 1'0
-    assign $0\wb_sdram_we[0:0] 1'0
+    assign $0\libresocsim_converter2_skip[0:0] 1'0
+    assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
+    assign $0\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
     assign { } { }
-    assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
-    assign $0\wb_sdram_adr[29:0] 30'000000000000000000000000000000
-    assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0
-    assign $0\socbushandler_converted_interface_ack[0:0] 1'0
+    assign $0\libresocsim_interface2_converted_interface_sel[3:0] 4'0000
+    assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0
+    assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0
+    assign $0\libresocsim_interface2_converted_interface_cyc[0:0] 1'0
+    assign $0\libresocsim_interface2_converted_interface_stb[0:0] 1'0
+    assign $0\libresocsim_interface2_converted_interface_we[0:0] 1'0
     assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state
-    attribute \src "ls180.v:1671.2-1704.9"
+    attribute \src "ls180.v:1664.2-1697.9"
     switch \subfragments_converter2_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
-        assign $0\wb_sdram_adr[29:0] { \socbushandler_converted_interface_adr [28:0] \socbushandler_counter }
-        attribute \src "ls180.v:1674.4-1681.11"
-        switch \socbushandler_counter
+        assign $0\libresocsim_interface2_converted_interface_adr[29:0] { \libresocsim_libresoc_jtag_wb_adr \libresocsim_converter2_counter }
+        attribute \src "ls180.v:1667.4-1674.11"
+        switch \libresocsim_converter2_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
-            assign $0\wb_sdram_sel[3:0] \socbushandler_converted_interface_sel [3:0]
+            assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'1
-            assign $0\wb_sdram_sel[3:0] \socbushandler_converted_interface_sel [7:4]
+            assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [7:4]
           case 
         end
-        attribute \src "ls180.v:1682.4-1695.7"
-        switch $and$ls180.v:1682$50_Y
-          attribute \src "ls180.v:1682.8-1682.87"
+        attribute \src "ls180.v:1675.4-1688.7"
+        switch $and$ls180.v:1675$42_Y
+          attribute \src "ls180.v:1675.8-1675.77"
           case 1'1
-            assign $0\socbushandler_skip[0:0] $eq$ls180.v:1683$51_Y
-            assign $0\wb_sdram_we[0:0] \socbushandler_converted_interface_we
-            assign $0\wb_sdram_cyc[0:0] $not$ls180.v:1685$52_Y
-            assign $0\wb_sdram_stb[0:0] $not$ls180.v:1686$53_Y
-            attribute \src "ls180.v:1687.5-1694.8"
-            switch $or$ls180.v:1687$54_Y
-              attribute \src "ls180.v:1687.9-1687.44"
+            assign $0\libresocsim_converter2_skip[0:0] $eq$ls180.v:1676$43_Y
+            assign $0\libresocsim_interface2_converted_interface_we[0:0] \libresocsim_libresoc_jtag_wb_we
+            assign $0\libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:1678$44_Y
+            assign $0\libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:1679$45_Y
+            attribute \src "ls180.v:1680.5-1687.8"
+            switch $or$ls180.v:1680$46_Y
+              attribute \src "ls180.v:1680.9-1680.87"
               case 1'1
-                assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1688$55_Y
-                assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:1690.6-1693.9"
-                switch $eq$ls180.v:1690$56_Y
-                  attribute \src "ls180.v:1690.10-1690.41"
+                assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1681$47_Y
+                assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1
+                attribute \src "ls180.v:1683.6-1686.9"
+                switch $eq$ls180.v:1683$48_Y
+                  attribute \src "ls180.v:1683.10-1683.50"
                   case 1'1
-                    assign $0\socbushandler_converted_interface_ack[0:0] 1'1
+                    assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'1
                     assign $0\subfragments_converter2_next_state[0:0] 1'0
                   case 
                 end
@@ -262947,82 +262463,78 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
-        assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:1700.4-1702.7"
-        switch $and$ls180.v:1700$57_Y
-          attribute \src "ls180.v:1700.8-1700.87"
+        assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0
+        assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1
+        attribute \src "ls180.v:1693.4-1695.7"
+        switch $and$ls180.v:1693$49_Y
+          attribute \src "ls180.v:1693.8-1693.77"
           case 1'1
             assign $0\subfragments_converter2_next_state[0:0] 1'1
           case 
         end
     end
     sync always
-      update \wb_sdram_adr $0\wb_sdram_adr[29:0]
-      update \wb_sdram_sel $0\wb_sdram_sel[3:0]
-      update \wb_sdram_cyc $0\wb_sdram_cyc[0:0]
-      update \wb_sdram_stb $0\wb_sdram_stb[0:0]
-      update \wb_sdram_we $0\wb_sdram_we[0:0]
-      update \socbushandler_converted_interface_ack $0\socbushandler_converted_interface_ack[0:0]
-      update \socbushandler_skip $0\socbushandler_skip[0:0]
+      update \libresocsim_libresoc_jtag_wb_ack $0\libresocsim_libresoc_jtag_wb_ack[0:0]
+      update \libresocsim_interface2_converted_interface_adr $0\libresocsim_interface2_converted_interface_adr[29:0]
+      update \libresocsim_interface2_converted_interface_sel $0\libresocsim_interface2_converted_interface_sel[3:0]
+      update \libresocsim_interface2_converted_interface_cyc $0\libresocsim_interface2_converted_interface_cyc[0:0]
+      update \libresocsim_interface2_converted_interface_stb $0\libresocsim_interface2_converted_interface_stb[0:0]
+      update \libresocsim_interface2_converted_interface_we $0\libresocsim_interface2_converted_interface_we[0:0]
+      update \libresocsim_converter2_skip $0\libresocsim_converter2_skip[0:0]
       update \subfragments_converter2_next_state $0\subfragments_converter2_next_state[0:0]
-      update \socbushandler_counter_subfragments_converter2_next_value $0\socbushandler_counter_subfragments_converter2_next_value[0:0]
-      update \socbushandler_counter_subfragments_converter2_next_value_ce $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
+      update \libresocsim_converter2_counter_subfragments_converter2_next_value $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0]
+      update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:166.5-166.44"
-  process $proc$ls180.v:166$1678
+  attribute \src "ls180.v:166.11-166.64"
+  process $proc$ls180.v:166$1594
     assign { } { }
-    assign $1\libresocsim_update_value_storage[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_cti[2:0] 3'000
     sync always
+      update \libresocsim_interface1_converted_interface_cti $0\libresocsim_interface1_converted_interface_cti[2:0]
     sync init
-      update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0]
   end
-  attribute \src "ls180.v:167.5-167.39"
-  process $proc$ls180.v:167$1679
+  attribute \src "ls180.v:167.11-167.64"
+  process $proc$ls180.v:167$1595
     assign { } { }
-    assign $1\libresocsim_update_value_re[0:0] 1'0
+    assign $0\libresocsim_interface1_converted_interface_bte[1:0] 2'00
     sync always
+      update \libresocsim_interface1_converted_interface_bte $0\libresocsim_interface1_converted_interface_bte[1:0]
     sync init
-      update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0]
   end
-  attribute \src "ls180.v:168.12-168.44"
-  process $proc$ls180.v:168$1680
+  attribute \src "ls180.v:169.5-169.39"
+  process $proc$ls180.v:169$1596
     assign { } { }
-    assign $1\libresocsim_value_status[31:0] 0
+    assign $1\libresocsim_converter1_skip[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_value_status $1\libresocsim_value_status[31:0]
+      update \libresocsim_converter1_skip $1\libresocsim_converter1_skip[0:0]
   end
-  attribute \src "ls180.v:1708.1-1718.4"
-  process $proc$ls180.v:1708$58
-    assign { } { }
+  attribute \src "ls180.v:170.5-170.42"
+  process $proc$ls180.v:170$1597
     assign { } { }
-    assign $0\libresocsim_we[7:0] [0] $and$ls180.v:1710$61_Y
-    assign $0\libresocsim_we[7:0] [1] $and$ls180.v:1711$64_Y
-    assign $0\libresocsim_we[7:0] [2] $and$ls180.v:1712$67_Y
-    assign $0\libresocsim_we[7:0] [3] $and$ls180.v:1713$70_Y
-    assign $0\libresocsim_we[7:0] [4] $and$ls180.v:1714$73_Y
-    assign $0\libresocsim_we[7:0] [5] $and$ls180.v:1715$76_Y
-    assign $0\libresocsim_we[7:0] [6] $and$ls180.v:1716$79_Y
-    assign $0\libresocsim_we[7:0] [7] $and$ls180.v:1717$82_Y
+    assign $1\libresocsim_converter1_counter[0:0] 1'0
     sync always
-      update \libresocsim_we $0\libresocsim_we[7:0]
+    sync init
+      update \libresocsim_converter1_counter $1\libresocsim_converter1_counter[0:0]
   end
-  attribute \src "ls180.v:172.5-172.36"
-  process $proc$ls180.v:172$1681
+  attribute \src "ls180.v:1701.1-1707.4"
+  process $proc$ls180.v:1701$50
     assign { } { }
-    assign $1\libresocsim_zero_pending[0:0] 1'0
+    assign { } { }
+    assign $0\libresocsim_we[3:0] [0] $and$ls180.v:1703$53_Y
+    assign $0\libresocsim_we[3:0] [1] $and$ls180.v:1704$56_Y
+    assign $0\libresocsim_we[3:0] [2] $and$ls180.v:1705$59_Y
+    assign $0\libresocsim_we[3:0] [3] $and$ls180.v:1706$62_Y
     sync always
-    sync init
-      update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0]
+      update \libresocsim_we $0\libresocsim_we[3:0]
   end
-  attribute \src "ls180.v:1724.1-1729.4"
-  process $proc$ls180.v:1724$84
+  attribute \src "ls180.v:1713.1-1718.4"
+  process $proc$ls180.v:1713$64
     assign { } { }
     assign $0\libresocsim_zero_clear[0:0] 1'0
-    attribute \src "ls180.v:1726.2-1728.5"
-    switch $and$ls180.v:1726$85_Y
-      attribute \src "ls180.v:1726.6-1726.80"
+    attribute \src "ls180.v:1715.2-1717.5"
+    switch $and$ls180.v:1715$65_Y
+      attribute \src "ls180.v:1715.6-1715.80"
       case 1'1
         assign $0\libresocsim_zero_clear[0:0] 1'1
       case 
@@ -263030,39 +262542,51 @@ module \ls180
     sync always
       update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0]
   end
-  attribute \src "ls180.v:1733.1-1743.4"
-  process $proc$ls180.v:1733$87
+  attribute \src "ls180.v:172.12-172.48"
+  process $proc$ls180.v:172$1598
+    assign { } { }
+    assign $1\libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync always
+    sync init
+      update \libresocsim_converter1_dat_r $1\libresocsim_converter1_dat_r[63:0]
+  end
+  attribute \src "ls180.v:1722.1-1728.4"
+  process $proc$ls180.v:1722$67
     assign { } { }
     assign { } { }
-    assign $0\ram_we[7:0] [0] $and$ls180.v:1735$90_Y
-    assign $0\ram_we[7:0] [1] $and$ls180.v:1736$93_Y
-    assign $0\ram_we[7:0] [2] $and$ls180.v:1737$96_Y
-    assign $0\ram_we[7:0] [3] $and$ls180.v:1738$99_Y
-    assign $0\ram_we[7:0] [4] $and$ls180.v:1739$102_Y
-    assign $0\ram_we[7:0] [5] $and$ls180.v:1740$105_Y
-    assign $0\ram_we[7:0] [6] $and$ls180.v:1741$108_Y
-    assign $0\ram_we[7:0] [7] $and$ls180.v:1742$111_Y
+    assign $0\ram_we[3:0] [0] $and$ls180.v:1724$70_Y
+    assign $0\ram_we[3:0] [1] $and$ls180.v:1725$73_Y
+    assign $0\ram_we[3:0] [2] $and$ls180.v:1726$76_Y
+    assign $0\ram_we[3:0] [3] $and$ls180.v:1727$79_Y
     sync always
-      update \ram_we $0\ram_we[7:0]
+      update \ram_we $0\ram_we[3:0]
   end
-  attribute \src "ls180.v:174.5-174.34"
-  process $proc$ls180.v:174$1682
+  attribute \src "ls180.v:173.12-173.66"
+  process $proc$ls180.v:173$1599
     assign { } { }
-    assign $1\libresocsim_zero_clear[0:0] 1'0
+    assign $1\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
     sync always
     sync init
-      update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0]
+      update \libresocsim_interface2_converted_interface_adr $1\libresocsim_interface2_converted_interface_adr[29:0]
   end
-  attribute \src "ls180.v:175.5-175.40"
-  process $proc$ls180.v:175$1683
+  attribute \src "ls180.v:174.12-174.68"
+  process $proc$ls180.v:174$1600
     assign { } { }
-    assign $1\libresocsim_zero_old_trigger[0:0] 1'0
+    assign $1\libresocsim_interface2_converted_interface_dat_w[31:0] 0
     sync always
     sync init
-      update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0]
+      update \libresocsim_interface2_converted_interface_dat_w $1\libresocsim_interface2_converted_interface_dat_w[31:0]
+  end
+  attribute \src "ls180.v:176.11-176.64"
+  process $proc$ls180.v:176$1601
+    assign { } { }
+    assign $1\libresocsim_interface2_converted_interface_sel[3:0] 4'0000
+    sync always
+    sync init
+      update \libresocsim_interface2_converted_interface_sel $1\libresocsim_interface2_converted_interface_sel[3:0]
   end
-  attribute \src "ls180.v:1782.1-1836.4"
-  process $proc$ls180.v:1782$112
+  attribute \src "ls180.v:1767.1-1821.4"
+  process $proc$ls180.v:1767$80
     assign { } { }
     assign { } { }
     assign { } { }
@@ -263092,16 +262616,16 @@ module \ls180
     assign $0\sdram_master_p0_cke[0:0] 1'0
     assign $0\sdram_master_p0_odt[0:0] 1'0
     assign $0\sdram_master_p0_reset_n[0:0] 1'0
-    assign $0\sdram_inti_p0_rddata[15:0] 16'0000000000000000
     assign $0\sdram_master_p0_act_n[0:0] 1'1
-    assign $0\sdram_inti_p0_rddata_valid[0:0] 1'0
+    assign $0\sdram_inti_p0_rddata[15:0] 16'0000000000000000
     assign $0\sdram_master_p0_wrdata[15:0] 16'0000000000000000
+    assign $0\sdram_inti_p0_rddata_valid[0:0] 1'0
     assign $0\sdram_master_p0_wrdata_en[0:0] 1'0
     assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00
     assign $0\sdram_master_p0_rddata_en[0:0] 1'0
-    attribute \src "ls180.v:1801.2-1835.5"
+    attribute \src "ls180.v:1786.2-1820.5"
     switch \sdram_sel
-      attribute \src "ls180.v:1801.6-1801.15"
+      attribute \src "ls180.v:1786.6-1786.15"
       case 1'1
         assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address
         assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank
@@ -263119,7 +262643,7 @@ module \ls180
         assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en
         assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata
         assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid
-      attribute \src "ls180.v:1818.6-1818.10"
+      attribute \src "ls180.v:1803.6-1803.10"
       case 
         assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address
         assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank
@@ -263158,16 +262682,48 @@ module \ls180
       update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0]
       update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0]
   end
-  attribute \src "ls180.v:184.5-184.44"
-  process $proc$ls180.v:184$1684
+  attribute \src "ls180.v:177.5-177.58"
+  process $proc$ls180.v:177$1602
     assign { } { }
-    assign $1\libresocsim_eventmanager_storage[0:0] 1'0
+    assign $1\libresocsim_interface2_converted_interface_cyc[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0]
+      update \libresocsim_interface2_converted_interface_cyc $1\libresocsim_interface2_converted_interface_cyc[0:0]
+  end
+  attribute \src "ls180.v:178.5-178.58"
+  process $proc$ls180.v:178$1603
+    assign { } { }
+    assign $1\libresocsim_interface2_converted_interface_stb[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_interface2_converted_interface_stb $1\libresocsim_interface2_converted_interface_stb[0:0]
+  end
+  attribute \src "ls180.v:180.5-180.57"
+  process $proc$ls180.v:180$1604
+    assign { } { }
+    assign $1\libresocsim_interface2_converted_interface_we[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_interface2_converted_interface_we $1\libresocsim_interface2_converted_interface_we[0:0]
+  end
+  attribute \src "ls180.v:181.11-181.64"
+  process $proc$ls180.v:181$1605
+    assign { } { }
+    assign $0\libresocsim_interface2_converted_interface_cti[2:0] 3'000
+    sync always
+      update \libresocsim_interface2_converted_interface_cti $0\libresocsim_interface2_converted_interface_cti[2:0]
+    sync init
+  end
+  attribute \src "ls180.v:182.11-182.64"
+  process $proc$ls180.v:182$1606
+    assign { } { }
+    assign $0\libresocsim_interface2_converted_interface_bte[1:0] 2'00
+    sync always
+      update \libresocsim_interface2_converted_interface_bte $0\libresocsim_interface2_converted_interface_bte[1:0]
+    sync init
   end
-  attribute \src "ls180.v:1840.1-1856.4"
-  process $proc$ls180.v:1840$113
+  attribute \src "ls180.v:1825.1-1841.4"
+  process $proc$ls180.v:1825$81
     assign { } { }
     assign { } { }
     assign { } { }
@@ -263176,15 +262732,15 @@ module \ls180
     assign $0\sdram_inti_p0_we_n[0:0] 1'1
     assign $0\sdram_inti_p0_cas_n[0:0] 1'1
     assign $0\sdram_inti_p0_cs_n[0:0] 1'1
-    attribute \src "ls180.v:1845.2-1855.5"
+    attribute \src "ls180.v:1830.2-1840.5"
     switch \sdram_command_issue_re
-      attribute \src "ls180.v:1845.6-1845.28"
+      attribute \src "ls180.v:1830.6-1830.28"
       case 1'1
-        assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1846$114_Y
-        assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1847$115_Y
-        assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1848$116_Y
-        assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1849$117_Y
-      attribute \src "ls180.v:1850.6-1850.10"
+        assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1831$82_Y
+        assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1832$83_Y
+        assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1833$84_Y
+        assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1834$85_Y
+      attribute \src "ls180.v:1835.6-1835.10"
       case 
         assign $0\sdram_inti_p0_cs_n[0:0] 1'1
         assign $0\sdram_inti_p0_we_n[0:0] 1'1
@@ -263197,41 +262753,49 @@ module \ls180
       update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0]
       update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0]
   end
-  attribute \src "ls180.v:185.5-185.39"
-  process $proc$ls180.v:185$1685
+  attribute \src "ls180.v:184.5-184.39"
+  process $proc$ls180.v:184$1607
     assign { } { }
-    assign $1\libresocsim_eventmanager_re[0:0] 1'0
+    assign $1\libresocsim_converter2_skip[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0]
+      update \libresocsim_converter2_skip $1\libresocsim_converter2_skip[0:0]
   end
-  attribute \src "ls180.v:186.12-186.37"
-  process $proc$ls180.v:186$1686
+  attribute \src "ls180.v:185.5-185.42"
+  process $proc$ls180.v:185$1608
     assign { } { }
-    assign $1\libresocsim_value[31:0] 0
+    assign $1\libresocsim_converter2_counter[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_value $1\libresocsim_value[31:0]
+      update \libresocsim_converter2_counter $1\libresocsim_converter2_counter[0:0]
+  end
+  attribute \src "ls180.v:187.12-187.48"
+  process $proc$ls180.v:187$1609
+    assign { } { }
+    assign $1\libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync always
+    sync init
+      update \libresocsim_converter2_dat_r $1\libresocsim_converter2_dat_r[63:0]
   end
-  attribute \src "ls180.v:1899.1-1929.4"
-  process $proc$ls180.v:1899$126
+  attribute \src "ls180.v:1884.1-1914.4"
+  process $proc$ls180.v:1884$94
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\sdram_cmd_last[0:0] 1'0
     assign $0\sdram_sequencer_start0[0:0] 1'0
-    assign $0\sdram_cmd_valid[0:0] 1'0
     assign { } { }
+    assign $0\sdram_cmd_valid[0:0] 1'0
     assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state
-    attribute \src "ls180.v:1905.2-1928.9"
+    attribute \src "ls180.v:1890.2-1913.9"
     switch \subfragments_refresher_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
         assign $0\sdram_cmd_valid[0:0] 1'1
-        attribute \src "ls180.v:1908.4-1911.7"
+        attribute \src "ls180.v:1893.4-1896.7"
         switch \sdram_cmd_ready
-          attribute \src "ls180.v:1908.8-1908.23"
+          attribute \src "ls180.v:1893.8-1893.23"
           case 1'1
             assign $0\sdram_sequencer_start0[0:0] 1'1
             assign $0\subfragments_refresher_next_state[1:0] 2'10
@@ -263240,9 +262804,9 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
         assign $0\sdram_cmd_valid[0:0] 1'1
-        attribute \src "ls180.v:1915.4-1919.7"
+        attribute \src "ls180.v:1900.4-1904.7"
         switch \sdram_sequencer_done0
-          attribute \src "ls180.v:1915.8-1915.29"
+          attribute \src "ls180.v:1900.8-1900.29"
           case 1'1
             assign $0\sdram_cmd_valid[0:0] 1'0
             assign $0\sdram_cmd_last[0:0] 1'1
@@ -263251,13 +262815,13 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:1922.4-1926.7"
+        attribute \src "ls180.v:1907.4-1911.7"
         switch 1'1
-          attribute \src "ls180.v:1922.8-1922.12"
+          attribute \src "ls180.v:1907.8-1907.12"
           case 1'1
-            attribute \src "ls180.v:1923.5-1925.8"
+            attribute \src "ls180.v:1908.5-1910.8"
             switch \sdram_wants_refresh
-              attribute \src "ls180.v:1923.9-1923.28"
+              attribute \src "ls180.v:1908.9-1908.28"
               case 1'1
                 assign $0\subfragments_refresher_next_state[1:0] 2'01
               case 
@@ -263271,43 +262835,43 @@ module \ls180
       update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0]
       update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0]
   end
-  attribute \src "ls180.v:193.5-193.31"
-  process $proc$ls180.v:193$1687
-    assign { } { }
-    assign $1\ram_bus_ram_bus_ack[0:0] 1'0
-    sync always
-    sync init
-      update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0]
-  end
-  attribute \src "ls180.v:1944.1-1951.4"
-  process $proc$ls180.v:1944$130
+  attribute \src "ls180.v:1929.1-1936.4"
+  process $proc$ls180.v:1929$98
     assign { } { }
     assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:1946.2-1950.5"
+    attribute \src "ls180.v:1931.2-1935.5"
     switch \sdram_bankmachine0_row_col_n_addr_sel
-      attribute \src "ls180.v:1946.6-1946.43"
+      attribute \src "ls180.v:1931.6-1931.43"
       case 1'1
         assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:1948.6-1948.10"
+      attribute \src "ls180.v:1933.6-1933.10"
       case 
-        assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1949$132_Y
+        assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1934$100_Y
     end
     sync always
       update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:1955.1-1962.4"
-  process $proc$ls180.v:1955$139
+  attribute \src "ls180.v:194.5-194.35"
+  process $proc$ls180.v:194$1610
+    assign { } { }
+    assign $1\libresocsim_ram_bus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0]
+  end
+  attribute \src "ls180.v:1940.1-1947.4"
+  process $proc$ls180.v:1940$107
     assign { } { }
     assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:1957.2-1961.5"
-    switch $and$ls180.v:1957$140_Y
-      attribute \src "ls180.v:1957.6-1957.105"
+    attribute \src "ls180.v:1942.2-1946.5"
+    switch $and$ls180.v:1942$108_Y
+      attribute \src "ls180.v:1942.6-1942.105"
       case 1'1
-        attribute \src "ls180.v:1958.3-1960.6"
-        switch $ne$ls180.v:1958$141_Y
-          attribute \src "ls180.v:1958.7-1958.133"
+        attribute \src "ls180.v:1943.3-1945.6"
+        switch $ne$ls180.v:1943$109_Y
+          attribute \src "ls180.v:1943.7-1943.133"
           case 1'1
-            assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1959$142_Y
+            assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1944$110_Y
           case 
         end
       case 
@@ -263315,32 +262879,24 @@ module \ls180
     sync always
       update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:197.5-197.31"
-  process $proc$ls180.v:197$1688
-    assign { } { }
-    assign $0\ram_bus_ram_bus_err[0:0] 1'0
-    sync always
-      update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:1977.1-1984.4"
-  process $proc$ls180.v:1977$143
+  attribute \src "ls180.v:1962.1-1969.4"
+  process $proc$ls180.v:1962$111
     assign { } { }
     assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:1979.2-1983.5"
+    attribute \src "ls180.v:1964.2-1968.5"
     switch \sdram_bankmachine0_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:1979.6-1979.53"
+      attribute \src "ls180.v:1964.6-1964.53"
       case 1'1
-        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1980$144_Y
-      attribute \src "ls180.v:1981.6-1981.10"
+        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1965$112_Y
+      attribute \src "ls180.v:1966.6-1966.10"
       case 
         assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce
     end
     sync always
       update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:1993.1-2086.4"
-  process $proc$ls180.v:1993$152
+  attribute \src "ls180.v:1978.1-2071.4"
+  process $proc$ls180.v:1978$120
     assign { } { }
     assign { } { }
     assign { } { }
@@ -263355,37 +262911,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
-    assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0
-    assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0
-    assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     assign { } { }
-    assign $0\sdram_bankmachine0_row_open[0:0] 1'0
-    assign $0\sdram_bankmachine0_row_close[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+    assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
     assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
     assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+    assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+    assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0
+    assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0
+    assign $0\sdram_bankmachine0_row_open[0:0] 1'0
+    assign $0\sdram_bankmachine0_row_close[0:0] 1'0
     assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state
-    attribute \src "ls180.v:2009.2-2085.9"
+    attribute \src "ls180.v:1994.2-2070.9"
     switch \subfragments_bankmachine0_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\sdram_bankmachine0_row_close[0:0] 1'1
-        attribute \src "ls180.v:2011.4-2019.7"
-        switch $and$ls180.v:2011$153_Y
-          attribute \src "ls180.v:2011.8-2011.77"
+        attribute \src "ls180.v:1996.4-2004.7"
+        switch $and$ls180.v:1996$121_Y
+          attribute \src "ls180.v:1996.8-1996.77"
           case 1'1
             assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:2013.5-2015.8"
+            attribute \src "ls180.v:1998.5-2000.8"
             switch \sdram_bankmachine0_cmd_ready
-              attribute \src "ls180.v:2013.9-2013.37"
+              attribute \src "ls180.v:1998.9-1998.37"
               case 1'1
                 assign $0\subfragments_bankmachine0_next_state[2:0] 3'101
               case 
@@ -263395,27 +262951,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\sdram_bankmachine0_row_close[0:0] 1'1
-        attribute \src "ls180.v:2023.4-2025.7"
-        switch $and$ls180.v:2023$154_Y
-          attribute \src "ls180.v:2023.8-2023.77"
+        attribute \src "ls180.v:2008.4-2010.7"
+        switch $and$ls180.v:2008$122_Y
+          attribute \src "ls180.v:2008.8-2008.77"
           case 1'1
             assign $0\subfragments_bankmachine0_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:2029.4-2038.7"
+        attribute \src "ls180.v:2014.4-2023.7"
         switch \sdram_bankmachine0_trccon_ready
-          attribute \src "ls180.v:2029.8-2029.39"
+          attribute \src "ls180.v:2014.8-2014.39"
           case 1'1
             assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
             assign $0\sdram_bankmachine0_row_open[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
             assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:2034.5-2036.8"
+            attribute \src "ls180.v:2019.5-2021.8"
             switch \sdram_bankmachine0_cmd_ready
-              attribute \src "ls180.v:2034.9-2034.37"
+              attribute \src "ls180.v:2019.9-2019.37"
               case 1'1
                 assign $0\subfragments_bankmachine0_next_state[2:0] 3'110
               case 
@@ -263426,16 +262982,16 @@ module \ls180
       case 3'100
         assign $0\sdram_bankmachine0_row_close[0:0] 1'1
         assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:2041.4-2043.7"
+        attribute \src "ls180.v:2026.4-2028.7"
         switch \sdram_bankmachine0_twtpcon_ready
-          attribute \src "ls180.v:2041.8-2041.40"
+          attribute \src "ls180.v:2026.8-2026.40"
           case 1'1
             assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:2046.4-2048.7"
-        switch $not$ls180.v:2046$155_Y
-          attribute \src "ls180.v:2046.8-2046.41"
+        attribute \src "ls180.v:2031.4-2033.7"
+        switch $not$ls180.v:2031$123_Y
+          attribute \src "ls180.v:2031.8-2031.41"
           case 1'1
             assign $0\subfragments_bankmachine0_next_state[2:0] 3'000
           case 
@@ -263448,51 +263004,51 @@ module \ls180
         assign $0\subfragments_bankmachine0_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:2057.4-2083.7"
+        attribute \src "ls180.v:2042.4-2068.7"
         switch \sdram_bankmachine0_refresh_req
-          attribute \src "ls180.v:2057.8-2057.38"
+          attribute \src "ls180.v:2042.8-2042.38"
           case 1'1
             assign $0\subfragments_bankmachine0_next_state[2:0] 3'100
-          attribute \src "ls180.v:2059.8-2059.12"
+          attribute \src "ls180.v:2044.8-2044.12"
           case 
-            attribute \src "ls180.v:2060.5-2082.8"
+            attribute \src "ls180.v:2045.5-2067.8"
             switch \sdram_bankmachine0_cmd_buffer_source_valid
-              attribute \src "ls180.v:2060.9-2060.51"
+              attribute \src "ls180.v:2045.9-2045.51"
               case 1'1
-                attribute \src "ls180.v:2061.6-2081.9"
+                attribute \src "ls180.v:2046.6-2066.9"
                 switch \sdram_bankmachine0_row_opened
-                  attribute \src "ls180.v:2061.10-2061.39"
+                  attribute \src "ls180.v:2046.10-2046.39"
                   case 1'1
-                    attribute \src "ls180.v:2062.7-2078.10"
+                    attribute \src "ls180.v:2047.7-2063.10"
                     switch \sdram_bankmachine0_row_hit
-                      attribute \src "ls180.v:2062.11-2062.37"
+                      attribute \src "ls180.v:2047.11-2047.37"
                       case 1'1
                         assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
                         assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:2064.8-2071.11"
+                        attribute \src "ls180.v:2049.8-2056.11"
                         switch \sdram_bankmachine0_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:2064.12-2064.59"
+                          attribute \src "ls180.v:2049.12-2049.59"
                           case 1'1
                             assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready
                             assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
                             assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:2068.12-2068.16"
+                          attribute \src "ls180.v:2053.12-2053.16"
                           case 
                             assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready
                             assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:2073.8-2075.11"
-                        switch $and$ls180.v:2073$156_Y
-                          attribute \src "ls180.v:2073.12-2073.78"
+                        attribute \src "ls180.v:2058.8-2060.11"
+                        switch $and$ls180.v:2058$124_Y
+                          attribute \src "ls180.v:2058.12-2058.78"
                           case 1'1
                             assign $0\subfragments_bankmachine0_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:2076.11-2076.15"
+                      attribute \src "ls180.v:2061.11-2061.15"
                       case 
                         assign $0\subfragments_bankmachine0_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:2079.10-2079.14"
+                  attribute \src "ls180.v:2064.10-2064.14"
                   case 
                     assign $0\subfragments_bankmachine0_next_state[2:0] 3'011
                 end
@@ -263516,51 +263072,107 @@ module \ls180
       update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0]
       update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0]
   end
-  attribute \src "ls180.v:200.11-200.24"
-  process $proc$ls180.v:200$1689
+  attribute \src "ls180.v:198.5-198.35"
+  process $proc$ls180.v:198$1611
     assign { } { }
-    assign $1\ram_we[7:0] 8'00000000
+    assign $0\libresocsim_ram_bus_err[0:0] 1'0
     sync always
+      update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0]
     sync init
-      update \ram_we $1\ram_we[7:0]
   end
-  attribute \src "ls180.v:208.5-208.46"
-  process $proc$ls180.v:208$1690
+  attribute \src "ls180.v:201.11-201.32"
+  process $proc$ls180.v:201$1612
     assign { } { }
-    assign $1\interface0_converted_interface_ack[0:0] 1'0
+    assign $1\libresocsim_we[3:0] 4'0000
     sync always
     sync init
-      update \interface0_converted_interface_ack $1\interface0_converted_interface_ack[0:0]
+      update \libresocsim_we $1\libresocsim_we[3:0]
   end
-  attribute \src "ls180.v:2101.1-2108.4"
-  process $proc$ls180.v:2101$160
+  attribute \src "ls180.v:203.12-203.44"
+  process $proc$ls180.v:203$1613
     assign { } { }
-    assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:2103.2-2107.5"
-    switch \sdram_bankmachine1_row_col_n_addr_sel
-      attribute \src "ls180.v:2103.6-2103.43"
-      case 1'1
-        assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:2105.6-2105.10"
-      case 
-        assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2106$162_Y
-    end
+    assign $1\libresocsim_load_storage[31:0] 0
     sync always
-      update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0]
-  end
-  attribute \src "ls180.v:2112.1-2119.4"
-  process $proc$ls180.v:2112$169
+    sync init
+      update \libresocsim_load_storage $1\libresocsim_load_storage[31:0]
+  end
+  attribute \src "ls180.v:204.5-204.31"
+  process $proc$ls180.v:204$1614
+    assign { } { }
+    assign $1\libresocsim_load_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_load_re $1\libresocsim_load_re[0:0]
+  end
+  attribute \src "ls180.v:205.12-205.46"
+  process $proc$ls180.v:205$1615
+    assign { } { }
+    assign $1\libresocsim_reload_storage[31:0] 0
+    sync always
+    sync init
+      update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0]
+  end
+  attribute \src "ls180.v:206.5-206.33"
+  process $proc$ls180.v:206$1616
+    assign { } { }
+    assign $1\libresocsim_reload_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_reload_re $1\libresocsim_reload_re[0:0]
+  end
+  attribute \src "ls180.v:207.5-207.34"
+  process $proc$ls180.v:207$1617
+    assign { } { }
+    assign $1\libresocsim_en_storage[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_en_storage $1\libresocsim_en_storage[0:0]
+  end
+  attribute \src "ls180.v:208.5-208.29"
+  process $proc$ls180.v:208$1618
+    assign { } { }
+    assign $1\libresocsim_en_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_en_re $1\libresocsim_en_re[0:0]
+  end
+  attribute \src "ls180.v:2086.1-2093.4"
+  process $proc$ls180.v:2086$128
+    assign { } { }
+    assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
+    attribute \src "ls180.v:2088.2-2092.5"
+    switch \sdram_bankmachine1_row_col_n_addr_sel
+      attribute \src "ls180.v:2088.6-2088.43"
+      case 1'1
+        assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
+      attribute \src "ls180.v:2090.6-2090.10"
+      case 
+        assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2091$130_Y
+    end
+    sync always
+      update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0]
+  end
+  attribute \src "ls180.v:209.5-209.44"
+  process $proc$ls180.v:209$1619
+    assign { } { }
+    assign $1\libresocsim_update_value_storage[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0]
+  end
+  attribute \src "ls180.v:2097.1-2104.4"
+  process $proc$ls180.v:2097$137
     assign { } { }
     assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:2114.2-2118.5"
-    switch $and$ls180.v:2114$170_Y
-      attribute \src "ls180.v:2114.6-2114.105"
+    attribute \src "ls180.v:2099.2-2103.5"
+    switch $and$ls180.v:2099$138_Y
+      attribute \src "ls180.v:2099.6-2099.105"
       case 1'1
-        attribute \src "ls180.v:2115.3-2117.6"
-        switch $ne$ls180.v:2115$171_Y
-          attribute \src "ls180.v:2115.7-2115.133"
+        attribute \src "ls180.v:2100.3-2102.6"
+        switch $ne$ls180.v:2100$139_Y
+          attribute \src "ls180.v:2100.7-2100.133"
           case 1'1
-            assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2116$172_Y
+            assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2101$140_Y
           case 
         end
       case 
@@ -263568,48 +263180,40 @@ module \ls180
     sync always
       update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:212.5-212.46"
-  process $proc$ls180.v:212$1691
+  attribute \src "ls180.v:210.5-210.39"
+  process $proc$ls180.v:210$1620
     assign { } { }
-    assign $0\interface0_converted_interface_err[0:0] 1'0
+    assign $1\libresocsim_update_value_re[0:0] 1'0
     sync always
-      update \interface0_converted_interface_err $0\interface0_converted_interface_err[0:0]
     sync init
+      update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0]
   end
-  attribute \src "ls180.v:213.5-213.27"
-  process $proc$ls180.v:213$1692
+  attribute \src "ls180.v:211.12-211.44"
+  process $proc$ls180.v:211$1621
     assign { } { }
-    assign $1\converter0_skip[0:0] 1'0
+    assign $1\libresocsim_value_status[31:0] 0
     sync always
     sync init
-      update \converter0_skip $1\converter0_skip[0:0]
+      update \libresocsim_value_status $1\libresocsim_value_status[31:0]
   end
-  attribute \src "ls180.v:2134.1-2141.4"
-  process $proc$ls180.v:2134$173
+  attribute \src "ls180.v:2119.1-2126.4"
+  process $proc$ls180.v:2119$141
     assign { } { }
     assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:2136.2-2140.5"
+    attribute \src "ls180.v:2121.2-2125.5"
     switch \sdram_bankmachine1_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:2136.6-2136.53"
+      attribute \src "ls180.v:2121.6-2121.53"
       case 1'1
-        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2137$174_Y
-      attribute \src "ls180.v:2138.6-2138.10"
+        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2122$142_Y
+      attribute \src "ls180.v:2123.6-2123.10"
       case 
         assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce
     end
     sync always
       update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:214.5-214.30"
-  process $proc$ls180.v:214$1693
-    assign { } { }
-    assign $1\converter0_counter[0:0] 1'0
-    sync always
-    sync init
-      update \converter0_counter $1\converter0_counter[0:0]
-  end
-  attribute \src "ls180.v:2150.1-2243.4"
-  process $proc$ls180.v:2150$182
+  attribute \src "ls180.v:2135.1-2228.4"
+  process $proc$ls180.v:2135$150
     assign { } { }
     assign { } { }
     assign { } { }
@@ -263624,37 +263228,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign $0\sdram_bankmachine1_row_open[0:0] 1'0
+    assign $0\sdram_bankmachine1_row_close[0:0] 1'0
+    assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
+    assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
+    assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0
+    assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
     assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
     assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
     assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
-    assign { } { }
     assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0
     assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0
+    assign { } { }
     assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0
     assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0
-    assign $0\sdram_bankmachine1_row_open[0:0] 1'0
-    assign $0\sdram_bankmachine1_row_close[0:0] 1'0
-    assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
-    assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
-    assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
-    assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0
     assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state
-    attribute \src "ls180.v:2166.2-2242.9"
+    attribute \src "ls180.v:2151.2-2227.9"
     switch \subfragments_bankmachine1_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\sdram_bankmachine1_row_close[0:0] 1'1
-        attribute \src "ls180.v:2168.4-2176.7"
-        switch $and$ls180.v:2168$183_Y
-          attribute \src "ls180.v:2168.8-2168.77"
+        attribute \src "ls180.v:2153.4-2161.7"
+        switch $and$ls180.v:2153$151_Y
+          attribute \src "ls180.v:2153.8-2153.77"
           case 1'1
             assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:2170.5-2172.8"
+            attribute \src "ls180.v:2155.5-2157.8"
             switch \sdram_bankmachine1_cmd_ready
-              attribute \src "ls180.v:2170.9-2170.37"
+              attribute \src "ls180.v:2155.9-2155.37"
               case 1'1
                 assign $0\subfragments_bankmachine1_next_state[2:0] 3'101
               case 
@@ -263664,27 +263268,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\sdram_bankmachine1_row_close[0:0] 1'1
-        attribute \src "ls180.v:2180.4-2182.7"
-        switch $and$ls180.v:2180$184_Y
-          attribute \src "ls180.v:2180.8-2180.77"
+        attribute \src "ls180.v:2165.4-2167.7"
+        switch $and$ls180.v:2165$152_Y
+          attribute \src "ls180.v:2165.8-2165.77"
           case 1'1
             assign $0\subfragments_bankmachine1_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:2186.4-2195.7"
+        attribute \src "ls180.v:2171.4-2180.7"
         switch \sdram_bankmachine1_trccon_ready
-          attribute \src "ls180.v:2186.8-2186.39"
+          attribute \src "ls180.v:2171.8-2171.39"
           case 1'1
             assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
             assign $0\sdram_bankmachine1_row_open[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
             assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:2191.5-2193.8"
+            attribute \src "ls180.v:2176.5-2178.8"
             switch \sdram_bankmachine1_cmd_ready
-              attribute \src "ls180.v:2191.9-2191.37"
+              attribute \src "ls180.v:2176.9-2176.37"
               case 1'1
                 assign $0\subfragments_bankmachine1_next_state[2:0] 3'110
               case 
@@ -263695,16 +263299,16 @@ module \ls180
       case 3'100
         assign $0\sdram_bankmachine1_row_close[0:0] 1'1
         assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:2198.4-2200.7"
+        attribute \src "ls180.v:2183.4-2185.7"
         switch \sdram_bankmachine1_twtpcon_ready
-          attribute \src "ls180.v:2198.8-2198.40"
+          attribute \src "ls180.v:2183.8-2183.40"
           case 1'1
             assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:2203.4-2205.7"
-        switch $not$ls180.v:2203$185_Y
-          attribute \src "ls180.v:2203.8-2203.41"
+        attribute \src "ls180.v:2188.4-2190.7"
+        switch $not$ls180.v:2188$153_Y
+          attribute \src "ls180.v:2188.8-2188.41"
           case 1'1
             assign $0\subfragments_bankmachine1_next_state[2:0] 3'000
           case 
@@ -263717,51 +263321,51 @@ module \ls180
         assign $0\subfragments_bankmachine1_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:2214.4-2240.7"
+        attribute \src "ls180.v:2199.4-2225.7"
         switch \sdram_bankmachine1_refresh_req
-          attribute \src "ls180.v:2214.8-2214.38"
+          attribute \src "ls180.v:2199.8-2199.38"
           case 1'1
             assign $0\subfragments_bankmachine1_next_state[2:0] 3'100
-          attribute \src "ls180.v:2216.8-2216.12"
+          attribute \src "ls180.v:2201.8-2201.12"
           case 
-            attribute \src "ls180.v:2217.5-2239.8"
+            attribute \src "ls180.v:2202.5-2224.8"
             switch \sdram_bankmachine1_cmd_buffer_source_valid
-              attribute \src "ls180.v:2217.9-2217.51"
+              attribute \src "ls180.v:2202.9-2202.51"
               case 1'1
-                attribute \src "ls180.v:2218.6-2238.9"
+                attribute \src "ls180.v:2203.6-2223.9"
                 switch \sdram_bankmachine1_row_opened
-                  attribute \src "ls180.v:2218.10-2218.39"
+                  attribute \src "ls180.v:2203.10-2203.39"
                   case 1'1
-                    attribute \src "ls180.v:2219.7-2235.10"
+                    attribute \src "ls180.v:2204.7-2220.10"
                     switch \sdram_bankmachine1_row_hit
-                      attribute \src "ls180.v:2219.11-2219.37"
+                      attribute \src "ls180.v:2204.11-2204.37"
                       case 1'1
                         assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
                         assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:2221.8-2228.11"
+                        attribute \src "ls180.v:2206.8-2213.11"
                         switch \sdram_bankmachine1_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:2221.12-2221.59"
+                          attribute \src "ls180.v:2206.12-2206.59"
                           case 1'1
                             assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready
                             assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
                             assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:2225.12-2225.16"
+                          attribute \src "ls180.v:2210.12-2210.16"
                           case 
                             assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready
                             assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:2230.8-2232.11"
-                        switch $and$ls180.v:2230$186_Y
-                          attribute \src "ls180.v:2230.12-2230.78"
+                        attribute \src "ls180.v:2215.8-2217.11"
+                        switch $and$ls180.v:2215$154_Y
+                          attribute \src "ls180.v:2215.12-2215.78"
                           case 1'1
                             assign $0\subfragments_bankmachine1_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:2233.11-2233.15"
+                      attribute \src "ls180.v:2218.11-2218.15"
                       case 
                         assign $0\subfragments_bankmachine1_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:2236.10-2236.14"
+                  attribute \src "ls180.v:2221.10-2221.14"
                   case 
                     assign $0\subfragments_bankmachine1_next_state[2:0] 3'011
                 end
@@ -263785,51 +263389,59 @@ module \ls180
       update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0]
       update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0]
   end
-  attribute \src "ls180.v:216.12-216.36"
-  process $proc$ls180.v:216$1694
+  attribute \src "ls180.v:215.5-215.36"
+  process $proc$ls180.v:215$1622
     assign { } { }
-    assign $1\converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign $1\libresocsim_zero_pending[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0]
+  end
+  attribute \src "ls180.v:217.5-217.34"
+  process $proc$ls180.v:217$1623
+    assign { } { }
+    assign $1\libresocsim_zero_clear[0:0] 1'0
     sync always
     sync init
-      update \converter0_dat_r $1\converter0_dat_r[63:0]
+      update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0]
   end
-  attribute \src "ls180.v:223.5-223.46"
-  process $proc$ls180.v:223$1695
+  attribute \src "ls180.v:218.5-218.40"
+  process $proc$ls180.v:218$1624
     assign { } { }
-    assign $1\interface1_converted_interface_ack[0:0] 1'0
+    assign $1\libresocsim_zero_old_trigger[0:0] 1'0
     sync always
     sync init
-      update \interface1_converted_interface_ack $1\interface1_converted_interface_ack[0:0]
+      update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0]
   end
-  attribute \src "ls180.v:2258.1-2265.4"
-  process $proc$ls180.v:2258$190
+  attribute \src "ls180.v:2243.1-2250.4"
+  process $proc$ls180.v:2243$158
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:2260.2-2264.5"
+    attribute \src "ls180.v:2245.2-2249.5"
     switch \sdram_bankmachine2_row_col_n_addr_sel
-      attribute \src "ls180.v:2260.6-2260.43"
+      attribute \src "ls180.v:2245.6-2245.43"
       case 1'1
         assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:2262.6-2262.10"
+      attribute \src "ls180.v:2247.6-2247.10"
       case 
-        assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2263$192_Y
+        assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2248$160_Y
     end
     sync always
       update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:2269.1-2276.4"
-  process $proc$ls180.v:2269$199
+  attribute \src "ls180.v:2254.1-2261.4"
+  process $proc$ls180.v:2254$167
     assign { } { }
     assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:2271.2-2275.5"
-    switch $and$ls180.v:2271$200_Y
-      attribute \src "ls180.v:2271.6-2271.105"
+    attribute \src "ls180.v:2256.2-2260.5"
+    switch $and$ls180.v:2256$168_Y
+      attribute \src "ls180.v:2256.6-2256.105"
       case 1'1
-        attribute \src "ls180.v:2272.3-2274.6"
-        switch $ne$ls180.v:2272$201_Y
-          attribute \src "ls180.v:2272.7-2272.133"
+        attribute \src "ls180.v:2257.3-2259.6"
+        switch $ne$ls180.v:2257$169_Y
+          attribute \src "ls180.v:2257.7-2257.133"
           case 1'1
-            assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2273$202_Y
+            assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2258$170_Y
           case 
         end
       case 
@@ -263837,49 +263449,48 @@ module \ls180
     sync always
       update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:227.5-227.46"
-  process $proc$ls180.v:227$1696
-    assign { } { }
-    assign $0\interface1_converted_interface_err[0:0] 1'0
-    sync always
-      update \interface1_converted_interface_err $0\interface1_converted_interface_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:228.5-228.27"
-  process $proc$ls180.v:228$1697
-    assign { } { }
-    assign $1\converter1_skip[0:0] 1'0
-    sync always
-    sync init
-      update \converter1_skip $1\converter1_skip[0:0]
-  end
-  attribute \src "ls180.v:229.5-229.30"
-  process $proc$ls180.v:229$1698
+  attribute \src "ls180.v:227.5-227.44"
+  process $proc$ls180.v:227$1625
     assign { } { }
-    assign $1\converter1_counter[0:0] 1'0
+    assign $1\libresocsim_eventmanager_storage[0:0] 1'0
     sync always
     sync init
-      update \converter1_counter $1\converter1_counter[0:0]
+      update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0]
   end
-  attribute \src "ls180.v:2291.1-2298.4"
-  process $proc$ls180.v:2291$203
+  attribute \src "ls180.v:2276.1-2283.4"
+  process $proc$ls180.v:2276$171
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:2293.2-2297.5"
+    attribute \src "ls180.v:2278.2-2282.5"
     switch \sdram_bankmachine2_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:2293.6-2293.53"
+      attribute \src "ls180.v:2278.6-2278.53"
       case 1'1
-        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2294$204_Y
-      attribute \src "ls180.v:2295.6-2295.10"
+        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2279$172_Y
+      attribute \src "ls180.v:2280.6-2280.10"
       case 
         assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce
     end
     sync always
       update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:2307.1-2400.4"
-  process $proc$ls180.v:2307$212
+  attribute \src "ls180.v:228.5-228.39"
+  process $proc$ls180.v:228$1626
+    assign { } { }
+    assign $1\libresocsim_eventmanager_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0]
+  end
+  attribute \src "ls180.v:229.12-229.37"
+  process $proc$ls180.v:229$1627
     assign { } { }
+    assign $1\libresocsim_value[31:0] 0
+    sync always
+    sync init
+      update \libresocsim_value $1\libresocsim_value[31:0]
+  end
+  attribute \src "ls180.v:2292.1-2385.4"
+  process $proc$ls180.v:2292$180
     assign { } { }
     assign { } { }
     assign { } { }
@@ -263893,37 +263504,38 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\sdram_bankmachine2_row_close[0:0] 1'0
     assign { } { }
+    assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+    assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
+    assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0
+    assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0
+    assign $0\sdram_bankmachine2_row_open[0:0] 1'0
+    assign $0\sdram_bankmachine2_row_close[0:0] 1'0
     assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
     assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
     assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'0
     assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
-    assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
+    assign { } { }
     assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
     assign $0\sdram_bankmachine2_req_wdata_ready[0:0] 1'0
-    assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
-    assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0
-    assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0
-    assign $0\sdram_bankmachine2_row_open[0:0] 1'0
     assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state
-    attribute \src "ls180.v:2323.2-2399.9"
+    attribute \src "ls180.v:2308.2-2384.9"
     switch \subfragments_bankmachine2_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\sdram_bankmachine2_row_close[0:0] 1'1
-        attribute \src "ls180.v:2325.4-2333.7"
-        switch $and$ls180.v:2325$213_Y
-          attribute \src "ls180.v:2325.8-2325.77"
+        attribute \src "ls180.v:2310.4-2318.7"
+        switch $and$ls180.v:2310$181_Y
+          attribute \src "ls180.v:2310.8-2310.77"
           case 1'1
             assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:2327.5-2329.8"
+            attribute \src "ls180.v:2312.5-2314.8"
             switch \sdram_bankmachine2_cmd_ready
-              attribute \src "ls180.v:2327.9-2327.37"
+              attribute \src "ls180.v:2312.9-2312.37"
               case 1'1
                 assign $0\subfragments_bankmachine2_next_state[2:0] 3'101
               case 
@@ -263933,27 +263545,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\sdram_bankmachine2_row_close[0:0] 1'1
-        attribute \src "ls180.v:2337.4-2339.7"
-        switch $and$ls180.v:2337$214_Y
-          attribute \src "ls180.v:2337.8-2337.77"
+        attribute \src "ls180.v:2322.4-2324.7"
+        switch $and$ls180.v:2322$182_Y
+          attribute \src "ls180.v:2322.8-2322.77"
           case 1'1
             assign $0\subfragments_bankmachine2_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:2343.4-2352.7"
+        attribute \src "ls180.v:2328.4-2337.7"
         switch \sdram_bankmachine2_trccon_ready
-          attribute \src "ls180.v:2343.8-2343.39"
+          attribute \src "ls180.v:2328.8-2328.39"
           case 1'1
             assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
             assign $0\sdram_bankmachine2_row_open[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
             assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:2348.5-2350.8"
+            attribute \src "ls180.v:2333.5-2335.8"
             switch \sdram_bankmachine2_cmd_ready
-              attribute \src "ls180.v:2348.9-2348.37"
+              attribute \src "ls180.v:2333.9-2333.37"
               case 1'1
                 assign $0\subfragments_bankmachine2_next_state[2:0] 3'110
               case 
@@ -263964,16 +263576,16 @@ module \ls180
       case 3'100
         assign $0\sdram_bankmachine2_row_close[0:0] 1'1
         assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:2355.4-2357.7"
+        attribute \src "ls180.v:2340.4-2342.7"
         switch \sdram_bankmachine2_twtpcon_ready
-          attribute \src "ls180.v:2355.8-2355.40"
+          attribute \src "ls180.v:2340.8-2340.40"
           case 1'1
             assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:2360.4-2362.7"
-        switch $not$ls180.v:2360$215_Y
-          attribute \src "ls180.v:2360.8-2360.41"
+        attribute \src "ls180.v:2345.4-2347.7"
+        switch $not$ls180.v:2345$183_Y
+          attribute \src "ls180.v:2345.8-2345.41"
           case 1'1
             assign $0\subfragments_bankmachine2_next_state[2:0] 3'000
           case 
@@ -263986,51 +263598,51 @@ module \ls180
         assign $0\subfragments_bankmachine2_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:2371.4-2397.7"
+        attribute \src "ls180.v:2356.4-2382.7"
         switch \sdram_bankmachine2_refresh_req
-          attribute \src "ls180.v:2371.8-2371.38"
+          attribute \src "ls180.v:2356.8-2356.38"
           case 1'1
             assign $0\subfragments_bankmachine2_next_state[2:0] 3'100
-          attribute \src "ls180.v:2373.8-2373.12"
+          attribute \src "ls180.v:2358.8-2358.12"
           case 
-            attribute \src "ls180.v:2374.5-2396.8"
+            attribute \src "ls180.v:2359.5-2381.8"
             switch \sdram_bankmachine2_cmd_buffer_source_valid
-              attribute \src "ls180.v:2374.9-2374.51"
+              attribute \src "ls180.v:2359.9-2359.51"
               case 1'1
-                attribute \src "ls180.v:2375.6-2395.9"
+                attribute \src "ls180.v:2360.6-2380.9"
                 switch \sdram_bankmachine2_row_opened
-                  attribute \src "ls180.v:2375.10-2375.39"
+                  attribute \src "ls180.v:2360.10-2360.39"
                   case 1'1
-                    attribute \src "ls180.v:2376.7-2392.10"
+                    attribute \src "ls180.v:2361.7-2377.10"
                     switch \sdram_bankmachine2_row_hit
-                      attribute \src "ls180.v:2376.11-2376.37"
+                      attribute \src "ls180.v:2361.11-2361.37"
                       case 1'1
                         assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
                         assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:2378.8-2385.11"
+                        attribute \src "ls180.v:2363.8-2370.11"
                         switch \sdram_bankmachine2_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:2378.12-2378.59"
+                          attribute \src "ls180.v:2363.12-2363.59"
                           case 1'1
                             assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready
                             assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
                             assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:2382.12-2382.16"
+                          attribute \src "ls180.v:2367.12-2367.16"
                           case 
                             assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready
                             assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:2387.8-2389.11"
-                        switch $and$ls180.v:2387$216_Y
-                          attribute \src "ls180.v:2387.12-2387.78"
+                        attribute \src "ls180.v:2372.8-2374.11"
+                        switch $and$ls180.v:2372$184_Y
+                          attribute \src "ls180.v:2372.12-2372.78"
                           case 1'1
                             assign $0\subfragments_bankmachine2_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:2390.11-2390.15"
+                      attribute \src "ls180.v:2375.11-2375.15"
                       case 
                         assign $0\subfragments_bankmachine2_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:2393.10-2393.14"
+                  attribute \src "ls180.v:2378.10-2378.14"
                   case 
                     assign $0\subfragments_bankmachine2_next_state[2:0] 3'011
                 end
@@ -264054,51 +263666,51 @@ module \ls180
       update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0]
       update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0]
   end
-  attribute \src "ls180.v:231.12-231.36"
-  process $proc$ls180.v:231$1699
+  attribute \src "ls180.v:236.5-236.31"
+  process $proc$ls180.v:236$1628
     assign { } { }
-    assign $1\converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign $1\ram_bus_ram_bus_ack[0:0] 1'0
     sync always
     sync init
-      update \converter1_dat_r $1\converter1_dat_r[63:0]
+      update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0]
   end
-  attribute \src "ls180.v:235.5-235.19"
-  process $proc$ls180.v:235$1700
+  attribute \src "ls180.v:240.5-240.31"
+  process $proc$ls180.v:240$1629
     assign { } { }
-    assign $1\int_rst[0:0] 1'1
+    assign $0\ram_bus_ram_bus_err[0:0] 1'0
     sync always
+      update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0]
     sync init
-      update \int_rst $1\int_rst[0:0]
   end
-  attribute \src "ls180.v:2415.1-2422.4"
-  process $proc$ls180.v:2415$220
+  attribute \src "ls180.v:2400.1-2407.4"
+  process $proc$ls180.v:2400$188
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
-    attribute \src "ls180.v:2417.2-2421.5"
+    attribute \src "ls180.v:2402.2-2406.5"
     switch \sdram_bankmachine3_row_col_n_addr_sel
-      attribute \src "ls180.v:2417.6-2417.43"
+      attribute \src "ls180.v:2402.6-2402.43"
       case 1'1
         assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
-      attribute \src "ls180.v:2419.6-2419.10"
+      attribute \src "ls180.v:2404.6-2404.10"
       case 
-        assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2420$222_Y
+        assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2405$190_Y
     end
     sync always
       update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:2426.1-2433.4"
-  process $proc$ls180.v:2426$229
+  attribute \src "ls180.v:2411.1-2418.4"
+  process $proc$ls180.v:2411$197
     assign { } { }
     assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0
-    attribute \src "ls180.v:2428.2-2432.5"
-    switch $and$ls180.v:2428$230_Y
-      attribute \src "ls180.v:2428.6-2428.105"
+    attribute \src "ls180.v:2413.2-2417.5"
+    switch $and$ls180.v:2413$198_Y
+      attribute \src "ls180.v:2413.6-2413.105"
       case 1'1
-        attribute \src "ls180.v:2429.3-2431.6"
-        switch $ne$ls180.v:2429$231_Y
-          attribute \src "ls180.v:2429.7-2429.133"
+        attribute \src "ls180.v:2414.3-2416.6"
+        switch $ne$ls180.v:2414$199_Y
+          attribute \src "ls180.v:2414.7-2414.133"
           case 1'1
-            assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2430$232_Y
+            assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2415$200_Y
           case 
         end
       case 
@@ -264106,24 +263718,32 @@ module \ls180
     sync always
       update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:2448.1-2455.4"
-  process $proc$ls180.v:2448$233
+  attribute \src "ls180.v:243.11-243.24"
+  process $proc$ls180.v:243$1630
+    assign { } { }
+    assign $1\ram_we[3:0] 4'0000
+    sync always
+    sync init
+      update \ram_we $1\ram_we[3:0]
+  end
+  attribute \src "ls180.v:2433.1-2440.4"
+  process $proc$ls180.v:2433$201
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    attribute \src "ls180.v:2450.2-2454.5"
+    attribute \src "ls180.v:2435.2-2439.5"
     switch \sdram_bankmachine3_cmd_buffer_lookahead_replace
-      attribute \src "ls180.v:2450.6-2450.53"
+      attribute \src "ls180.v:2435.6-2435.53"
       case 1'1
-        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2451$234_Y
-      attribute \src "ls180.v:2452.6-2452.10"
+        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2436$202_Y
+      attribute \src "ls180.v:2437.6-2437.10"
       case 
         assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce
     end
     sync always
       update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:2464.1-2557.4"
-  process $proc$ls180.v:2464$242
+  attribute \src "ls180.v:2449.1-2542.4"
+  process $proc$ls180.v:2449$210
     assign { } { }
     assign { } { }
     assign { } { }
@@ -264138,37 +263758,37 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\sdram_bankmachine3_row_open[0:0] 1'0
-    assign $0\sdram_bankmachine3_row_close[0:0] 1'0
-    assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
-    assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
-    assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0
-    assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
     assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
     assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
     assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
+    assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
     assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0
-    assign { } { }
     assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0
+    assign $0\sdram_bankmachine3_row_open[0:0] 1'0
+    assign { } { }
+    assign $0\sdram_bankmachine3_row_close[0:0] 1'0
+    assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
+    assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
+    assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0
     assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state
-    attribute \src "ls180.v:2480.2-2556.9"
+    attribute \src "ls180.v:2465.2-2541.9"
     switch \subfragments_bankmachine3_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\sdram_bankmachine3_row_close[0:0] 1'1
-        attribute \src "ls180.v:2482.4-2490.7"
-        switch $and$ls180.v:2482$243_Y
-          attribute \src "ls180.v:2482.8-2482.77"
+        attribute \src "ls180.v:2467.4-2475.7"
+        switch $and$ls180.v:2467$211_Y
+          attribute \src "ls180.v:2467.8-2467.77"
           case 1'1
             assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
-            attribute \src "ls180.v:2484.5-2486.8"
+            attribute \src "ls180.v:2469.5-2471.8"
             switch \sdram_bankmachine3_cmd_ready
-              attribute \src "ls180.v:2484.9-2484.37"
+              attribute \src "ls180.v:2469.9-2469.37"
               case 1'1
                 assign $0\subfragments_bankmachine3_next_state[2:0] 3'101
               case 
@@ -264178,27 +263798,27 @@ module \ls180
       attribute \src "ls180.v:0.0-0.0"
       case 3'010
         assign $0\sdram_bankmachine3_row_close[0:0] 1'1
-        attribute \src "ls180.v:2494.4-2496.7"
-        switch $and$ls180.v:2494$244_Y
-          attribute \src "ls180.v:2494.8-2494.77"
+        attribute \src "ls180.v:2479.4-2481.7"
+        switch $and$ls180.v:2479$212_Y
+          attribute \src "ls180.v:2479.8-2479.77"
           case 1'1
             assign $0\subfragments_bankmachine3_next_state[2:0] 3'101
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:2500.4-2509.7"
+        attribute \src "ls180.v:2485.4-2494.7"
         switch \sdram_bankmachine3_trccon_ready
-          attribute \src "ls180.v:2500.8-2500.39"
+          attribute \src "ls180.v:2485.8-2485.39"
           case 1'1
             assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
             assign $0\sdram_bankmachine3_row_open[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
             assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
-            attribute \src "ls180.v:2505.5-2507.8"
+            attribute \src "ls180.v:2490.5-2492.8"
             switch \sdram_bankmachine3_cmd_ready
-              attribute \src "ls180.v:2505.9-2505.37"
+              attribute \src "ls180.v:2490.9-2490.37"
               case 1'1
                 assign $0\subfragments_bankmachine3_next_state[2:0] 3'110
               case 
@@ -264209,16 +263829,16 @@ module \ls180
       case 3'100
         assign $0\sdram_bankmachine3_row_close[0:0] 1'1
         assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
-        attribute \src "ls180.v:2512.4-2514.7"
+        attribute \src "ls180.v:2497.4-2499.7"
         switch \sdram_bankmachine3_twtpcon_ready
-          attribute \src "ls180.v:2512.8-2512.40"
+          attribute \src "ls180.v:2497.8-2497.40"
           case 1'1
             assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:2517.4-2519.7"
-        switch $not$ls180.v:2517$245_Y
-          attribute \src "ls180.v:2517.8-2517.41"
+        attribute \src "ls180.v:2502.4-2504.7"
+        switch $not$ls180.v:2502$213_Y
+          attribute \src "ls180.v:2502.8-2502.41"
           case 1'1
             assign $0\subfragments_bankmachine3_next_state[2:0] 3'000
           case 
@@ -264231,51 +263851,51 @@ module \ls180
         assign $0\subfragments_bankmachine3_next_state[2:0] 3'000
       attribute \src "ls180.v:0.0-0.0"
       case 
-        attribute \src "ls180.v:2528.4-2554.7"
+        attribute \src "ls180.v:2513.4-2539.7"
         switch \sdram_bankmachine3_refresh_req
-          attribute \src "ls180.v:2528.8-2528.38"
+          attribute \src "ls180.v:2513.8-2513.38"
           case 1'1
             assign $0\subfragments_bankmachine3_next_state[2:0] 3'100
-          attribute \src "ls180.v:2530.8-2530.12"
+          attribute \src "ls180.v:2515.8-2515.12"
           case 
-            attribute \src "ls180.v:2531.5-2553.8"
+            attribute \src "ls180.v:2516.5-2538.8"
             switch \sdram_bankmachine3_cmd_buffer_source_valid
-              attribute \src "ls180.v:2531.9-2531.51"
+              attribute \src "ls180.v:2516.9-2516.51"
               case 1'1
-                attribute \src "ls180.v:2532.6-2552.9"
+                attribute \src "ls180.v:2517.6-2537.9"
                 switch \sdram_bankmachine3_row_opened
-                  attribute \src "ls180.v:2532.10-2532.39"
+                  attribute \src "ls180.v:2517.10-2517.39"
                   case 1'1
-                    attribute \src "ls180.v:2533.7-2549.10"
+                    attribute \src "ls180.v:2518.7-2534.10"
                     switch \sdram_bankmachine3_row_hit
-                      attribute \src "ls180.v:2533.11-2533.37"
+                      attribute \src "ls180.v:2518.11-2518.37"
                       case 1'1
                         assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
                         assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
-                        attribute \src "ls180.v:2535.8-2542.11"
+                        attribute \src "ls180.v:2520.8-2527.11"
                         switch \sdram_bankmachine3_cmd_buffer_source_payload_we
-                          attribute \src "ls180.v:2535.12-2535.59"
+                          attribute \src "ls180.v:2520.12-2520.59"
                           case 1'1
                             assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready
                             assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
                             assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1
-                          attribute \src "ls180.v:2539.12-2539.16"
+                          attribute \src "ls180.v:2524.12-2524.16"
                           case 
                             assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready
                             assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
                         end
-                        attribute \src "ls180.v:2544.8-2546.11"
-                        switch $and$ls180.v:2544$246_Y
-                          attribute \src "ls180.v:2544.12-2544.78"
+                        attribute \src "ls180.v:2529.8-2531.11"
+                        switch $and$ls180.v:2529$214_Y
+                          attribute \src "ls180.v:2529.12-2529.78"
                           case 1'1
                             assign $0\subfragments_bankmachine3_next_state[2:0] 3'010
                           case 
                         end
-                      attribute \src "ls180.v:2547.11-2547.15"
+                      attribute \src "ls180.v:2532.11-2532.15"
                       case 
                         assign $0\subfragments_bankmachine3_next_state[2:0] 3'001
                     end
-                  attribute \src "ls180.v:2550.10-2550.14"
+                  attribute \src "ls180.v:2535.10-2535.14"
                   case 
                     assign $0\subfragments_bankmachine3_next_state[2:0] 3'011
                 end
@@ -264299,80 +263919,32 @@ module \ls180
       update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0]
       update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0]
   end
-  attribute \src "ls180.v:250.12-250.33"
-  process $proc$ls180.v:250$1701
-    assign { } { }
-    assign $1\dfi_p0_rddata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \dfi_p0_rddata $1\dfi_p0_rddata[15:0]
-  end
-  attribute \src "ls180.v:251.5-251.31"
-  process $proc$ls180.v:251$1702
-    assign { } { }
-    assign $1\dfi_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:252.11-252.27"
-  process $proc$ls180.v:252$1703
-    assign { } { }
-    assign $1\rddata_en[2:0] 3'000
-    sync always
-    sync init
-      update \rddata_en $1\rddata_en[2:0]
-  end
-  attribute \src "ls180.v:255.5-255.31"
-  process $proc$ls180.v:255$1704
-    assign { } { }
-    assign $1\sdram_inti_p0_cas_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0]
-  end
-  attribute \src "ls180.v:256.5-256.30"
-  process $proc$ls180.v:256$1705
-    assign { } { }
-    assign $1\sdram_inti_p0_cs_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0]
-  end
-  attribute \src "ls180.v:257.5-257.31"
-  process $proc$ls180.v:257$1706
+  attribute \src "ls180.v:248.5-248.19"
+  process $proc$ls180.v:248$1631
     assign { } { }
-    assign $1\sdram_inti_p0_ras_n[0:0] 1'1
+    assign $1\int_rst[0:0] 1'1
     sync always
     sync init
-      update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0]
+      update \int_rst $1\int_rst[0:0]
   end
-  attribute \src "ls180.v:2577.1-2583.4"
-  process $proc$ls180.v:2577$285
+  attribute \src "ls180.v:2562.1-2568.4"
+  process $proc$ls180.v:2562$253
     assign { } { }
     assign { } { }
-    assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2579$298_Y
-    assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2580$311_Y
-    assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2581$324_Y
-    assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2582$337_Y
+    assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2564$266_Y
+    assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2565$279_Y
+    assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2566$292_Y
+    assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2567$305_Y
     sync always
       update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0]
   end
-  attribute \src "ls180.v:258.5-258.30"
-  process $proc$ls180.v:258$1707
-    assign { } { }
-    assign $1\sdram_inti_p0_we_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0]
-  end
-  attribute \src "ls180.v:2591.1-2596.4"
-  process $proc$ls180.v:2591$338
+  attribute \src "ls180.v:2576.1-2581.4"
+  process $proc$ls180.v:2576$306
     assign { } { }
     assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
-    attribute \src "ls180.v:2593.2-2595.5"
+    attribute \src "ls180.v:2578.2-2580.5"
     switch \sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:2593.6-2593.32"
+      attribute \src "ls180.v:2578.6-2578.32"
       case 1'1
         assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0
       case 
@@ -264380,13 +263952,13 @@ module \ls180
     sync always
       update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:2597.1-2602.4"
-  process $proc$ls180.v:2597$339
+  attribute \src "ls180.v:2582.1-2587.4"
+  process $proc$ls180.v:2582$307
     assign { } { }
     assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
-    attribute \src "ls180.v:2599.2-2601.5"
+    attribute \src "ls180.v:2584.2-2586.5"
     switch \sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:2599.6-2599.32"
+      attribute \src "ls180.v:2584.6-2584.32"
       case 1'1
         assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1
       case 
@@ -264394,13 +263966,13 @@ module \ls180
     sync always
       update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:2603.1-2608.4"
-  process $proc$ls180.v:2603$340
+  attribute \src "ls180.v:2588.1-2593.4"
+  process $proc$ls180.v:2588$308
     assign { } { }
     assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0
-    attribute \src "ls180.v:2605.2-2607.5"
+    attribute \src "ls180.v:2590.2-2592.5"
     switch \sdram_choose_cmd_cmd_valid
-      attribute \src "ls180.v:2605.6-2605.32"
+      attribute \src "ls180.v:2590.6-2590.32"
       case 1'1
         assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2
       case 
@@ -264408,32 +263980,24 @@ module \ls180
     sync always
       update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:2610.1-2616.4"
-  process $proc$ls180.v:2610$343
+  attribute \src "ls180.v:2595.1-2601.4"
+  process $proc$ls180.v:2595$311
     assign { } { }
     assign { } { }
-    assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2612$356_Y
-    assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2613$369_Y
-    assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2614$382_Y
-    assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2615$395_Y
+    assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2597$324_Y
+    assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2598$337_Y
+    assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2599$350_Y
+    assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2600$363_Y
     sync always
       update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0]
   end
-  attribute \src "ls180.v:262.5-262.31"
-  process $proc$ls180.v:262$1708
-    assign { } { }
-    assign $0\sdram_inti_p0_act_n[0:0] 1'1
-    sync always
-      update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:2624.1-2629.4"
-  process $proc$ls180.v:2624$396
+  attribute \src "ls180.v:2609.1-2614.4"
+  process $proc$ls180.v:2609$364
     assign { } { }
     assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0
-    attribute \src "ls180.v:2626.2-2628.5"
+    attribute \src "ls180.v:2611.2-2613.5"
     switch \sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:2626.6-2626.32"
+      attribute \src "ls180.v:2611.6-2611.32"
       case 1'1
         assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3
       case 
@@ -264441,13 +264005,13 @@ module \ls180
     sync always
       update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:2630.1-2635.4"
-  process $proc$ls180.v:2630$397
+  attribute \src "ls180.v:2615.1-2620.4"
+  process $proc$ls180.v:2615$365
     assign { } { }
     assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0
-    attribute \src "ls180.v:2632.2-2634.5"
+    attribute \src "ls180.v:2617.2-2619.5"
     switch \sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:2632.6-2632.32"
+      attribute \src "ls180.v:2617.6-2617.32"
       case 1'1
         assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4
       case 
@@ -264455,13 +264019,13 @@ module \ls180
     sync always
       update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:2636.1-2641.4"
-  process $proc$ls180.v:2636$398
+  attribute \src "ls180.v:2621.1-2626.4"
+  process $proc$ls180.v:2621$366
     assign { } { }
     assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0
-    attribute \src "ls180.v:2638.2-2640.5"
+    attribute \src "ls180.v:2623.2-2625.5"
     switch \sdram_choose_req_cmd_valid
-      attribute \src "ls180.v:2638.6-2638.32"
+      attribute \src "ls180.v:2623.6-2623.32"
       case 1'1
         assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5
       case 
@@ -264469,20 +264033,20 @@ module \ls180
     sync always
       update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:2642.1-2650.4"
-  process $proc$ls180.v:2642$399
+  attribute \src "ls180.v:2627.1-2635.4"
+  process $proc$ls180.v:2627$367
     assign { } { }
     assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:2644.2-2646.5"
-    switch $and$ls180.v:2644$402_Y
-      attribute \src "ls180.v:2644.6-2644.100"
+    attribute \src "ls180.v:2629.2-2631.5"
+    switch $and$ls180.v:2629$370_Y
+      attribute \src "ls180.v:2629.6-2629.100"
       case 1'1
         assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:2647.2-2649.5"
-    switch $and$ls180.v:2647$405_Y
-      attribute \src "ls180.v:2647.6-2647.100"
+    attribute \src "ls180.v:2632.2-2634.5"
+    switch $and$ls180.v:2632$373_Y
+      attribute \src "ls180.v:2632.6-2632.100"
       case 1'1
         assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1
       case 
@@ -264490,20 +264054,28 @@ module \ls180
     sync always
       update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:2651.1-2659.4"
-  process $proc$ls180.v:2651$406
+  attribute \src "ls180.v:263.12-263.33"
+  process $proc$ls180.v:263$1632
+    assign { } { }
+    assign $1\dfi_p0_rddata[15:0] 16'0000000000000000
+    sync always
+    sync init
+      update \dfi_p0_rddata $1\dfi_p0_rddata[15:0]
+  end
+  attribute \src "ls180.v:2636.1-2644.4"
+  process $proc$ls180.v:2636$374
     assign { } { }
     assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:2653.2-2655.5"
-    switch $and$ls180.v:2653$409_Y
-      attribute \src "ls180.v:2653.6-2653.100"
+    attribute \src "ls180.v:2638.2-2640.5"
+    switch $and$ls180.v:2638$377_Y
+      attribute \src "ls180.v:2638.6-2638.100"
       case 1'1
         assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:2656.2-2658.5"
-    switch $and$ls180.v:2656$412_Y
-      attribute \src "ls180.v:2656.6-2656.100"
+    attribute \src "ls180.v:2641.2-2643.5"
+    switch $and$ls180.v:2641$380_Y
+      attribute \src "ls180.v:2641.6-2641.100"
       case 1'1
         assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1
       case 
@@ -264511,20 +264083,28 @@ module \ls180
     sync always
       update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:2660.1-2668.4"
-  process $proc$ls180.v:2660$413
+  attribute \src "ls180.v:264.5-264.31"
+  process $proc$ls180.v:264$1633
+    assign { } { }
+    assign $1\dfi_p0_rddata_valid[0:0] 1'0
+    sync always
+    sync init
+      update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0]
+  end
+  attribute \src "ls180.v:2645.1-2653.4"
+  process $proc$ls180.v:2645$381
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:2662.2-2664.5"
-    switch $and$ls180.v:2662$416_Y
-      attribute \src "ls180.v:2662.6-2662.100"
+    attribute \src "ls180.v:2647.2-2649.5"
+    switch $and$ls180.v:2647$384_Y
+      attribute \src "ls180.v:2647.6-2647.100"
       case 1'1
         assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:2665.2-2667.5"
-    switch $and$ls180.v:2665$419_Y
-      attribute \src "ls180.v:2665.6-2665.100"
+    attribute \src "ls180.v:2650.2-2652.5"
+    switch $and$ls180.v:2650$387_Y
+      attribute \src "ls180.v:2650.6-2650.100"
       case 1'1
         assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1
       case 
@@ -264532,20 +264112,28 @@ module \ls180
     sync always
       update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:2669.1-2677.4"
-  process $proc$ls180.v:2669$420
+  attribute \src "ls180.v:265.11-265.27"
+  process $proc$ls180.v:265$1634
+    assign { } { }
+    assign $1\rddata_en[2:0] 3'000
+    sync always
+    sync init
+      update \rddata_en $1\rddata_en[2:0]
+  end
+  attribute \src "ls180.v:2654.1-2662.4"
+  process $proc$ls180.v:2654$388
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0
-    attribute \src "ls180.v:2671.2-2673.5"
-    switch $and$ls180.v:2671$423_Y
-      attribute \src "ls180.v:2671.6-2671.100"
+    attribute \src "ls180.v:2656.2-2658.5"
+    switch $and$ls180.v:2656$391_Y
+      attribute \src "ls180.v:2656.6-2656.100"
       case 1'1
         assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:2674.2-2676.5"
-    switch $and$ls180.v:2674$426_Y
-      attribute \src "ls180.v:2674.6-2674.100"
+    attribute \src "ls180.v:2659.2-2661.5"
+    switch $and$ls180.v:2659$394_Y
+      attribute \src "ls180.v:2659.6-2659.100"
       case 1'1
         assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1
       case 
@@ -264553,24 +264141,8 @@ module \ls180
     sync always
       update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:267.12-267.40"
-  process $proc$ls180.v:267$1709
-    assign { } { }
-    assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0]
-  end
-  attribute \src "ls180.v:268.5-268.38"
-  process $proc$ls180.v:268$1710
-    assign { } { }
-    assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:2682.1-2754.4"
-  process $proc$ls180.v:2682$429
+  attribute \src "ls180.v:2667.1-2739.4"
+  process $proc$ls180.v:2667$397
     assign { } { }
     assign { } { }
     assign { } { }
@@ -264580,47 +264152,47 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\sdram_choose_req_cmd_ready[0:0] 1'0
-    assign $0\sdram_steerer_sel[1:0] 2'00
-    assign $0\sdram_en0[0:0] 1'0
     assign $0\sdram_en1[0:0] 1'0
-    assign $0\sdram_choose_req_want_writes[0:0] 1'0
     assign $0\sdram_choose_req_want_reads[0:0] 1'0
-    assign { } { }
+    assign $0\sdram_choose_req_want_writes[0:0] 1'0
     assign $0\sdram_cmd_ready[0:0] 1'0
     assign { } { }
+    assign $0\sdram_choose_req_cmd_ready[0:0] 1'0
+    assign $0\sdram_steerer_sel[1:0] 2'00
+    assign { } { }
+    assign $0\sdram_en0[0:0] 1'0
     assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed
     assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state
-    attribute \src "ls180.v:2694.2-2753.9"
+    attribute \src "ls180.v:2679.2-2738.9"
     switch \subfragments_multiplexer_state
       attribute \src "ls180.v:0.0-0.0"
       case 3'001
         assign $0\sdram_en1[0:0] 1'1
         assign $0\sdram_choose_req_want_writes[0:0] 1'1
         assign $0\sdram_steerer_sel[1:0] 2'10
-        attribute \src "ls180.v:2698.4-2704.7"
+        attribute \src "ls180.v:2683.4-2689.7"
         switch 1'1
-          attribute \src "ls180.v:2698.8-2698.12"
+          attribute \src "ls180.v:2683.8-2683.12"
           case 1'1
-            assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2699$436_Y
+            assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2684$404_Y
           case 
         end
-        attribute \src "ls180.v:2706.4-2710.7"
+        attribute \src "ls180.v:2691.4-2695.7"
         switch \sdram_read_available
-          attribute \src "ls180.v:2706.8-2706.28"
+          attribute \src "ls180.v:2691.8-2691.28"
           case 1'1
-            attribute \src "ls180.v:2707.5-2709.8"
-            switch $or$ls180.v:2707$438_Y
-              attribute \src "ls180.v:2707.9-2707.53"
+            attribute \src "ls180.v:2692.5-2694.8"
+            switch $or$ls180.v:2692$406_Y
+              attribute \src "ls180.v:2692.9-2692.53"
               case 1'1
                 assign $0\subfragments_multiplexer_next_state[2:0] 3'011
               case 
             end
           case 
         end
-        attribute \src "ls180.v:2711.4-2713.7"
+        attribute \src "ls180.v:2696.4-2698.7"
         switch \sdram_go_to_refresh
-          attribute \src "ls180.v:2711.8-2711.27"
+          attribute \src "ls180.v:2696.8-2696.27"
           case 1'1
             assign $0\subfragments_multiplexer_next_state[2:0] 3'010
           case 
@@ -264629,18 +264201,18 @@ module \ls180
       case 3'010
         assign $0\sdram_steerer_sel[1:0] 2'11
         assign $0\sdram_cmd_ready[0:0] 1'1
-        attribute \src "ls180.v:2718.4-2720.7"
+        attribute \src "ls180.v:2703.4-2705.7"
         switch \sdram_cmd_last
-          attribute \src "ls180.v:2718.8-2718.22"
+          attribute \src "ls180.v:2703.8-2703.22"
           case 1'1
             assign $0\subfragments_multiplexer_next_state[2:0] 3'000
           case 
         end
       attribute \src "ls180.v:0.0-0.0"
       case 3'011
-        attribute \src "ls180.v:2723.4-2725.7"
+        attribute \src "ls180.v:2708.4-2710.7"
         switch \sdram_twtrcon_ready
-          attribute \src "ls180.v:2723.8-2723.27"
+          attribute \src "ls180.v:2708.8-2708.27"
           case 1'1
             assign $0\subfragments_multiplexer_next_state[2:0] 3'000
           case 
@@ -264656,29 +264228,29 @@ module \ls180
         assign $0\sdram_en0[0:0] 1'1
         assign $0\sdram_choose_req_want_reads[0:0] 1'1
         assign $0\sdram_steerer_sel[1:0] 2'10
-        attribute \src "ls180.v:2736.4-2742.7"
+        attribute \src "ls180.v:2721.4-2727.7"
         switch 1'1
-          attribute \src "ls180.v:2736.8-2736.12"
+          attribute \src "ls180.v:2721.8-2721.12"
           case 1'1
-            assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2737$445_Y
+            assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2722$413_Y
           case 
         end
-        attribute \src "ls180.v:2744.4-2748.7"
+        attribute \src "ls180.v:2729.4-2733.7"
         switch \sdram_write_available
-          attribute \src "ls180.v:2744.8-2744.29"
+          attribute \src "ls180.v:2729.8-2729.29"
           case 1'1
-            attribute \src "ls180.v:2745.5-2747.8"
-            switch $or$ls180.v:2745$447_Y
-              attribute \src "ls180.v:2745.9-2745.52"
+            attribute \src "ls180.v:2730.5-2732.8"
+            switch $or$ls180.v:2730$415_Y
+              attribute \src "ls180.v:2730.9-2730.52"
               case 1'1
                 assign $0\subfragments_multiplexer_next_state[2:0] 3'100
               case 
             end
           case 
         end
-        attribute \src "ls180.v:2749.4-2751.7"
+        attribute \src "ls180.v:2734.4-2736.7"
         switch \sdram_go_to_refresh
-          attribute \src "ls180.v:2749.8-2749.27"
+          attribute \src "ls180.v:2734.8-2734.27"
           case 1'1
             assign $0\subfragments_multiplexer_next_state[2:0] 3'010
           case 
@@ -264695,32 +264267,72 @@ module \ls180
       update \sdram_en1 $0\sdram_en1[0:0]
       update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0]
   end
-  attribute \src "ls180.v:2778.1-2791.4"
-  process $proc$ls180.v:2778$576
-    assign { } { }
+  attribute \src "ls180.v:268.5-268.31"
+  process $proc$ls180.v:268$1635
     assign { } { }
-    assign $0\sdram_interface_wdata[15:0] 16'0000000000000000
-    assign $0\sdram_interface_wdata_we[1:0] 2'00
-    attribute \src "ls180.v:2781.2-2790.9"
-    switch \subfragments_new_master_wdata_ready
-      attribute \src "ls180.v:0.0-0.0"
-      case 1'1
-        assign $0\sdram_interface_wdata[15:0] \port_wdata_payload_data
-        assign $0\sdram_interface_wdata_we[1:0] \port_wdata_payload_we
-      attribute \src "ls180.v:0.0-0.0"
-      case 
-        assign $0\sdram_interface_wdata[15:0] 16'0000000000000000
-        assign $0\sdram_interface_wdata_we[1:0] 2'00
-    end
+    assign $1\sdram_inti_p0_cas_n[0:0] 1'1
     sync always
-      update \sdram_interface_wdata $0\sdram_interface_wdata[15:0]
-      update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0]
-  end
-  attribute \src "ls180.v:2798.1-2808.4"
-  process $proc$ls180.v:2798$578
+    sync init
+      update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0]
+  end
+  attribute \src "ls180.v:269.5-269.30"
+  process $proc$ls180.v:269$1636
+    assign { } { }
+    assign $1\sdram_inti_p0_cs_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0]
+  end
+  attribute \src "ls180.v:270.5-270.31"
+  process $proc$ls180.v:270$1637
+    assign { } { }
+    assign $1\sdram_inti_p0_ras_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0]
+  end
+  attribute \src "ls180.v:271.5-271.30"
+  process $proc$ls180.v:271$1638
+    assign { } { }
+    assign $1\sdram_inti_p0_we_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0]
+  end
+  attribute \src "ls180.v:275.5-275.31"
+  process $proc$ls180.v:275$1639
+    assign { } { }
+    assign $0\sdram_inti_p0_act_n[0:0] 1'1
+    sync always
+      update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:2763.1-2776.4"
+  process $proc$ls180.v:2763$544
+    assign { } { }
+    assign { } { }
+    assign $0\sdram_interface_wdata_we[1:0] 2'00
+    assign $0\sdram_interface_wdata[15:0] 16'0000000000000000
+    attribute \src "ls180.v:2766.2-2775.9"
+    switch \subfragments_new_master_wdata_ready
+      attribute \src "ls180.v:0.0-0.0"
+      case 1'1
+        assign $0\sdram_interface_wdata[15:0] \port_wdata_payload_data
+        assign $0\sdram_interface_wdata_we[1:0] \port_wdata_payload_we
+      attribute \src "ls180.v:0.0-0.0"
+      case 
+        assign $0\sdram_interface_wdata[15:0] 16'0000000000000000
+        assign $0\sdram_interface_wdata_we[1:0] 2'00
+    end
+    sync always
+      update \sdram_interface_wdata $0\sdram_interface_wdata[15:0]
+      update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0]
+  end
+  attribute \src "ls180.v:2783.1-2793.4"
+  process $proc$ls180.v:2783$546
     assign { } { }
     assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000
-    attribute \src "ls180.v:2800.2-2807.9"
+    attribute \src "ls180.v:2785.2-2792.9"
     switch \converter_counter
       attribute \src "ls180.v:0.0-0.0"
       case 1'0
@@ -264733,8 +264345,8 @@ module \ls180
     sync always
       update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0]
   end
-  attribute \src "ls180.v:2810.1-2856.4"
-  process $proc$ls180.v:2810$579
+  attribute \src "ls180.v:2795.1-2841.4"
+  process $proc$ls180.v:2795$547
     assign { } { }
     assign { } { }
     assign { } { }
@@ -264745,23 +264357,23 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign { } { }
-    assign $0\converter_counter_subfragments_next_value[0:0] 1'0
-    assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0
-    assign $0\wb_sdram_ack[0:0] 1'0
     assign $0\litedram_wb_adr[29:0] 30'000000000000000000000000000000
     assign $0\litedram_wb_sel[1:0] 2'00
     assign $0\litedram_wb_cyc[0:0] 1'0
     assign $0\litedram_wb_stb[0:0] 1'0
     assign $0\litedram_wb_we[0:0] 1'0
+    assign $0\wb_sdram_ack[0:0] 1'0
     assign $0\converter_skip[0:0] 1'0
+    assign { } { }
+    assign $0\converter_counter_subfragments_next_value[0:0] 1'0
+    assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0
     assign $0\subfragments_next_state[0:0] \subfragments_state
-    attribute \src "ls180.v:2822.2-2855.9"
+    attribute \src "ls180.v:2807.2-2840.9"
     switch \subfragments_state
       attribute \src "ls180.v:0.0-0.0"
       case 1'1
         assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter }
-        attribute \src "ls180.v:2825.4-2832.11"
+        attribute \src "ls180.v:2810.4-2817.11"
         switch \converter_counter
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -264771,23 +264383,23 @@ module \ls180
             assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2]
           case 
         end
-        attribute \src "ls180.v:2833.4-2846.7"
-        switch $and$ls180.v:2833$580_Y
-          attribute \src "ls180.v:2833.8-2833.37"
+        attribute \src "ls180.v:2818.4-2831.7"
+        switch $and$ls180.v:2818$548_Y
+          attribute \src "ls180.v:2818.8-2818.37"
           case 1'1
-            assign $0\converter_skip[0:0] $eq$ls180.v:2834$581_Y
+            assign $0\converter_skip[0:0] $eq$ls180.v:2819$549_Y
             assign $0\litedram_wb_we[0:0] \wb_sdram_we
-            assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2836$582_Y
-            assign $0\litedram_wb_stb[0:0] $not$ls180.v:2837$583_Y
-            attribute \src "ls180.v:2838.5-2845.8"
-            switch $or$ls180.v:2838$584_Y
-              attribute \src "ls180.v:2838.9-2838.43"
+            assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2821$550_Y
+            assign $0\litedram_wb_stb[0:0] $not$ls180.v:2822$551_Y
+            attribute \src "ls180.v:2823.5-2830.8"
+            switch $or$ls180.v:2823$552_Y
+              attribute \src "ls180.v:2823.9-2823.43"
               case 1'1
-                assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2839$585_Y
+                assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2824$553_Y
                 assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1
-                attribute \src "ls180.v:2841.6-2844.9"
-                switch $eq$ls180.v:2841$586_Y
-                  attribute \src "ls180.v:2841.10-2841.37"
+                attribute \src "ls180.v:2826.6-2829.9"
+                switch $eq$ls180.v:2826$554_Y
+                  attribute \src "ls180.v:2826.10-2826.37"
                   case 1'1
                     assign $0\wb_sdram_ack[0:0] 1'1
                     assign $0\subfragments_next_state[0:0] 1'0
@@ -264801,9 +264413,9 @@ module \ls180
       case 
         assign $0\converter_counter_subfragments_next_value[0:0] 1'0
         assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1
-        attribute \src "ls180.v:2851.4-2853.7"
-        switch $and$ls180.v:2851$587_Y
-          attribute \src "ls180.v:2851.8-2851.37"
+        attribute \src "ls180.v:2836.4-2838.7"
+        switch $and$ls180.v:2836$555_Y
+          attribute \src "ls180.v:2836.8-2836.37"
           case 1'1
             assign $0\subfragments_next_state[0:0] 1'1
           case 
@@ -264821,77 +264433,29 @@ module \ls180
       update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0]
       update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0]
   end
-  attribute \src "ls180.v:283.12-283.41"
-  process $proc$ls180.v:283$1711
-    assign { } { }
-    assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0]
-  end
-  attribute \src "ls180.v:284.5-284.39"
-  process $proc$ls180.v:284$1712
-    assign { } { }
-    assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0]
-  end
-  attribute \src "ls180.v:285.12-285.43"
-  process $proc$ls180.v:285$1713
-    assign { } { }
-    assign $1\sdram_master_p0_address[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \sdram_master_p0_address $1\sdram_master_p0_address[12:0]
-  end
-  attribute \src "ls180.v:286.11-286.38"
-  process $proc$ls180.v:286$1714
-    assign { } { }
-    assign $1\sdram_master_p0_bank[1:0] 2'00
-    sync always
-    sync init
-      update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0]
-  end
-  attribute \src "ls180.v:287.5-287.33"
-  process $proc$ls180.v:287$1715
-    assign { } { }
-    assign $1\sdram_master_p0_cas_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0]
-  end
-  attribute \src "ls180.v:288.5-288.32"
-  process $proc$ls180.v:288$1716
+  attribute \src "ls180.v:280.12-280.40"
+  process $proc$ls180.v:280$1640
     assign { } { }
-    assign $1\sdram_master_p0_cs_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0]
-  end
-  attribute \src "ls180.v:289.5-289.33"
-  process $proc$ls180.v:289$1717
-    assign { } { }
-    assign $1\sdram_master_p0_ras_n[0:0] 1'1
+    assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0]
+      update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0]
   end
-  attribute \src "ls180.v:290.5-290.32"
-  process $proc$ls180.v:290$1718
+  attribute \src "ls180.v:281.5-281.38"
+  process $proc$ls180.v:281$1641
     assign { } { }
-    assign $1\sdram_master_p0_we_n[0:0] 1'1
+    assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0
     sync always
     sync init
-      update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0]
+      update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0]
   end
-  attribute \src "ls180.v:2901.1-2906.4"
-  process $proc$ls180.v:2901$619
+  attribute \src "ls180.v:2886.1-2891.4"
+  process $proc$ls180.v:2886$587
     assign { } { }
     assign $0\tx_clear[0:0] 1'0
-    attribute \src "ls180.v:2903.2-2905.5"
-    switch $and$ls180.v:2903$620_Y
-      attribute \src "ls180.v:2903.6-2903.59"
+    attribute \src "ls180.v:2888.2-2890.5"
+    switch $and$ls180.v:2888$588_Y
+      attribute \src "ls180.v:2888.6-2888.59"
       case 1'1
         assign $0\tx_clear[0:0] 1'1
       case 
@@ -264899,8 +264463,8 @@ module \ls180
     sync always
       update \tx_clear $0\tx_clear[0:0]
   end
-  attribute \src "ls180.v:2907.1-2911.4"
-  process $proc$ls180.v:2907$621
+  attribute \src "ls180.v:2892.1-2896.4"
+  process $proc$ls180.v:2892$589
     assign { } { }
     assign { } { }
     assign $0\eventmanager_status_w[1:0] [0] \tx_status
@@ -264908,21 +264472,13 @@ module \ls180
     sync always
       update \eventmanager_status_w $0\eventmanager_status_w[1:0]
   end
-  attribute \src "ls180.v:291.5-291.31"
-  process $proc$ls180.v:291$1719
-    assign { } { }
-    assign $1\sdram_master_p0_cke[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0]
-  end
-  attribute \src "ls180.v:2912.1-2917.4"
-  process $proc$ls180.v:2912$622
+  attribute \src "ls180.v:2897.1-2902.4"
+  process $proc$ls180.v:2897$590
     assign { } { }
     assign $0\rx_clear[0:0] 1'0
-    attribute \src "ls180.v:2914.2-2916.5"
-    switch $and$ls180.v:2914$623_Y
-      attribute \src "ls180.v:2914.6-2914.59"
+    attribute \src "ls180.v:2899.2-2901.5"
+    switch $and$ls180.v:2899$591_Y
+      attribute \src "ls180.v:2899.6-2899.59"
       case 1'1
         assign $0\rx_clear[0:0] 1'1
       case 
@@ -264930,8 +264486,8 @@ module \ls180
     sync always
       update \rx_clear $0\rx_clear[0:0]
   end
-  attribute \src "ls180.v:2918.1-2922.4"
-  process $proc$ls180.v:2918$624
+  attribute \src "ls180.v:2903.1-2907.4"
+  process $proc$ls180.v:2903$592
     assign { } { }
     assign { } { }
     assign $0\eventmanager_pending_w[1:0] [0] \tx_pending
@@ -264939,96 +264495,56 @@ module \ls180
     sync always
       update \eventmanager_pending_w $0\eventmanager_pending_w[1:0]
   end
-  attribute \src "ls180.v:292.5-292.31"
-  process $proc$ls180.v:292$1720
-    assign { } { }
-    assign $1\sdram_master_p0_odt[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0]
-  end
-  attribute \src "ls180.v:293.5-293.35"
-  process $proc$ls180.v:293$1721
-    assign { } { }
-    assign $1\sdram_master_p0_reset_n[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0]
-  end
-  attribute \src "ls180.v:294.5-294.33"
-  process $proc$ls180.v:294$1722
-    assign { } { }
-    assign $1\sdram_master_p0_act_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0]
-  end
-  attribute \src "ls180.v:2940.1-2947.4"
-  process $proc$ls180.v:2940$632
+  attribute \src "ls180.v:2925.1-2932.4"
+  process $proc$ls180.v:2925$600
     assign { } { }
     assign $0\tx_fifo_wrport_adr[3:0] 4'0000
-    attribute \src "ls180.v:2942.2-2946.5"
+    attribute \src "ls180.v:2927.2-2931.5"
     switch \tx_fifo_replace
-      attribute \src "ls180.v:2942.6-2942.21"
+      attribute \src "ls180.v:2927.6-2927.21"
       case 1'1
-        assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2943$633_Y
-      attribute \src "ls180.v:2944.6-2944.10"
+        assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2928$601_Y
+      attribute \src "ls180.v:2929.6-2929.10"
       case 
         assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce
     end
     sync always
       update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:295.12-295.42"
-  process $proc$ls180.v:295$1723
-    assign { } { }
-    assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0]
-  end
-  attribute \src "ls180.v:296.5-296.37"
-  process $proc$ls180.v:296$1724
-    assign { } { }
-    assign $1\sdram_master_p0_wrdata_en[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0]
-  end
-  attribute \src "ls180.v:297.11-297.45"
-  process $proc$ls180.v:297$1725
-    assign { } { }
-    assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00
-    sync always
-    sync init
-      update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0]
-  end
-  attribute \src "ls180.v:2970.1-2977.4"
-  process $proc$ls180.v:2970$643
+  attribute \src "ls180.v:2955.1-2962.4"
+  process $proc$ls180.v:2955$611
     assign { } { }
     assign $0\rx_fifo_wrport_adr[3:0] 4'0000
-    attribute \src "ls180.v:2972.2-2976.5"
+    attribute \src "ls180.v:2957.2-2961.5"
     switch \rx_fifo_replace
-      attribute \src "ls180.v:2972.6-2972.21"
+      attribute \src "ls180.v:2957.6-2957.21"
       case 1'1
-        assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2973$644_Y
-      attribute \src "ls180.v:2974.6-2974.10"
+        assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2958$612_Y
+      attribute \src "ls180.v:2959.6-2959.10"
       case 
         assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce
     end
     sync always
       update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:298.5-298.37"
-  process $proc$ls180.v:298$1726
+  attribute \src "ls180.v:296.12-296.41"
+  process $proc$ls180.v:296$1642
     assign { } { }
-    assign $1\sdram_master_p0_rddata_en[0:0] 1'0
+    assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0]
+      update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0]
   end
-  attribute \src "ls180.v:2986.1-2996.4"
-  process $proc$ls180.v:2986$650
+  attribute \src "ls180.v:297.5-297.39"
+  process $proc$ls180.v:297$1643
+    assign { } { }
+    assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0]
+  end
+  attribute \src "ls180.v:2971.1-2981.4"
+  process $proc$ls180.v:2971$618
     assign { } { }
     assign { } { }
     assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [0]
@@ -265042,8 +264558,16 @@ module \ls180
     sync always
       update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0]
   end
-  attribute \src "ls180.v:2997.1-3007.4"
-  process $proc$ls180.v:2997$651
+  attribute \src "ls180.v:298.12-298.43"
+  process $proc$ls180.v:298$1644
+    assign { } { }
+    assign $1\sdram_master_p0_address[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \sdram_master_p0_address $1\sdram_master_p0_address[12:0]
+  end
+  attribute \src "ls180.v:2982.1-2992.4"
+  process $proc$ls180.v:2982$619
     assign { } { }
     assign { } { }
     assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [8]
@@ -265057,8 +264581,16 @@ module \ls180
     sync always
       update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0]
   end
-  attribute \src "ls180.v:3008.1-3026.4"
-  process $proc$ls180.v:3008$652
+  attribute \src "ls180.v:299.11-299.38"
+  process $proc$ls180.v:299$1645
+    assign { } { }
+    assign $1\sdram_master_p0_bank[1:0] 2'00
+    sync always
+    sync init
+      update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0]
+  end
+  attribute \src "ls180.v:2993.1-3011.4"
+  process $proc$ls180.v:2993$620
     assign { } { }
     assign { } { }
     assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0]
@@ -265080,8 +264612,24 @@ module \ls180
     sync always
       update \libresocsim_libresoc_constraintmanager_gpio_o $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
   end
-  attribute \src "ls180.v:3027.1-3045.4"
-  process $proc$ls180.v:3027$653
+  attribute \src "ls180.v:300.5-300.33"
+  process $proc$ls180.v:300$1646
+    assign { } { }
+    assign $1\sdram_master_p0_cas_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0]
+  end
+  attribute \src "ls180.v:301.5-301.32"
+  process $proc$ls180.v:301$1647
+    assign { } { }
+    assign $1\sdram_master_p0_cs_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0]
+  end
+  attribute \src "ls180.v:3012.1-3030.4"
+  process $proc$ls180.v:3012$621
     assign { } { }
     assign { } { }
     assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0]
@@ -265103,17 +264651,24 @@ module \ls180
     sync always
       update \libresocsim_libresoc_constraintmanager_gpio_oe $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
   end
-  attribute \src "ls180.v:305.11-305.31"
-  process $proc$ls180.v:305$1727
+  attribute \src "ls180.v:302.5-302.33"
+  process $proc$ls180.v:302$1648
     assign { } { }
-    assign $1\sdram_storage[3:0] 4'0001
+    assign $1\sdram_master_p0_ras_n[0:0] 1'1
     sync always
     sync init
-      update \sdram_storage $1\sdram_storage[3:0]
+      update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0]
   end
-  attribute \src "ls180.v:3050.1-3086.4"
-  process $proc$ls180.v:3050$654
+  attribute \src "ls180.v:303.5-303.32"
+  process $proc$ls180.v:303$1649
     assign { } { }
+    assign $1\sdram_master_p0_we_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0]
+  end
+  attribute \src "ls180.v:3035.1-3071.4"
+  process $proc$ls180.v:3035$622
     assign { } { }
     assign { } { }
     assign { } { }
@@ -265122,9 +264677,10 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
+    assign { } { }
+    assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0
     assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0
     assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0
-    assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0
     assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'0
     assign { } { }
     assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000
@@ -265132,7 +264688,7 @@ module \ls180
     assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000
     assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0
     assign $0\libresocsim_next_state[1:0] \libresocsim_state
-    attribute \src "ls180.v:3061.2-3085.9"
+    attribute \src "ls180.v:3046.2-3070.9"
     switch \libresocsim_state
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
@@ -265150,13 +264706,13 @@ module \ls180
       case 
         assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0]
         assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1
-        attribute \src "ls180.v:3077.4-3083.7"
-        switch $and$ls180.v:3077$655_Y
-          attribute \src "ls180.v:3077.8-3077.85"
+        attribute \src "ls180.v:3062.4-3068.7"
+        switch $and$ls180.v:3062$623_Y
+          attribute \src "ls180.v:3062.8-3062.85"
           case 1'1
             assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0]
             assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1
-            assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3080$657_Y
+            assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3065$625_Y
             assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1
             assign $0\libresocsim_next_state[1:0] 2'01
           case 
@@ -265173,96 +264729,96 @@ module \ls180
       update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
       update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
   end
-  attribute \src "ls180.v:306.5-306.20"
-  process $proc$ls180.v:306$1728
+  attribute \src "ls180.v:304.5-304.31"
+  process $proc$ls180.v:304$1650
     assign { } { }
-    assign $1\sdram_re[0:0] 1'0
+    assign $1\sdram_master_p0_cke[0:0] 1'0
     sync always
     sync init
-      update \sdram_re $1\sdram_re[0:0]
+      update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0]
   end
-  attribute \src "ls180.v:307.11-307.39"
-  process $proc$ls180.v:307$1729
+  attribute \src "ls180.v:305.5-305.31"
+  process $proc$ls180.v:305$1651
     assign { } { }
-    assign $1\sdram_command_storage[5:0] 6'000000
+    assign $1\sdram_master_p0_odt[0:0] 1'0
     sync always
     sync init
-      update \sdram_command_storage $1\sdram_command_storage[5:0]
+      update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0]
   end
-  attribute \src "ls180.v:308.5-308.28"
-  process $proc$ls180.v:308$1730
+  attribute \src "ls180.v:306.5-306.35"
+  process $proc$ls180.v:306$1652
     assign { } { }
-    assign $1\sdram_command_re[0:0] 1'0
+    assign $1\sdram_master_p0_reset_n[0:0] 1'0
     sync always
     sync init
-      update \sdram_command_re $1\sdram_command_re[0:0]
+      update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0]
   end
-  attribute \src "ls180.v:3105.1-3113.4"
-  process $proc$ls180.v:3105$670
-    assign { } { }
+  attribute \src "ls180.v:307.5-307.33"
+  process $proc$ls180.v:307$1653
     assign { } { }
-    assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3107$671_Y
-    assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3108$672_Y
-    assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3109$673_Y
-    assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3110$674_Y
-    assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3111$675_Y
-    assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3112$676_Y
+    assign $1\sdram_master_p0_act_n[0:0] 1'1
     sync always
-      update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0]
+    sync init
+      update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0]
   end
-  attribute \src "ls180.v:312.5-312.33"
-  process $proc$ls180.v:312$1731
+  attribute \src "ls180.v:308.12-308.42"
+  process $proc$ls180.v:308$1654
     assign { } { }
-    assign $0\sdram_command_issue_w[0:0] 1'0
+    assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000
     sync always
-      update \sdram_command_issue_w $0\sdram_command_issue_w[0:0]
     sync init
+      update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0]
   end
-  attribute \src "ls180.v:313.12-313.41"
-  process $proc$ls180.v:313$1732
+  attribute \src "ls180.v:309.5-309.37"
+  process $proc$ls180.v:309$1655
     assign { } { }
-    assign $1\sdram_address_storage[12:0] 13'0000000000000
+    assign $1\sdram_master_p0_wrdata_en[0:0] 1'0
     sync always
     sync init
-      update \sdram_address_storage $1\sdram_address_storage[12:0]
+      update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0]
   end
-  attribute \src "ls180.v:314.5-314.28"
-  process $proc$ls180.v:314$1733
+  attribute \src "ls180.v:3090.1-3098.4"
+  process $proc$ls180.v:3090$638
     assign { } { }
-    assign $1\sdram_address_re[0:0] 1'0
+    assign { } { }
+    assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3092$639_Y
+    assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3093$640_Y
+    assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3094$641_Y
+    assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3095$642_Y
+    assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3096$643_Y
+    assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3097$644_Y
     sync always
-    sync init
-      update \sdram_address_re $1\sdram_address_re[0:0]
+      update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0]
   end
-  attribute \src "ls180.v:315.11-315.40"
-  process $proc$ls180.v:315$1734
+  attribute \src "ls180.v:310.11-310.45"
+  process $proc$ls180.v:310$1656
     assign { } { }
-    assign $1\sdram_baddress_storage[1:0] 2'00
+    assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00
     sync always
     sync init
-      update \sdram_baddress_storage $1\sdram_baddress_storage[1:0]
+      update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0]
   end
-  attribute \src "ls180.v:316.5-316.29"
-  process $proc$ls180.v:316$1735
+  attribute \src "ls180.v:311.5-311.37"
+  process $proc$ls180.v:311$1657
     assign { } { }
-    assign $1\sdram_baddress_re[0:0] 1'0
+    assign $1\sdram_master_p0_rddata_en[0:0] 1'0
     sync always
     sync init
-      update \sdram_baddress_re $1\sdram_baddress_re[0:0]
+      update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0]
   end
-  attribute \src "ls180.v:3164.1-3175.4"
-  process $proc$ls180.v:3164$691
+  attribute \src "ls180.v:3149.1-3160.4"
+  process $proc$ls180.v:3149$659
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\libresocsim_error[0:0] 1'0
     assign { } { }
     assign { } { }
-    assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3168$696_Y
-    assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3169$707_Y [31:0]
-    attribute \src "ls180.v:3170.2-3174.5"
+    assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3153$664_Y
+    assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3154$675_Y
+    attribute \src "ls180.v:3155.2-3159.5"
     switch \libresocsim_done
-      attribute \src "ls180.v:3170.6-3170.22"
+      attribute \src "ls180.v:3155.6-3155.22"
       case 1'1
         assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111
         assign $0\libresocsim_shared_ack[0:0] 1'1
@@ -265274,35 +264830,107 @@ module \ls180
       update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0]
       update \libresocsim_error $0\libresocsim_error[0:0]
   end
-  attribute \src "ls180.v:317.12-317.40"
-  process $proc$ls180.v:317$1736
+  attribute \src "ls180.v:318.11-318.31"
+  process $proc$ls180.v:318$1658
+    assign { } { }
+    assign $1\sdram_storage[3:0] 4'0001
+    sync always
+    sync init
+      update \sdram_storage $1\sdram_storage[3:0]
+  end
+  attribute \src "ls180.v:319.5-319.20"
+  process $proc$ls180.v:319$1659
+    assign { } { }
+    assign $1\sdram_re[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_re $1\sdram_re[0:0]
+  end
+  attribute \src "ls180.v:320.11-320.39"
+  process $proc$ls180.v:320$1660
+    assign { } { }
+    assign $1\sdram_command_storage[5:0] 6'000000
+    sync always
+    sync init
+      update \sdram_command_storage $1\sdram_command_storage[5:0]
+  end
+  attribute \src "ls180.v:321.5-321.28"
+  process $proc$ls180.v:321$1661
+    assign { } { }
+    assign $1\sdram_command_re[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_command_re $1\sdram_command_re[0:0]
+  end
+  attribute \src "ls180.v:325.5-325.33"
+  process $proc$ls180.v:325$1662
+    assign { } { }
+    assign $0\sdram_command_issue_w[0:0] 1'0
+    sync always
+      update \sdram_command_issue_w $0\sdram_command_issue_w[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:326.12-326.41"
+  process $proc$ls180.v:326$1663
+    assign { } { }
+    assign $1\sdram_address_storage[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \sdram_address_storage $1\sdram_address_storage[12:0]
+  end
+  attribute \src "ls180.v:327.5-327.28"
+  process $proc$ls180.v:327$1664
+    assign { } { }
+    assign $1\sdram_address_re[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_address_re $1\sdram_address_re[0:0]
+  end
+  attribute \src "ls180.v:328.11-328.40"
+  process $proc$ls180.v:328$1665
+    assign { } { }
+    assign $1\sdram_baddress_storage[1:0] 2'00
+    sync always
+    sync init
+      update \sdram_baddress_storage $1\sdram_baddress_storage[1:0]
+  end
+  attribute \src "ls180.v:329.5-329.29"
+  process $proc$ls180.v:329$1666
+    assign { } { }
+    assign $1\sdram_baddress_re[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_baddress_re $1\sdram_baddress_re[0:0]
+  end
+  attribute \src "ls180.v:330.12-330.40"
+  process $proc$ls180.v:330$1667
     assign { } { }
     assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000
     sync always
     sync init
       update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0]
   end
-  attribute \src "ls180.v:318.5-318.27"
-  process $proc$ls180.v:318$1737
+  attribute \src "ls180.v:331.5-331.27"
+  process $proc$ls180.v:331$1668
     assign { } { }
     assign $1\sdram_wrdata_re[0:0] 1'0
     sync always
     sync init
       update \sdram_wrdata_re $1\sdram_wrdata_re[0:0]
   end
-  attribute \src "ls180.v:319.12-319.32"
-  process $proc$ls180.v:319$1738
+  attribute \src "ls180.v:332.12-332.32"
+  process $proc$ls180.v:332$1669
     assign { } { }
     assign $1\sdram_status[15:0] 16'0000000000000000
     sync always
     sync init
       update \sdram_status $1\sdram_status[15:0]
   end
-  attribute \src "ls180.v:3450.1-3466.4"
-  process $proc$ls180.v:3450$1116
+  attribute \src "ls180.v:3435.1-3451.4"
+  process $proc$ls180.v:3435$1084
     assign { } { }
     assign $0\rhs_array_muxed0[0:0] 1'0
-    attribute \src "ls180.v:3452.2-3465.9"
+    attribute \src "ls180.v:3437.2-3450.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265320,11 +264948,11 @@ module \ls180
     sync always
       update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:3467.1-3483.4"
-  process $proc$ls180.v:3467$1117
+  attribute \src "ls180.v:3452.1-3468.4"
+  process $proc$ls180.v:3452$1085
     assign { } { }
     assign $0\rhs_array_muxed1[12:0] 13'0000000000000
-    attribute \src "ls180.v:3469.2-3482.9"
+    attribute \src "ls180.v:3454.2-3467.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265342,11 +264970,11 @@ module \ls180
     sync always
       update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0]
   end
-  attribute \src "ls180.v:3484.1-3500.4"
-  process $proc$ls180.v:3484$1118
+  attribute \src "ls180.v:3469.1-3485.4"
+  process $proc$ls180.v:3469$1086
     assign { } { }
     assign $0\rhs_array_muxed2[1:0] 2'00
-    attribute \src "ls180.v:3486.2-3499.9"
+    attribute \src "ls180.v:3471.2-3484.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265364,27 +264992,11 @@ module \ls180
     sync always
       update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0]
   end
-  attribute \src "ls180.v:349.12-349.41"
-  process $proc$ls180.v:349$1739
-    assign { } { }
-    assign $1\sdram_interface_wdata[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \sdram_interface_wdata $1\sdram_interface_wdata[15:0]
-  end
-  attribute \src "ls180.v:350.11-350.42"
-  process $proc$ls180.v:350$1740
-    assign { } { }
-    assign $1\sdram_interface_wdata_we[1:0] 2'00
-    sync always
-    sync init
-      update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0]
-  end
-  attribute \src "ls180.v:3501.1-3517.4"
-  process $proc$ls180.v:3501$1119
+  attribute \src "ls180.v:3486.1-3502.4"
+  process $proc$ls180.v:3486$1087
     assign { } { }
     assign $0\rhs_array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:3503.2-3516.9"
+    attribute \src "ls180.v:3488.2-3501.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265402,11 +265014,11 @@ module \ls180
     sync always
       update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:3518.1-3534.4"
-  process $proc$ls180.v:3518$1120
+  attribute \src "ls180.v:3503.1-3519.4"
+  process $proc$ls180.v:3503$1088
     assign { } { }
     assign $0\rhs_array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:3520.2-3533.9"
+    attribute \src "ls180.v:3505.2-3518.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265424,27 +265036,11 @@ module \ls180
     sync always
       update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:352.12-352.40"
-  process $proc$ls180.v:352$1741
-    assign { } { }
-    assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0]
-  end
-  attribute \src "ls180.v:353.11-353.35"
-  process $proc$ls180.v:353$1742
-    assign { } { }
-    assign $1\sdram_dfi_p0_bank[1:0] 2'00
-    sync always
-    sync init
-      update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0]
-  end
-  attribute \src "ls180.v:3535.1-3551.4"
-  process $proc$ls180.v:3535$1121
+  attribute \src "ls180.v:3520.1-3536.4"
+  process $proc$ls180.v:3520$1089
     assign { } { }
     assign $0\rhs_array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:3537.2-3550.9"
+    attribute \src "ls180.v:3522.2-3535.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265462,27 +265058,11 @@ module \ls180
     sync always
       update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:354.5-354.30"
-  process $proc$ls180.v:354$1743
-    assign { } { }
-    assign $1\sdram_dfi_p0_cas_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0]
-  end
-  attribute \src "ls180.v:355.5-355.29"
-  process $proc$ls180.v:355$1744
-    assign { } { }
-    assign $1\sdram_dfi_p0_cs_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0]
-  end
-  attribute \src "ls180.v:3552.1-3568.4"
-  process $proc$ls180.v:3552$1122
+  attribute \src "ls180.v:3537.1-3553.4"
+  process $proc$ls180.v:3537$1090
     assign { } { }
     assign $0\t_array_muxed0[0:0] 1'0
-    attribute \src "ls180.v:3554.2-3567.9"
+    attribute \src "ls180.v:3539.2-3552.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265500,19 +265080,11 @@ module \ls180
     sync always
       update \t_array_muxed0 $0\t_array_muxed0[0:0]
   end
-  attribute \src "ls180.v:356.5-356.30"
-  process $proc$ls180.v:356$1745
-    assign { } { }
-    assign $1\sdram_dfi_p0_ras_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0]
-  end
-  attribute \src "ls180.v:3569.1-3585.4"
-  process $proc$ls180.v:3569$1123
+  attribute \src "ls180.v:3554.1-3570.4"
+  process $proc$ls180.v:3554$1091
     assign { } { }
     assign $0\t_array_muxed1[0:0] 1'0
-    attribute \src "ls180.v:3571.2-3584.9"
+    attribute \src "ls180.v:3556.2-3569.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265530,19 +265102,11 @@ module \ls180
     sync always
       update \t_array_muxed1 $0\t_array_muxed1[0:0]
   end
-  attribute \src "ls180.v:357.5-357.29"
-  process $proc$ls180.v:357$1746
-    assign { } { }
-    assign $1\sdram_dfi_p0_we_n[0:0] 1'1
-    sync always
-    sync init
-      update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0]
-  end
-  attribute \src "ls180.v:3586.1-3602.4"
-  process $proc$ls180.v:3586$1124
+  attribute \src "ls180.v:3571.1-3587.4"
+  process $proc$ls180.v:3571$1092
     assign { } { }
     assign $0\t_array_muxed2[0:0] 1'0
-    attribute \src "ls180.v:3588.2-3601.9"
+    attribute \src "ls180.v:3573.2-3586.9"
     switch \sdram_choose_cmd_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265560,11 +265124,11 @@ module \ls180
     sync always
       update \t_array_muxed2 $0\t_array_muxed2[0:0]
   end
-  attribute \src "ls180.v:3603.1-3619.4"
-  process $proc$ls180.v:3603$1125
+  attribute \src "ls180.v:3588.1-3604.4"
+  process $proc$ls180.v:3588$1093
     assign { } { }
     assign $0\rhs_array_muxed6[0:0] 1'0
-    attribute \src "ls180.v:3605.2-3618.9"
+    attribute \src "ls180.v:3590.2-3603.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265582,19 +265146,11 @@ module \ls180
     sync always
       update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0]
   end
-  attribute \src "ls180.v:361.5-361.30"
-  process $proc$ls180.v:361$1747
-    assign { } { }
-    assign $0\sdram_dfi_p0_act_n[0:0] 1'1
-    sync always
-      update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:3620.1-3636.4"
-  process $proc$ls180.v:3620$1126
+  attribute \src "ls180.v:3605.1-3621.4"
+  process $proc$ls180.v:3605$1094
     assign { } { }
     assign $0\rhs_array_muxed7[12:0] 13'0000000000000
-    attribute \src "ls180.v:3622.2-3635.9"
+    attribute \src "ls180.v:3607.2-3620.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265612,19 +265168,19 @@ module \ls180
     sync always
       update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0]
   end
-  attribute \src "ls180.v:363.5-363.34"
-  process $proc$ls180.v:363$1748
+  attribute \src "ls180.v:362.12-362.41"
+  process $proc$ls180.v:362$1670
     assign { } { }
-    assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0
+    assign $1\sdram_interface_wdata[15:0] 16'0000000000000000
     sync always
     sync init
-      update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0]
+      update \sdram_interface_wdata $1\sdram_interface_wdata[15:0]
   end
-  attribute \src "ls180.v:3637.1-3653.4"
-  process $proc$ls180.v:3637$1127
+  attribute \src "ls180.v:3622.1-3638.4"
+  process $proc$ls180.v:3622$1095
     assign { } { }
     assign $0\rhs_array_muxed8[1:0] 2'00
-    attribute \src "ls180.v:3639.2-3652.9"
+    attribute \src "ls180.v:3624.2-3637.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265642,19 +265198,19 @@ module \ls180
     sync always
       update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0]
   end
-  attribute \src "ls180.v:365.5-365.34"
-  process $proc$ls180.v:365$1749
+  attribute \src "ls180.v:363.11-363.42"
+  process $proc$ls180.v:363$1671
     assign { } { }
-    assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0
+    assign $1\sdram_interface_wdata_we[1:0] 2'00
     sync always
     sync init
-      update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0]
+      update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0]
   end
-  attribute \src "ls180.v:3654.1-3670.4"
-  process $proc$ls180.v:3654$1128
+  attribute \src "ls180.v:3639.1-3655.4"
+  process $proc$ls180.v:3639$1096
     assign { } { }
     assign $0\rhs_array_muxed9[0:0] 1'0
-    attribute \src "ls180.v:3656.2-3669.9"
+    attribute \src "ls180.v:3641.2-3654.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265672,11 +265228,19 @@ module \ls180
     sync always
       update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0]
   end
-  attribute \src "ls180.v:3671.1-3687.4"
-  process $proc$ls180.v:3671$1129
+  attribute \src "ls180.v:365.12-365.40"
+  process $proc$ls180.v:365$1672
+    assign { } { }
+    assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0]
+  end
+  attribute \src "ls180.v:3656.1-3672.4"
+  process $proc$ls180.v:3656$1097
     assign { } { }
     assign $0\rhs_array_muxed10[0:0] 1'0
-    attribute \src "ls180.v:3673.2-3686.9"
+    attribute \src "ls180.v:3658.2-3671.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265694,19 +265258,27 @@ module \ls180
     sync always
       update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0]
   end
-  attribute \src "ls180.v:368.5-368.27"
-  process $proc$ls180.v:368$1750
+  attribute \src "ls180.v:366.11-366.35"
+  process $proc$ls180.v:366$1673
     assign { } { }
-    assign $1\sdram_cmd_valid[0:0] 1'0
+    assign $1\sdram_dfi_p0_bank[1:0] 2'00
     sync always
     sync init
-      update \sdram_cmd_valid $1\sdram_cmd_valid[0:0]
+      update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0]
+  end
+  attribute \src "ls180.v:367.5-367.30"
+  process $proc$ls180.v:367$1674
+    assign { } { }
+    assign $1\sdram_dfi_p0_cas_n[0:0] 1'1
+    sync always
+    sync init
+      update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0]
   end
-  attribute \src "ls180.v:3688.1-3704.4"
-  process $proc$ls180.v:3688$1130
+  attribute \src "ls180.v:3673.1-3689.4"
+  process $proc$ls180.v:3673$1098
     assign { } { }
     assign $0\rhs_array_muxed11[0:0] 1'0
-    attribute \src "ls180.v:3690.2-3703.9"
+    attribute \src "ls180.v:3675.2-3688.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265724,27 +265296,27 @@ module \ls180
     sync always
       update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0]
   end
-  attribute \src "ls180.v:369.5-369.27"
-  process $proc$ls180.v:369$1751
+  attribute \src "ls180.v:368.5-368.29"
+  process $proc$ls180.v:368$1675
     assign { } { }
-    assign $1\sdram_cmd_ready[0:0] 1'0
+    assign $1\sdram_dfi_p0_cs_n[0:0] 1'1
     sync always
     sync init
-      update \sdram_cmd_ready $1\sdram_cmd_ready[0:0]
+      update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0]
   end
-  attribute \src "ls180.v:370.5-370.26"
-  process $proc$ls180.v:370$1752
+  attribute \src "ls180.v:369.5-369.30"
+  process $proc$ls180.v:369$1676
     assign { } { }
-    assign $1\sdram_cmd_last[0:0] 1'0
+    assign $1\sdram_dfi_p0_ras_n[0:0] 1'1
     sync always
     sync init
-      update \sdram_cmd_last $1\sdram_cmd_last[0:0]
+      update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0]
   end
-  attribute \src "ls180.v:3705.1-3721.4"
-  process $proc$ls180.v:3705$1131
+  attribute \src "ls180.v:3690.1-3706.4"
+  process $proc$ls180.v:3690$1099
     assign { } { }
     assign $0\t_array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:3707.2-3720.9"
+    attribute \src "ls180.v:3692.2-3705.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265762,27 +265334,19 @@ module \ls180
     sync always
       update \t_array_muxed3 $0\t_array_muxed3[0:0]
   end
-  attribute \src "ls180.v:371.12-371.39"
-  process $proc$ls180.v:371$1753
-    assign { } { }
-    assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0]
-  end
-  attribute \src "ls180.v:372.11-372.38"
-  process $proc$ls180.v:372$1754
+  attribute \src "ls180.v:370.5-370.29"
+  process $proc$ls180.v:370$1677
     assign { } { }
-    assign $1\sdram_cmd_payload_ba[1:0] 2'00
+    assign $1\sdram_dfi_p0_we_n[0:0] 1'1
     sync always
     sync init
-      update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0]
+      update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0]
   end
-  attribute \src "ls180.v:3722.1-3738.4"
-  process $proc$ls180.v:3722$1132
+  attribute \src "ls180.v:3707.1-3723.4"
+  process $proc$ls180.v:3707$1100
     assign { } { }
     assign $0\t_array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:3724.2-3737.9"
+    attribute \src "ls180.v:3709.2-3722.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265800,19 +265364,11 @@ module \ls180
     sync always
       update \t_array_muxed4 $0\t_array_muxed4[0:0]
   end
-  attribute \src "ls180.v:373.5-373.33"
-  process $proc$ls180.v:373$1755
-    assign { } { }
-    assign $1\sdram_cmd_payload_cas[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0]
-  end
-  attribute \src "ls180.v:3739.1-3755.4"
-  process $proc$ls180.v:3739$1133
+  attribute \src "ls180.v:3724.1-3740.4"
+  process $proc$ls180.v:3724$1101
     assign { } { }
     assign $0\t_array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:3741.2-3754.9"
+    attribute \src "ls180.v:3726.2-3739.9"
     switch \sdram_choose_req_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -265830,27 +265386,19 @@ module \ls180
     sync always
       update \t_array_muxed5 $0\t_array_muxed5[0:0]
   end
-  attribute \src "ls180.v:374.5-374.33"
-  process $proc$ls180.v:374$1756
-    assign { } { }
-    assign $1\sdram_cmd_payload_ras[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0]
-  end
-  attribute \src "ls180.v:375.5-375.32"
-  process $proc$ls180.v:375$1757
+  attribute \src "ls180.v:374.5-374.30"
+  process $proc$ls180.v:374$1678
     assign { } { }
-    assign $1\sdram_cmd_payload_we[0:0] 1'0
+    assign $0\sdram_dfi_p0_act_n[0:0] 1'1
     sync always
+      update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0]
     sync init
-      update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:3756.1-3763.4"
-  process $proc$ls180.v:3756$1134
+  attribute \src "ls180.v:3741.1-3748.4"
+  process $proc$ls180.v:3741$1102
     assign { } { }
     assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:3758.2-3762.9"
+    attribute \src "ls180.v:3743.2-3747.9"
     switch \subfragments_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265859,19 +265407,11 @@ module \ls180
     sync always
       update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0]
   end
-  attribute \src "ls180.v:376.5-376.37"
-  process $proc$ls180.v:376$1758
-    assign { } { }
-    assign $0\sdram_cmd_payload_is_read[0:0] 1'0
-    sync always
-      update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:3764.1-3771.4"
-  process $proc$ls180.v:3764$1135
+  attribute \src "ls180.v:3749.1-3756.4"
+  process $proc$ls180.v:3749$1103
     assign { } { }
     assign $0\rhs_array_muxed13[0:0] 1'0
-    attribute \src "ls180.v:3766.2-3770.9"
+    attribute \src "ls180.v:3751.2-3755.9"
     switch \subfragments_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265880,32 +265420,32 @@ module \ls180
     sync always
       update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0]
   end
-  attribute \src "ls180.v:377.5-377.38"
-  process $proc$ls180.v:377$1759
-    assign { } { }
-    assign $0\sdram_cmd_payload_is_write[0:0] 1'0
-    sync always
-      update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:3772.1-3779.4"
-  process $proc$ls180.v:3772$1136
+  attribute \src "ls180.v:3757.1-3764.4"
+  process $proc$ls180.v:3757$1104
     assign { } { }
     assign $0\rhs_array_muxed14[0:0] 1'0
-    attribute \src "ls180.v:3774.2-3778.9"
+    attribute \src "ls180.v:3759.2-3763.9"
     switch \subfragments_roundrobin0_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3776$1149_Y
+        assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3761$1117_Y
     end
     sync always
       update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0]
   end
-  attribute \src "ls180.v:3780.1-3787.4"
-  process $proc$ls180.v:3780$1150
+  attribute \src "ls180.v:376.5-376.34"
+  process $proc$ls180.v:376$1679
+    assign { } { }
+    assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0]
+  end
+  attribute \src "ls180.v:3765.1-3772.4"
+  process $proc$ls180.v:3765$1118
     assign { } { }
     assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:3782.2-3786.9"
+    attribute \src "ls180.v:3767.2-3771.9"
     switch \subfragments_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265914,11 +265454,11 @@ module \ls180
     sync always
       update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0]
   end
-  attribute \src "ls180.v:3788.1-3795.4"
-  process $proc$ls180.v:3788$1151
+  attribute \src "ls180.v:3773.1-3780.4"
+  process $proc$ls180.v:3773$1119
     assign { } { }
     assign $0\rhs_array_muxed16[0:0] 1'0
-    attribute \src "ls180.v:3790.2-3794.9"
+    attribute \src "ls180.v:3775.2-3779.9"
     switch \subfragments_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265927,24 +265467,32 @@ module \ls180
     sync always
       update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0]
   end
-  attribute \src "ls180.v:3796.1-3803.4"
-  process $proc$ls180.v:3796$1152
+  attribute \src "ls180.v:378.5-378.34"
+  process $proc$ls180.v:378$1680
+    assign { } { }
+    assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0]
+  end
+  attribute \src "ls180.v:3781.1-3788.4"
+  process $proc$ls180.v:3781$1120
     assign { } { }
     assign $0\rhs_array_muxed17[0:0] 1'0
-    attribute \src "ls180.v:3798.2-3802.9"
+    attribute \src "ls180.v:3783.2-3787.9"
     switch \subfragments_roundrobin1_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3800$1165_Y
+        assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3785$1133_Y
     end
     sync always
       update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0]
   end
-  attribute \src "ls180.v:3804.1-3811.4"
-  process $proc$ls180.v:3804$1166
+  attribute \src "ls180.v:3789.1-3796.4"
+  process $proc$ls180.v:3789$1134
     assign { } { }
     assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:3806.2-3810.9"
+    attribute \src "ls180.v:3791.2-3795.9"
     switch \subfragments_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265953,11 +265501,11 @@ module \ls180
     sync always
       update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0]
   end
-  attribute \src "ls180.v:3812.1-3819.4"
-  process $proc$ls180.v:3812$1167
+  attribute \src "ls180.v:3797.1-3804.4"
+  process $proc$ls180.v:3797$1135
     assign { } { }
     assign $0\rhs_array_muxed19[0:0] 1'0
-    attribute \src "ls180.v:3814.2-3818.9"
+    attribute \src "ls180.v:3799.2-3803.9"
     switch \subfragments_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265966,24 +265514,32 @@ module \ls180
     sync always
       update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0]
   end
-  attribute \src "ls180.v:3820.1-3827.4"
-  process $proc$ls180.v:3820$1168
+  attribute \src "ls180.v:3805.1-3812.4"
+  process $proc$ls180.v:3805$1136
     assign { } { }
     assign $0\rhs_array_muxed20[0:0] 1'0
-    attribute \src "ls180.v:3822.2-3826.9"
+    attribute \src "ls180.v:3807.2-3811.9"
     switch \subfragments_roundrobin2_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3824$1181_Y
+        assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3809$1149_Y
     end
     sync always
       update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0]
   end
-  attribute \src "ls180.v:3828.1-3835.4"
-  process $proc$ls180.v:3828$1182
+  attribute \src "ls180.v:381.5-381.27"
+  process $proc$ls180.v:381$1681
+    assign { } { }
+    assign $1\sdram_cmd_valid[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_cmd_valid $1\sdram_cmd_valid[0:0]
+  end
+  attribute \src "ls180.v:3813.1-3820.4"
+  process $proc$ls180.v:3813$1150
     assign { } { }
     assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000
-    attribute \src "ls180.v:3830.2-3834.9"
+    attribute \src "ls180.v:3815.2-3819.9"
     switch \subfragments_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -265992,19 +265548,19 @@ module \ls180
     sync always
       update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0]
   end
-  attribute \src "ls180.v:383.11-383.39"
-  process $proc$ls180.v:383$1760
+  attribute \src "ls180.v:382.5-382.27"
+  process $proc$ls180.v:382$1682
     assign { } { }
-    assign $1\sdram_timer_count1[9:0] 10'1100001101
+    assign $1\sdram_cmd_ready[0:0] 1'0
     sync always
     sync init
-      update \sdram_timer_count1 $1\sdram_timer_count1[9:0]
+      update \sdram_cmd_ready $1\sdram_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:3836.1-3843.4"
-  process $proc$ls180.v:3836$1183
+  attribute \src "ls180.v:3821.1-3828.4"
+  process $proc$ls180.v:3821$1151
     assign { } { }
     assign $0\rhs_array_muxed22[0:0] 1'0
-    attribute \src "ls180.v:3838.2-3842.9"
+    attribute \src "ls180.v:3823.2-3827.9"
     switch \subfragments_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
@@ -266013,224 +265569,240 @@ module \ls180
     sync always
       update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0]
   end
-  attribute \src "ls180.v:3844.1-3851.4"
-  process $proc$ls180.v:3844$1184
+  attribute \src "ls180.v:3829.1-3836.4"
+  process $proc$ls180.v:3829$1152
     assign { } { }
     assign $0\rhs_array_muxed23[0:0] 1'0
-    attribute \src "ls180.v:3846.2-3850.9"
+    attribute \src "ls180.v:3831.2-3835.9"
     switch \subfragments_roundrobin3_grant
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3848$1197_Y
+        assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3833$1165_Y
     end
     sync always
       update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0]
   end
-  attribute \src "ls180.v:385.5-385.33"
-  process $proc$ls180.v:385$1761
+  attribute \src "ls180.v:383.5-383.26"
+  process $proc$ls180.v:383$1683
     assign { } { }
-    assign $1\sdram_postponer_req_o[0:0] 1'0
+    assign $1\sdram_cmd_last[0:0] 1'0
     sync always
     sync init
-      update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0]
+      update \sdram_cmd_last $1\sdram_cmd_last[0:0]
   end
-  attribute \src "ls180.v:3852.1-3865.4"
-  process $proc$ls180.v:3852$1198
+  attribute \src "ls180.v:3837.1-3850.4"
+  process $proc$ls180.v:3837$1166
     assign { } { }
-    assign $0\rhs_array_muxed24[28:0] 29'00000000000000000000000000000
-    attribute \src "ls180.v:3854.2-3864.9"
+    assign $0\rhs_array_muxed24[29:0] 30'000000000000000000000000000000
+    attribute \src "ls180.v:3839.2-3849.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_ibus_adr
+        assign $0\rhs_array_muxed24[29:0] \libresocsim_interface0_converted_interface_adr
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_dbus_adr
+        assign $0\rhs_array_muxed24[29:0] \libresocsim_interface1_converted_interface_adr
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_jtag_wb_adr
+        assign $0\rhs_array_muxed24[29:0] \libresocsim_interface2_converted_interface_adr
     end
     sync always
-      update \rhs_array_muxed24 $0\rhs_array_muxed24[28:0]
+      update \rhs_array_muxed24 $0\rhs_array_muxed24[29:0]
   end
-  attribute \src "ls180.v:386.5-386.33"
-  process $proc$ls180.v:386$1762
+  attribute \src "ls180.v:384.12-384.39"
+  process $proc$ls180.v:384$1684
     assign { } { }
-    assign $1\sdram_postponer_count[0:0] 1'0
+    assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
-      update \sdram_postponer_count $1\sdram_postponer_count[0:0]
+      update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0]
+  end
+  attribute \src "ls180.v:385.11-385.38"
+  process $proc$ls180.v:385$1685
+    assign { } { }
+    assign $1\sdram_cmd_payload_ba[1:0] 2'00
+    sync always
+    sync init
+      update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0]
   end
-  attribute \src "ls180.v:3866.1-3879.4"
-  process $proc$ls180.v:3866$1199
+  attribute \src "ls180.v:3851.1-3864.4"
+  process $proc$ls180.v:3851$1167
     assign { } { }
-    assign $0\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "ls180.v:3868.2-3878.9"
+    assign $0\rhs_array_muxed25[31:0] 0
+    attribute \src "ls180.v:3853.2-3863.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_ibus_dat_w
+        assign $0\rhs_array_muxed25[31:0] \libresocsim_interface0_converted_interface_dat_w
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_dbus_dat_w
+        assign $0\rhs_array_muxed25[31:0] \libresocsim_interface1_converted_interface_dat_w
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_jtag_wb_dat_w
+        assign $0\rhs_array_muxed25[31:0] \libresocsim_interface2_converted_interface_dat_w
     end
     sync always
-      update \rhs_array_muxed25 $0\rhs_array_muxed25[63:0]
+      update \rhs_array_muxed25 $0\rhs_array_muxed25[31:0]
   end
-  attribute \src "ls180.v:387.5-387.34"
-  process $proc$ls180.v:387$1763
+  attribute \src "ls180.v:386.5-386.33"
+  process $proc$ls180.v:386$1686
     assign { } { }
-    assign $1\sdram_sequencer_start0[0:0] 1'0
+    assign $1\sdram_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
-      update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0]
+      update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:3880.1-3893.4"
-  process $proc$ls180.v:3880$1200
+  attribute \src "ls180.v:3865.1-3878.4"
+  process $proc$ls180.v:3865$1168
     assign { } { }
-    assign $0\rhs_array_muxed26[7:0] 8'00000000
-    attribute \src "ls180.v:3882.2-3892.9"
+    assign $0\rhs_array_muxed26[3:0] 4'0000
+    attribute \src "ls180.v:3867.2-3877.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_ibus_sel
+        assign $0\rhs_array_muxed26[3:0] \libresocsim_interface0_converted_interface_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_dbus_sel
+        assign $0\rhs_array_muxed26[3:0] \libresocsim_interface1_converted_interface_sel
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_jtag_wb_sel
+        assign $0\rhs_array_muxed26[3:0] \libresocsim_interface2_converted_interface_sel
     end
     sync always
-      update \rhs_array_muxed26 $0\rhs_array_muxed26[7:0]
+      update \rhs_array_muxed26 $0\rhs_array_muxed26[3:0]
+  end
+  attribute \src "ls180.v:387.5-387.33"
+  process $proc$ls180.v:387$1687
+    assign { } { }
+    assign $1\sdram_cmd_payload_ras[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:3894.1-3907.4"
-  process $proc$ls180.v:3894$1201
+  attribute \src "ls180.v:3879.1-3892.4"
+  process $proc$ls180.v:3879$1169
     assign { } { }
     assign $0\rhs_array_muxed27[0:0] 1'0
-    attribute \src "ls180.v:3896.2-3906.9"
+    attribute \src "ls180.v:3881.2-3891.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_ibus_cyc
+        assign $0\rhs_array_muxed27[0:0] \libresocsim_interface0_converted_interface_cyc
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_dbus_cyc
+        assign $0\rhs_array_muxed27[0:0] \libresocsim_interface1_converted_interface_cyc
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_jtag_wb_cyc
+        assign $0\rhs_array_muxed27[0:0] \libresocsim_interface2_converted_interface_cyc
     end
     sync always
       update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0]
   end
-  attribute \src "ls180.v:390.5-390.33"
-  process $proc$ls180.v:390$1764
+  attribute \src "ls180.v:388.5-388.32"
+  process $proc$ls180.v:388$1688
     assign { } { }
-    assign $1\sdram_sequencer_done1[0:0] 1'0
+    assign $1\sdram_cmd_payload_we[0:0] 1'0
     sync always
     sync init
-      update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0]
+      update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0]
+  end
+  attribute \src "ls180.v:389.5-389.37"
+  process $proc$ls180.v:389$1689
+    assign { } { }
+    assign $0\sdram_cmd_payload_is_read[0:0] 1'0
+    sync always
+      update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0]
+    sync init
   end
-  attribute \src "ls180.v:3908.1-3921.4"
-  process $proc$ls180.v:3908$1202
+  attribute \src "ls180.v:3893.1-3906.4"
+  process $proc$ls180.v:3893$1170
     assign { } { }
     assign $0\rhs_array_muxed28[0:0] 1'0
-    attribute \src "ls180.v:3910.2-3920.9"
+    attribute \src "ls180.v:3895.2-3905.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_ibus_stb
+        assign $0\rhs_array_muxed28[0:0] \libresocsim_interface0_converted_interface_stb
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_dbus_stb
+        assign $0\rhs_array_muxed28[0:0] \libresocsim_interface1_converted_interface_stb
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_jtag_wb_stb
+        assign $0\rhs_array_muxed28[0:0] \libresocsim_interface2_converted_interface_stb
     end
     sync always
       update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0]
   end
-  attribute \src "ls180.v:391.11-391.41"
-  process $proc$ls180.v:391$1765
-    assign { } { }
-    assign $1\sdram_sequencer_counter[3:0] 4'0000
-    sync always
-    sync init
-      update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0]
-  end
-  attribute \src "ls180.v:392.5-392.33"
-  process $proc$ls180.v:392$1766
+  attribute \src "ls180.v:390.5-390.38"
+  process $proc$ls180.v:390$1690
     assign { } { }
-    assign $1\sdram_sequencer_count[0:0] 1'0
+    assign $0\sdram_cmd_payload_is_write[0:0] 1'0
     sync always
+      update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0]
     sync init
-      update \sdram_sequencer_count $1\sdram_sequencer_count[0:0]
   end
-  attribute \src "ls180.v:3922.1-3935.4"
-  process $proc$ls180.v:3922$1203
+  attribute \src "ls180.v:3907.1-3920.4"
+  process $proc$ls180.v:3907$1171
     assign { } { }
     assign $0\rhs_array_muxed29[0:0] 1'0
-    attribute \src "ls180.v:3924.2-3934.9"
+    attribute \src "ls180.v:3909.2-3919.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_ibus_we
+        assign $0\rhs_array_muxed29[0:0] \libresocsim_interface0_converted_interface_we
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_dbus_we
+        assign $0\rhs_array_muxed29[0:0] \libresocsim_interface1_converted_interface_we
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_jtag_wb_we
+        assign $0\rhs_array_muxed29[0:0] \libresocsim_interface2_converted_interface_we
     end
     sync always
       update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0]
   end
-  attribute \src "ls180.v:3936.1-3949.4"
-  process $proc$ls180.v:3936$1204
+  attribute \src "ls180.v:3921.1-3934.4"
+  process $proc$ls180.v:3921$1172
     assign { } { }
     assign $0\rhs_array_muxed30[2:0] 3'000
-    attribute \src "ls180.v:3938.2-3948.9"
+    attribute \src "ls180.v:3923.2-3933.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_ibus_cti
+        assign $0\rhs_array_muxed30[2:0] \libresocsim_interface0_converted_interface_cti
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_dbus_cti
+        assign $0\rhs_array_muxed30[2:0] \libresocsim_interface1_converted_interface_cti
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_jtag_wb_cti
+        assign $0\rhs_array_muxed30[2:0] \libresocsim_interface2_converted_interface_cti
     end
     sync always
       update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0]
   end
-  attribute \src "ls180.v:3950.1-3963.4"
-  process $proc$ls180.v:3950$1205
+  attribute \src "ls180.v:3935.1-3948.4"
+  process $proc$ls180.v:3935$1173
     assign { } { }
     assign $0\rhs_array_muxed31[1:0] 2'00
-    attribute \src "ls180.v:3952.2-3962.9"
+    attribute \src "ls180.v:3937.2-3947.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_ibus_bte
+        assign $0\rhs_array_muxed31[1:0] \libresocsim_interface0_converted_interface_bte
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_dbus_bte
+        assign $0\rhs_array_muxed31[1:0] \libresocsim_interface1_converted_interface_bte
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_jtag_wb_bte
+        assign $0\rhs_array_muxed31[1:0] \libresocsim_interface2_converted_interface_bte
     end
     sync always
       update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0]
   end
-  attribute \src "ls180.v:3964.1-3980.4"
-  process $proc$ls180.v:3964$1206
+  attribute \src "ls180.v:3949.1-3965.4"
+  process $proc$ls180.v:3949$1174
     assign { } { }
     assign $0\array_muxed0[1:0] 2'00
-    attribute \src "ls180.v:3966.2-3979.9"
+    attribute \src "ls180.v:3951.2-3964.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -266248,19 +265820,19 @@ module \ls180
     sync always
       update \array_muxed0 $0\array_muxed0[1:0]
   end
-  attribute \src "ls180.v:398.5-398.46"
-  process $proc$ls180.v:398$1767
+  attribute \src "ls180.v:396.11-396.39"
+  process $proc$ls180.v:396$1691
     assign { } { }
-    assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+    assign $1\sdram_timer_count1[9:0] 10'1100001101
     sync always
     sync init
-      update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0]
+      update \sdram_timer_count1 $1\sdram_timer_count1[9:0]
   end
-  attribute \src "ls180.v:3981.1-3997.4"
-  process $proc$ls180.v:3981$1207
+  attribute \src "ls180.v:3966.1-3982.4"
+  process $proc$ls180.v:3966$1175
     assign { } { }
     assign $0\array_muxed1[12:0] 13'0000000000000
-    attribute \src "ls180.v:3983.2-3996.9"
+    attribute \src "ls180.v:3968.2-3981.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
@@ -266278,237 +265850,221 @@ module \ls180
     sync always
       update \array_muxed1 $0\array_muxed1[12:0]
   end
-  attribute \src "ls180.v:399.5-399.46"
-  process $proc$ls180.v:399$1768
+  attribute \src "ls180.v:398.5-398.33"
+  process $proc$ls180.v:398$1692
     assign { } { }
-    assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+    assign $1\sdram_postponer_req_o[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0]
+      update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0]
   end
-  attribute \src "ls180.v:3998.1-4014.4"
-  process $proc$ls180.v:3998$1208
+  attribute \src "ls180.v:3983.1-3999.4"
+  process $proc$ls180.v:3983$1176
     assign { } { }
     assign $0\array_muxed2[0:0] 1'0
-    attribute \src "ls180.v:4000.2-4013.9"
+    attribute \src "ls180.v:3985.2-3998.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\array_muxed2[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\array_muxed2[0:0] $and$ls180.v:4005$1210_Y
+        assign $0\array_muxed2[0:0] $and$ls180.v:3990$1178_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\array_muxed2[0:0] $and$ls180.v:4008$1212_Y
+        assign $0\array_muxed2[0:0] $and$ls180.v:3993$1180_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\array_muxed2[0:0] $and$ls180.v:4011$1214_Y
+        assign $0\array_muxed2[0:0] $and$ls180.v:3996$1182_Y
     end
     sync always
       update \array_muxed2 $0\array_muxed2[0:0]
   end
-  attribute \src "ls180.v:401.5-401.42"
-  process $proc$ls180.v:401$1769
+  attribute \src "ls180.v:399.5-399.33"
+  process $proc$ls180.v:399$1693
     assign { } { }
-    assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0
+    assign $1\sdram_postponer_count[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0]
+      update \sdram_postponer_count $1\sdram_postponer_count[0:0]
+  end
+  attribute \src "ls180.v:400.5-400.34"
+  process $proc$ls180.v:400$1694
+    assign { } { }
+    assign $1\sdram_sequencer_start0[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0]
   end
-  attribute \src "ls180.v:4015.1-4031.4"
-  process $proc$ls180.v:4015$1215
+  attribute \src "ls180.v:4000.1-4016.4"
+  process $proc$ls180.v:4000$1183
     assign { } { }
     assign $0\array_muxed3[0:0] 1'0
-    attribute \src "ls180.v:4017.2-4030.9"
+    attribute \src "ls180.v:4002.2-4015.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\array_muxed3[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\array_muxed3[0:0] $and$ls180.v:4022$1217_Y
+        assign $0\array_muxed3[0:0] $and$ls180.v:4007$1185_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\array_muxed3[0:0] $and$ls180.v:4025$1219_Y
+        assign $0\array_muxed3[0:0] $and$ls180.v:4010$1187_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\array_muxed3[0:0] $and$ls180.v:4028$1221_Y
+        assign $0\array_muxed3[0:0] $and$ls180.v:4013$1189_Y
     end
     sync always
       update \array_muxed3 $0\array_muxed3[0:0]
   end
-  attribute \src "ls180.v:402.5-402.40"
-  process $proc$ls180.v:402$1770
-    assign { } { }
-    assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0]
-  end
-  attribute \src "ls180.v:403.5-403.40"
-  process $proc$ls180.v:403$1771
-    assign { } { }
-    assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0]
-  end
-  attribute \src "ls180.v:4032.1-4048.4"
-  process $proc$ls180.v:4032$1222
+  attribute \src "ls180.v:4017.1-4033.4"
+  process $proc$ls180.v:4017$1190
     assign { } { }
     assign $0\array_muxed4[0:0] 1'0
-    attribute \src "ls180.v:4034.2-4047.9"
+    attribute \src "ls180.v:4019.2-4032.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\array_muxed4[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\array_muxed4[0:0] $and$ls180.v:4039$1224_Y
+        assign $0\array_muxed4[0:0] $and$ls180.v:4024$1192_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\array_muxed4[0:0] $and$ls180.v:4042$1226_Y
+        assign $0\array_muxed4[0:0] $and$ls180.v:4027$1194_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\array_muxed4[0:0] $and$ls180.v:4045$1228_Y
+        assign $0\array_muxed4[0:0] $and$ls180.v:4030$1196_Y
     end
     sync always
       update \array_muxed4 $0\array_muxed4[0:0]
   end
-  attribute \src "ls180.v:404.12-404.52"
-  process $proc$ls180.v:404$1772
+  attribute \src "ls180.v:403.5-403.33"
+  process $proc$ls180.v:403$1695
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+    assign $1\sdram_sequencer_done1[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0]
+      update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0]
   end
-  attribute \src "ls180.v:4049.1-4065.4"
-  process $proc$ls180.v:4049$1229
+  attribute \src "ls180.v:4034.1-4050.4"
+  process $proc$ls180.v:4034$1197
     assign { } { }
     assign $0\array_muxed5[0:0] 1'0
-    attribute \src "ls180.v:4051.2-4064.9"
+    attribute \src "ls180.v:4036.2-4049.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\array_muxed5[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\array_muxed5[0:0] $and$ls180.v:4056$1231_Y
+        assign $0\array_muxed5[0:0] $and$ls180.v:4041$1199_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\array_muxed5[0:0] $and$ls180.v:4059$1233_Y
+        assign $0\array_muxed5[0:0] $and$ls180.v:4044$1201_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\array_muxed5[0:0] $and$ls180.v:4062$1235_Y
+        assign $0\array_muxed5[0:0] $and$ls180.v:4047$1203_Y
     end
     sync always
       update \array_muxed5 $0\array_muxed5[0:0]
   end
-  attribute \src "ls180.v:406.5-406.46"
-  process $proc$ls180.v:406$1773
+  attribute \src "ls180.v:404.11-404.41"
+  process $proc$ls180.v:404$1696
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+    assign $1\sdram_sequencer_counter[3:0] 4'0000
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0]
+      update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0]
   end
-  attribute \src "ls180.v:4066.1-4082.4"
-  process $proc$ls180.v:4066$1236
+  attribute \src "ls180.v:405.5-405.33"
+  process $proc$ls180.v:405$1697
+    assign { } { }
+    assign $1\sdram_sequencer_count[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_sequencer_count $1\sdram_sequencer_count[0:0]
+  end
+  attribute \src "ls180.v:4051.1-4067.4"
+  process $proc$ls180.v:4051$1204
     assign { } { }
     assign $0\array_muxed6[0:0] 1'0
-    attribute \src "ls180.v:4068.2-4081.9"
+    attribute \src "ls180.v:4053.2-4066.9"
     switch \sdram_steerer_sel
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
         assign $0\array_muxed6[0:0] 1'0
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        assign $0\array_muxed6[0:0] $and$ls180.v:4073$1238_Y
+        assign $0\array_muxed6[0:0] $and$ls180.v:4058$1206_Y
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        assign $0\array_muxed6[0:0] $and$ls180.v:4076$1240_Y
+        assign $0\array_muxed6[0:0] $and$ls180.v:4061$1208_Y
       attribute \src "ls180.v:0.0-0.0"
       case 
-        assign $0\array_muxed6[0:0] $and$ls180.v:4079$1242_Y
+        assign $0\array_muxed6[0:0] $and$ls180.v:4064$1210_Y
     end
     sync always
       update \array_muxed6 $0\array_muxed6[0:0]
   end
-  attribute \src "ls180.v:407.5-407.46"
-  process $proc$ls180.v:407$1774
-    assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0]
-  end
-  attribute \src "ls180.v:408.5-408.45"
-  process $proc$ls180.v:408$1775
-    assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0]
-  end
-  attribute \src "ls180.v:409.5-409.49"
-  process $proc$ls180.v:409$1776
+  attribute \src "ls180.v:411.5-411.46"
+  process $proc$ls180.v:411$1698
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+    assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+      update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:410.5-410.50"
-  process $proc$ls180.v:410$1777
+  attribute \src "ls180.v:412.5-412.46"
+  process $proc$ls180.v:412$1699
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+    assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0]
+      update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:411.5-411.51"
-  process $proc$ls180.v:411$1778
+  attribute \src "ls180.v:414.5-414.42"
+  process $proc$ls180.v:414$1700
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+    assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0]
+      update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:412.5-412.45"
-  process $proc$ls180.v:412$1779
+  attribute \src "ls180.v:415.5-415.40"
+  process $proc$ls180.v:415$1701
     assign { } { }
-    assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0
+    assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0]
+      update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:415.5-415.62"
-  process $proc$ls180.v:415$1780
+  attribute \src "ls180.v:416.5-416.40"
+  process $proc$ls180.v:416$1702
     assign { } { }
-    assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0
     sync always
-      update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
     sync init
+      update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:416.5-416.61"
-  process $proc$ls180.v:416$1781
+  attribute \src "ls180.v:417.12-417.52"
+  process $proc$ls180.v:417$1703
     assign { } { }
-    assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
     sync always
-      update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
     sync init
+      update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:4189.1-4191.4"
-  process $proc$ls180.v:4189$1243
+  attribute \src "ls180.v:4174.1-4176.4"
+  process $proc$ls180.v:4174$1211
     assign { } { }
     assign $0\int_rst[0:0] \sys_rst
     sync posedge \por_clk
       update \int_rst $0\int_rst[0:0]
   end
-  attribute \src "ls180.v:4193.1-4298.4"
-  process $proc$ls180.v:4193$1244
+  attribute \src "ls180.v:4178.1-4283.4"
+  process $proc$ls180.v:4178$1212
     assign { } { }
     assign { } { }
     assign { } { }
@@ -266580,8 +266136,8 @@ module \ls180
     assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_sdram_dq_i [14]
     assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15]
     assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_sdram_dq_i [15]
-    assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4247$1245_Y
-    assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4248$1246_Y
+    assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4232$1213_Y
+    assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4233$1214_Y
     assign $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] \sys_clk_1
     assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0]
     assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0]
@@ -266651,14 +266207,84 @@ module \ls180
       update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0]
       update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0]
   end
-  attribute \src "ls180.v:4300.1-5506.4"
-  process $proc$ls180.v:4300$1247
+  attribute \src "ls180.v:419.5-419.46"
+  process $proc$ls180.v:419$1704
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0]
+  end
+  attribute \src "ls180.v:420.5-420.46"
+  process $proc$ls180.v:420$1705
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0]
+  end
+  attribute \src "ls180.v:421.5-421.45"
+  process $proc$ls180.v:421$1706
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0]
+  end
+  attribute \src "ls180.v:422.5-422.49"
+  process $proc$ls180.v:422$1707
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+  end
+  attribute \src "ls180.v:423.5-423.50"
+  process $proc$ls180.v:423$1708
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0]
+  end
+  attribute \src "ls180.v:424.5-424.51"
+  process $proc$ls180.v:424$1709
+    assign { } { }
+    assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0]
+  end
+  attribute \src "ls180.v:425.5-425.45"
+  process $proc$ls180.v:425$1710
+    assign { } { }
+    assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0]
+  end
+  attribute \src "ls180.v:428.5-428.62"
+  process $proc$ls180.v:428$1711
+    assign { } { }
+    assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
+    sync always
+      update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:4285.1-5491.4"
+  process $proc$ls180.v:4285$1215
     assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage
     assign { } { }
     assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage
     assign { } { }
     assign $0\libresocsim_bus_errors[31:0] \libresocsim_bus_errors
     assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_uart_tx
+    assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter
+    assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_converter0_dat_r
+    assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter
+    assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_converter1_dat_r
+    assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter
+    assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_converter2_dat_r
     assign { } { }
     assign $0\libresocsim_load_storage[31:0] \libresocsim_load_storage
     assign { } { }
@@ -266675,10 +266301,6 @@ module \ls180
     assign { } { }
     assign $0\libresocsim_value[31:0] \libresocsim_value
     assign { } { }
-    assign $0\converter0_counter[0:0] \converter0_counter
-    assign $0\converter0_dat_r[63:0] \converter0_dat_r
-    assign $0\converter1_counter[0:0] \converter1_counter
-    assign $0\converter1_dat_r[63:0] \converter1_dat_r
     assign { } { }
     assign { } { }
     assign $0\sdram_storage[3:0] \sdram_storage
@@ -266767,8 +266389,6 @@ module \ls180
     assign $0\sdram_twtrcon_count[2:0] \sdram_twtrcon_count
     assign $0\sdram_time0[4:0] \sdram_time0
     assign $0\sdram_time1[3:0] \sdram_time1
-    assign $0\socbushandler_counter[0:0] \socbushandler_counter
-    assign $0\socbushandler_dat_r[63:0] \socbushandler_dat_r
     assign $0\converter_counter[0:0] \converter_counter
     assign $0\converter_dat_r[31:0] \converter_dat_r
     assign $0\cmd_consumed[0:0] \cmd_consumed
@@ -266846,42 +266466,42 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0\dummy[35:0] [0] $or$ls180.v:4301$1248_Y
-    assign $0\dummy[35:0] [1] $or$ls180.v:4302$1249_Y
-    assign $0\dummy[35:0] [2] $or$ls180.v:4303$1250_Y
-    assign $0\dummy[35:0] [3] $or$ls180.v:4304$1251_Y
-    assign $0\dummy[35:0] [4] $or$ls180.v:4305$1252_Y
-    assign $0\dummy[35:0] [5] $or$ls180.v:4306$1253_Y
-    assign $0\dummy[35:0] [6] $or$ls180.v:4307$1254_Y
-    assign $0\dummy[35:0] [7] $or$ls180.v:4308$1255_Y
-    assign $0\dummy[35:0] [8] $or$ls180.v:4309$1256_Y
-    assign $0\dummy[35:0] [9] $or$ls180.v:4310$1257_Y
-    assign $0\dummy[35:0] [10] $or$ls180.v:4311$1258_Y
-    assign $0\dummy[35:0] [11] $or$ls180.v:4312$1259_Y
-    assign $0\dummy[35:0] [12] $or$ls180.v:4313$1260_Y
-    assign $0\dummy[35:0] [13] $or$ls180.v:4314$1261_Y
-    assign $0\dummy[35:0] [14] $or$ls180.v:4315$1262_Y
-    assign $0\dummy[35:0] [15] $or$ls180.v:4316$1263_Y
-    assign $0\dummy[35:0] [16] $or$ls180.v:4317$1264_Y
-    assign $0\dummy[35:0] [17] $or$ls180.v:4318$1265_Y
-    assign $0\dummy[35:0] [18] $or$ls180.v:4319$1266_Y
-    assign $0\dummy[35:0] [19] $or$ls180.v:4320$1267_Y
-    assign $0\dummy[35:0] [20] $or$ls180.v:4321$1268_Y
-    assign $0\dummy[35:0] [21] $or$ls180.v:4322$1269_Y
-    assign $0\dummy[35:0] [22] $or$ls180.v:4323$1270_Y
-    assign $0\dummy[35:0] [23] $or$ls180.v:4324$1271_Y
-    assign $0\dummy[35:0] [24] $or$ls180.v:4325$1272_Y
-    assign $0\dummy[35:0] [25] $or$ls180.v:4326$1273_Y
-    assign $0\dummy[35:0] [26] $or$ls180.v:4327$1274_Y
-    assign $0\dummy[35:0] [27] $or$ls180.v:4328$1275_Y
-    assign $0\dummy[35:0] [28] $or$ls180.v:4329$1276_Y
-    assign $0\dummy[35:0] [29] $or$ls180.v:4330$1277_Y
-    assign $0\dummy[35:0] [30] $or$ls180.v:4331$1278_Y
-    assign $0\dummy[35:0] [31] $or$ls180.v:4332$1279_Y
-    assign $0\dummy[35:0] [32] $or$ls180.v:4333$1280_Y
-    assign $0\dummy[35:0] [33] $or$ls180.v:4334$1281_Y
-    assign $0\dummy[35:0] [34] $or$ls180.v:4335$1282_Y
-    assign $0\dummy[35:0] [35] $or$ls180.v:4336$1283_Y
+    assign $0\dummy[35:0] [0] $or$ls180.v:4286$1216_Y
+    assign $0\dummy[35:0] [1] $or$ls180.v:4287$1217_Y
+    assign $0\dummy[35:0] [2] $or$ls180.v:4288$1218_Y
+    assign $0\dummy[35:0] [3] $or$ls180.v:4289$1219_Y
+    assign $0\dummy[35:0] [4] $or$ls180.v:4290$1220_Y
+    assign $0\dummy[35:0] [5] $or$ls180.v:4291$1221_Y
+    assign $0\dummy[35:0] [6] $or$ls180.v:4292$1222_Y
+    assign $0\dummy[35:0] [7] $or$ls180.v:4293$1223_Y
+    assign $0\dummy[35:0] [8] $or$ls180.v:4294$1224_Y
+    assign $0\dummy[35:0] [9] $or$ls180.v:4295$1225_Y
+    assign $0\dummy[35:0] [10] $or$ls180.v:4296$1226_Y
+    assign $0\dummy[35:0] [11] $or$ls180.v:4297$1227_Y
+    assign $0\dummy[35:0] [12] $or$ls180.v:4298$1228_Y
+    assign $0\dummy[35:0] [13] $or$ls180.v:4299$1229_Y
+    assign $0\dummy[35:0] [14] $or$ls180.v:4300$1230_Y
+    assign $0\dummy[35:0] [15] $or$ls180.v:4301$1231_Y
+    assign $0\dummy[35:0] [16] $or$ls180.v:4302$1232_Y
+    assign $0\dummy[35:0] [17] $or$ls180.v:4303$1233_Y
+    assign $0\dummy[35:0] [18] $or$ls180.v:4304$1234_Y
+    assign $0\dummy[35:0] [19] $or$ls180.v:4305$1235_Y
+    assign $0\dummy[35:0] [20] $or$ls180.v:4306$1236_Y
+    assign $0\dummy[35:0] [21] $or$ls180.v:4307$1237_Y
+    assign $0\dummy[35:0] [22] $or$ls180.v:4308$1238_Y
+    assign $0\dummy[35:0] [23] $or$ls180.v:4309$1239_Y
+    assign $0\dummy[35:0] [24] $or$ls180.v:4310$1240_Y
+    assign $0\dummy[35:0] [25] $or$ls180.v:4311$1241_Y
+    assign $0\dummy[35:0] [26] $or$ls180.v:4312$1242_Y
+    assign $0\dummy[35:0] [27] $or$ls180.v:4313$1243_Y
+    assign $0\dummy[35:0] [28] $or$ls180.v:4314$1244_Y
+    assign $0\dummy[35:0] [29] $or$ls180.v:4315$1245_Y
+    assign $0\dummy[35:0] [30] $or$ls180.v:4316$1246_Y
+    assign $0\dummy[35:0] [31] $or$ls180.v:4317$1247_Y
+    assign $0\dummy[35:0] [32] $or$ls180.v:4318$1248_Y
+    assign $0\dummy[35:0] [33] $or$ls180.v:4319$1249_Y
+    assign $0\dummy[35:0] [34] $or$ls180.v:4320$1250_Y
+    assign $0\dummy[35:0] [35] $or$ls180.v:4321$1251_Y
     assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state
     assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state
     assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state
@@ -266905,14 +266525,14 @@ module \ls180
     assign $0\sdram_dfi_p0_cs_n[0:0] 1'0
     assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0
     assign $0\sdram_dfi_p0_address[12:0] \array_muxed1
-    assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4782$1383_Y
-    assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4783$1384_Y
-    assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4784$1385_Y
+    assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4767$1351_Y
+    assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4768$1352_Y
+    assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4769$1353_Y
     assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5
     assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6
     assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state
-    assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4818$1403_Y
-    assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4819$1415_Y
+    assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4803$1371_Y
+    assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4804$1383_Y
     assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0
     assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1
     assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2
@@ -266953,161 +266573,161 @@ module \ls180
     assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re
     assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_uart_rx
     assign $0\regs1[0:0] \regs0
-    attribute \src "ls180.v:4337.2-4339.5"
-    switch $or$ls180.v:4337$1284_Y
-      attribute \src "ls180.v:4337.6-4337.59"
+    attribute \src "ls180.v:4322.2-4324.5"
+    switch $or$ls180.v:4322$1252_Y
+      attribute \src "ls180.v:4322.6-4322.84"
       case 1'1
-        assign $0\converter0_dat_r[63:0] \interface0_converted_interface_dat_r
+        assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_libresoc_ibus_dat_r
       case 
     end
-    attribute \src "ls180.v:4341.2-4343.5"
-    switch \converter0_counter_subfragments_converter0_next_value_ce
-      attribute \src "ls180.v:4341.6-4341.62"
+    attribute \src "ls180.v:4326.2-4328.5"
+    switch \libresocsim_converter0_counter_subfragments_converter0_next_value_ce
+      attribute \src "ls180.v:4326.6-4326.74"
       case 1'1
-        assign $0\converter0_counter[0:0] \converter0_counter_subfragments_converter0_next_value
+        assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter_subfragments_converter0_next_value
       case 
     end
-    attribute \src "ls180.v:4344.2-4347.5"
-    switch \converter0_reset
-      attribute \src "ls180.v:4344.6-4344.22"
+    attribute \src "ls180.v:4329.2-4332.5"
+    switch \libresocsim_converter0_reset
+      attribute \src "ls180.v:4329.6-4329.34"
       case 1'1
-        assign $0\converter0_counter[0:0] 1'0
+        assign $0\libresocsim_converter0_counter[0:0] 1'0
         assign $0\subfragments_converter0_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4348.2-4350.5"
-    switch $or$ls180.v:4348$1285_Y
-      attribute \src "ls180.v:4348.6-4348.59"
+    attribute \src "ls180.v:4333.2-4335.5"
+    switch $or$ls180.v:4333$1253_Y
+      attribute \src "ls180.v:4333.6-4333.84"
       case 1'1
-        assign $0\converter1_dat_r[63:0] \interface1_converted_interface_dat_r
+        assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_libresoc_dbus_dat_r
       case 
     end
-    attribute \src "ls180.v:4352.2-4354.5"
-    switch \converter1_counter_subfragments_converter1_next_value_ce
-      attribute \src "ls180.v:4352.6-4352.62"
+    attribute \src "ls180.v:4337.2-4339.5"
+    switch \libresocsim_converter1_counter_subfragments_converter1_next_value_ce
+      attribute \src "ls180.v:4337.6-4337.74"
       case 1'1
-        assign $0\converter1_counter[0:0] \converter1_counter_subfragments_converter1_next_value
+        assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter_subfragments_converter1_next_value
       case 
     end
-    attribute \src "ls180.v:4355.2-4358.5"
-    switch \converter1_reset
-      attribute \src "ls180.v:4355.6-4355.22"
+    attribute \src "ls180.v:4340.2-4343.5"
+    switch \libresocsim_converter1_reset
+      attribute \src "ls180.v:4340.6-4340.34"
       case 1'1
-        assign $0\converter1_counter[0:0] 1'0
+        assign $0\libresocsim_converter1_counter[0:0] 1'0
         assign $0\subfragments_converter1_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4359.2-4361.5"
-    switch $or$ls180.v:4359$1286_Y
-      attribute \src "ls180.v:4359.6-4359.41"
+    attribute \src "ls180.v:4344.2-4346.5"
+    switch $or$ls180.v:4344$1254_Y
+      attribute \src "ls180.v:4344.6-4344.84"
       case 1'1
-        assign $0\socbushandler_dat_r[63:0] \socbushandler_converted_interface_dat_r
+        assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_libresoc_jtag_wb_dat_r
       case 
     end
-    attribute \src "ls180.v:4363.2-4365.5"
-    switch \socbushandler_counter_subfragments_converter2_next_value_ce
-      attribute \src "ls180.v:4363.6-4363.65"
+    attribute \src "ls180.v:4348.2-4350.5"
+    switch \libresocsim_converter2_counter_subfragments_converter2_next_value_ce
+      attribute \src "ls180.v:4348.6-4348.74"
       case 1'1
-        assign $0\socbushandler_counter[0:0] \socbushandler_counter_subfragments_converter2_next_value
+        assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter_subfragments_converter2_next_value
       case 
     end
-    attribute \src "ls180.v:4366.2-4369.5"
-    switch \socbushandler_reset
-      attribute \src "ls180.v:4366.6-4366.25"
+    attribute \src "ls180.v:4351.2-4354.5"
+    switch \libresocsim_converter2_reset
+      attribute \src "ls180.v:4351.6-4351.34"
       case 1'1
-        assign $0\socbushandler_counter[0:0] 1'0
+        assign $0\libresocsim_converter2_counter[0:0] 1'0
         assign $0\subfragments_converter2_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4370.2-4374.5"
-    switch $ne$ls180.v:4370$1287_Y
-      attribute \src "ls180.v:4370.6-4370.48"
+    attribute \src "ls180.v:4355.2-4359.5"
+    switch $ne$ls180.v:4355$1255_Y
+      attribute \src "ls180.v:4355.6-4355.48"
       case 1'1
-        attribute \src "ls180.v:4371.3-4373.6"
+        attribute \src "ls180.v:4356.3-4358.6"
         switch \libresocsim_bus_error
-          attribute \src "ls180.v:4371.7-4371.28"
+          attribute \src "ls180.v:4356.7-4356.28"
           case 1'1
-            assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4372$1288_Y
+            assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4357$1256_Y
           case 
         end
       case 
     end
-    attribute \src "ls180.v:4376.2-4378.5"
-    switch $and$ls180.v:4376$1291_Y
-      attribute \src "ls180.v:4376.6-4376.88"
+    attribute \src "ls180.v:4361.2-4363.5"
+    switch $and$ls180.v:4361$1259_Y
+      attribute \src "ls180.v:4361.6-4361.88"
       case 1'1
         assign $0\libresocsim_ram_bus_ack[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4379.2-4387.5"
+    attribute \src "ls180.v:4364.2-4372.5"
     switch \libresocsim_en_storage
-      attribute \src "ls180.v:4379.6-4379.28"
+      attribute \src "ls180.v:4364.6-4364.28"
       case 1'1
-        attribute \src "ls180.v:4380.3-4384.6"
-        switch $eq$ls180.v:4380$1292_Y
-          attribute \src "ls180.v:4380.7-4380.34"
+        attribute \src "ls180.v:4365.3-4369.6"
+        switch $eq$ls180.v:4365$1260_Y
+          attribute \src "ls180.v:4365.7-4365.34"
           case 1'1
             assign $0\libresocsim_value[31:0] \libresocsim_reload_storage
-          attribute \src "ls180.v:4382.7-4382.11"
+          attribute \src "ls180.v:4367.7-4367.11"
           case 
-            assign $0\libresocsim_value[31:0] $sub$ls180.v:4383$1293_Y
+            assign $0\libresocsim_value[31:0] $sub$ls180.v:4368$1261_Y
         end
-      attribute \src "ls180.v:4385.6-4385.10"
+      attribute \src "ls180.v:4370.6-4370.10"
       case 
         assign $0\libresocsim_value[31:0] \libresocsim_load_storage
     end
-    attribute \src "ls180.v:4388.2-4390.5"
+    attribute \src "ls180.v:4373.2-4375.5"
     switch \libresocsim_update_value_re
-      attribute \src "ls180.v:4388.6-4388.33"
+      attribute \src "ls180.v:4373.6-4373.33"
       case 1'1
         assign $0\libresocsim_value_status[31:0] \libresocsim_value
       case 
     end
-    attribute \src "ls180.v:4391.2-4393.5"
+    attribute \src "ls180.v:4376.2-4378.5"
     switch \libresocsim_zero_clear
-      attribute \src "ls180.v:4391.6-4391.28"
+      attribute \src "ls180.v:4376.6-4376.28"
       case 1'1
         assign $0\libresocsim_zero_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4395.2-4397.5"
-    switch $and$ls180.v:4395$1295_Y
-      attribute \src "ls180.v:4395.6-4395.66"
+    attribute \src "ls180.v:4380.2-4382.5"
+    switch $and$ls180.v:4380$1263_Y
+      attribute \src "ls180.v:4380.6-4380.66"
       case 1'1
         assign $0\libresocsim_zero_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4399.2-4401.5"
-    switch $and$ls180.v:4399$1298_Y
-      attribute \src "ls180.v:4399.6-4399.76"
+    attribute \src "ls180.v:4384.2-4386.5"
+    switch $and$ls180.v:4384$1266_Y
+      attribute \src "ls180.v:4384.6-4384.76"
       case 1'1
         assign $0\ram_bus_ram_bus_ack[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4404.2-4406.5"
+    attribute \src "ls180.v:4389.2-4391.5"
     switch \sdram_inti_p0_rddata_valid
-      attribute \src "ls180.v:4404.6-4404.32"
+      attribute \src "ls180.v:4389.6-4389.32"
       case 1'1
         assign $0\sdram_status[15:0] \sdram_inti_p0_rddata
       case 
     end
-    attribute \src "ls180.v:4407.2-4411.5"
-    switch $and$ls180.v:4407$1300_Y
-      attribute \src "ls180.v:4407.6-4407.47"
+    attribute \src "ls180.v:4392.2-4396.5"
+    switch $and$ls180.v:4392$1268_Y
+      attribute \src "ls180.v:4392.6-4392.47"
       case 1'1
-        assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4408$1301_Y
-      attribute \src "ls180.v:4409.6-4409.10"
+        assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4393$1269_Y
+      attribute \src "ls180.v:4394.6-4394.10"
       case 
         assign $0\sdram_timer_count1[9:0] 10'1100001101
     end
-    attribute \src "ls180.v:4413.2-4419.5"
+    attribute \src "ls180.v:4398.2-4404.5"
     switch \sdram_postponer_req_i
-      attribute \src "ls180.v:4413.6-4413.27"
+      attribute \src "ls180.v:4398.6-4398.27"
       case 1'1
-        assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4414$1302_Y
-        attribute \src "ls180.v:4415.3-4418.6"
-        switch $eq$ls180.v:4415$1303_Y
-          attribute \src "ls180.v:4415.7-4415.38"
+        assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4399$1270_Y
+        attribute \src "ls180.v:4400.3-4403.6"
+        switch $eq$ls180.v:4400$1271_Y
+          attribute \src "ls180.v:4400.7-4400.38"
           case 1'1
             assign $0\sdram_postponer_count[0:0] 1'0
             assign $0\sdram_postponer_req_o[0:0] 1'1
@@ -267115,30 +266735,30 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:4420.2-4428.5"
+    attribute \src "ls180.v:4405.2-4413.5"
     switch \sdram_sequencer_start0
-      attribute \src "ls180.v:4420.6-4420.28"
+      attribute \src "ls180.v:4405.6-4405.28"
       case 1'1
         assign $0\sdram_sequencer_count[0:0] 1'0
-      attribute \src "ls180.v:4422.6-4422.10"
+      attribute \src "ls180.v:4407.6-4407.10"
       case 
-        attribute \src "ls180.v:4423.3-4427.6"
+        attribute \src "ls180.v:4408.3-4412.6"
         switch \sdram_sequencer_done1
-          attribute \src "ls180.v:4423.7-4423.28"
+          attribute \src "ls180.v:4408.7-4408.28"
           case 1'1
-            attribute \src "ls180.v:4424.4-4426.7"
-            switch $ne$ls180.v:4424$1304_Y
-              attribute \src "ls180.v:4424.8-4424.39"
+            attribute \src "ls180.v:4409.4-4411.7"
+            switch $ne$ls180.v:4409$1272_Y
+              attribute \src "ls180.v:4409.8-4409.39"
               case 1'1
-                assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4425$1305_Y
+                assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4410$1273_Y
               case 
             end
           case 
         end
     end
-    attribute \src "ls180.v:4435.2-4441.5"
-    switch $and$ls180.v:4435$1307_Y
-      attribute \src "ls180.v:4435.6-4435.66"
+    attribute \src "ls180.v:4420.2-4426.5"
+    switch $and$ls180.v:4420$1275_Y
+      attribute \src "ls180.v:4420.6-4420.66"
       case 1'1
         assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000
         assign $0\sdram_cmd_payload_ba[1:0] 2'00
@@ -267147,9 +266767,9 @@ module \ls180
         assign $0\sdram_cmd_payload_we[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4442.2-4448.5"
-    switch $eq$ls180.v:4442$1308_Y
-      attribute \src "ls180.v:4442.6-4442.39"
+    attribute \src "ls180.v:4427.2-4433.5"
+    switch $eq$ls180.v:4427$1276_Y
+      attribute \src "ls180.v:4427.6-4427.39"
       case 1'1
         assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\sdram_cmd_payload_ba[1:0] 2'00
@@ -267158,9 +266778,9 @@ module \ls180
         assign $0\sdram_cmd_payload_we[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4449.2-4456.5"
-    switch $eq$ls180.v:4449$1309_Y
-      attribute \src "ls180.v:4449.6-4449.39"
+    attribute \src "ls180.v:4434.2-4441.5"
+    switch $eq$ls180.v:4434$1277_Y
+      attribute \src "ls180.v:4434.6-4434.39"
       case 1'1
         assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000
         assign $0\sdram_cmd_payload_ba[1:0] 2'00
@@ -267170,83 +266790,83 @@ module \ls180
         assign $0\sdram_sequencer_done1[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4457.2-4467.5"
-    switch $eq$ls180.v:4457$1310_Y
-      attribute \src "ls180.v:4457.6-4457.39"
+    attribute \src "ls180.v:4442.2-4452.5"
+    switch $eq$ls180.v:4442$1278_Y
+      attribute \src "ls180.v:4442.6-4442.39"
       case 1'1
         assign $0\sdram_sequencer_counter[3:0] 4'0000
-      attribute \src "ls180.v:4459.6-4459.10"
+      attribute \src "ls180.v:4444.6-4444.10"
       case 
-        attribute \src "ls180.v:4460.3-4466.6"
-        switch $ne$ls180.v:4460$1311_Y
-          attribute \src "ls180.v:4460.7-4460.40"
+        attribute \src "ls180.v:4445.3-4451.6"
+        switch $ne$ls180.v:4445$1279_Y
+          attribute \src "ls180.v:4445.7-4445.40"
           case 1'1
-            assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4461$1312_Y
-          attribute \src "ls180.v:4462.7-4462.11"
+            assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4446$1280_Y
+          attribute \src "ls180.v:4447.7-4447.11"
           case 
-            attribute \src "ls180.v:4463.4-4465.7"
+            attribute \src "ls180.v:4448.4-4450.7"
             switch \sdram_sequencer_start1
-              attribute \src "ls180.v:4463.8-4463.30"
+              attribute \src "ls180.v:4448.8-4448.30"
               case 1'1
                 assign $0\sdram_sequencer_counter[3:0] 4'0001
               case 
             end
         end
     end
-    attribute \src "ls180.v:4469.2-4476.5"
+    attribute \src "ls180.v:4454.2-4461.5"
     switch \sdram_bankmachine0_row_close
-      attribute \src "ls180.v:4469.6-4469.34"
+      attribute \src "ls180.v:4454.6-4454.34"
       case 1'1
         assign $0\sdram_bankmachine0_row_opened[0:0] 1'0
-      attribute \src "ls180.v:4471.6-4471.10"
+      attribute \src "ls180.v:4456.6-4456.10"
       case 
-        attribute \src "ls180.v:4472.3-4475.6"
+        attribute \src "ls180.v:4457.3-4460.6"
         switch \sdram_bankmachine0_row_open
-          attribute \src "ls180.v:4472.7-4472.34"
+          attribute \src "ls180.v:4457.7-4457.34"
           case 1'1
             assign $0\sdram_bankmachine0_row_opened[0:0] 1'1
             assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:4477.2-4479.5"
-    switch $and$ls180.v:4477$1315_Y
-      attribute \src "ls180.v:4477.6-4477.176"
+    attribute \src "ls180.v:4462.2-4464.5"
+    switch $and$ls180.v:4462$1283_Y
+      attribute \src "ls180.v:4462.6-4462.176"
       case 1'1
-        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4478$1316_Y
+        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4463$1284_Y
       case 
     end
-    attribute \src "ls180.v:4480.2-4482.5"
+    attribute \src "ls180.v:4465.2-4467.5"
     switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:4480.6-4480.53"
+      attribute \src "ls180.v:4465.6-4465.53"
       case 1'1
-        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4481$1317_Y
+        assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4466$1285_Y
       case 
     end
-    attribute \src "ls180.v:4483.2-4491.5"
-    switch $and$ls180.v:4483$1320_Y
-      attribute \src "ls180.v:4483.6-4483.176"
+    attribute \src "ls180.v:4468.2-4476.5"
+    switch $and$ls180.v:4468$1288_Y
+      attribute \src "ls180.v:4468.6-4468.176"
       case 1'1
-        attribute \src "ls180.v:4484.3-4486.6"
-        switch $not$ls180.v:4484$1321_Y
-          attribute \src "ls180.v:4484.7-4484.57"
+        attribute \src "ls180.v:4469.3-4471.6"
+        switch $not$ls180.v:4469$1289_Y
+          attribute \src "ls180.v:4469.7-4469.57"
           case 1'1
-            assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4485$1322_Y
+            assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4470$1290_Y
           case 
         end
-      attribute \src "ls180.v:4487.6-4487.10"
+      attribute \src "ls180.v:4472.6-4472.10"
       case 
-        attribute \src "ls180.v:4488.3-4490.6"
+        attribute \src "ls180.v:4473.3-4475.6"
         switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:4488.7-4488.54"
+          attribute \src "ls180.v:4473.7-4473.54"
           case 1'1
-            assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4489$1323_Y
+            assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4474$1291_Y
           case 
         end
     end
-    attribute \src "ls180.v:4492.2-4498.5"
-    switch $or$ls180.v:4492$1325_Y
-      attribute \src "ls180.v:4492.6-4492.98"
+    attribute \src "ls180.v:4477.2-4483.5"
+    switch $or$ls180.v:4477$1293_Y
+      attribute \src "ls180.v:4477.6-4477.98"
       case 1'1
         assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid
         assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first
@@ -267255,27 +266875,27 @@ module \ls180
         assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:4499.2-4513.5"
+    attribute \src "ls180.v:4484.2-4498.5"
     switch \sdram_bankmachine0_twtpcon_valid
-      attribute \src "ls180.v:4499.6-4499.38"
+      attribute \src "ls180.v:4484.6-4484.38"
       case 1'1
         assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:4501.3-4505.6"
+        attribute \src "ls180.v:4486.3-4490.6"
         switch 1'0
-          attribute \src "ls180.v:4503.7-4503.11"
+          attribute \src "ls180.v:4488.7-4488.11"
           case 
             assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:4506.6-4506.10"
+      attribute \src "ls180.v:4491.6-4491.10"
       case 
-        attribute \src "ls180.v:4507.3-4512.6"
-        switch $not$ls180.v:4507$1326_Y
-          attribute \src "ls180.v:4507.7-4507.42"
+        attribute \src "ls180.v:4492.3-4497.6"
+        switch $not$ls180.v:4492$1294_Y
+          attribute \src "ls180.v:4492.7-4492.42"
           case 1'1
-            assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4508$1327_Y
-            attribute \src "ls180.v:4509.4-4511.7"
-            switch $eq$ls180.v:4509$1328_Y
-              attribute \src "ls180.v:4509.8-4509.50"
+            assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4493$1295_Y
+            attribute \src "ls180.v:4494.4-4496.7"
+            switch $eq$ls180.v:4494$1296_Y
+              attribute \src "ls180.v:4494.8-4494.50"
               case 1'1
                 assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1
               case 
@@ -267283,60 +266903,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4515.2-4522.5"
+    attribute \src "ls180.v:4500.2-4507.5"
     switch \sdram_bankmachine1_row_close
-      attribute \src "ls180.v:4515.6-4515.34"
+      attribute \src "ls180.v:4500.6-4500.34"
       case 1'1
         assign $0\sdram_bankmachine1_row_opened[0:0] 1'0
-      attribute \src "ls180.v:4517.6-4517.10"
+      attribute \src "ls180.v:4502.6-4502.10"
       case 
-        attribute \src "ls180.v:4518.3-4521.6"
+        attribute \src "ls180.v:4503.3-4506.6"
         switch \sdram_bankmachine1_row_open
-          attribute \src "ls180.v:4518.7-4518.34"
+          attribute \src "ls180.v:4503.7-4503.34"
           case 1'1
             assign $0\sdram_bankmachine1_row_opened[0:0] 1'1
             assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:4523.2-4525.5"
-    switch $and$ls180.v:4523$1331_Y
-      attribute \src "ls180.v:4523.6-4523.176"
+    attribute \src "ls180.v:4508.2-4510.5"
+    switch $and$ls180.v:4508$1299_Y
+      attribute \src "ls180.v:4508.6-4508.176"
       case 1'1
-        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4524$1332_Y
+        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4509$1300_Y
       case 
     end
-    attribute \src "ls180.v:4526.2-4528.5"
+    attribute \src "ls180.v:4511.2-4513.5"
     switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:4526.6-4526.53"
+      attribute \src "ls180.v:4511.6-4511.53"
       case 1'1
-        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4527$1333_Y
+        assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4512$1301_Y
       case 
     end
-    attribute \src "ls180.v:4529.2-4537.5"
-    switch $and$ls180.v:4529$1336_Y
-      attribute \src "ls180.v:4529.6-4529.176"
+    attribute \src "ls180.v:4514.2-4522.5"
+    switch $and$ls180.v:4514$1304_Y
+      attribute \src "ls180.v:4514.6-4514.176"
       case 1'1
-        attribute \src "ls180.v:4530.3-4532.6"
-        switch $not$ls180.v:4530$1337_Y
-          attribute \src "ls180.v:4530.7-4530.57"
+        attribute \src "ls180.v:4515.3-4517.6"
+        switch $not$ls180.v:4515$1305_Y
+          attribute \src "ls180.v:4515.7-4515.57"
           case 1'1
-            assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4531$1338_Y
+            assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4516$1306_Y
           case 
         end
-      attribute \src "ls180.v:4533.6-4533.10"
+      attribute \src "ls180.v:4518.6-4518.10"
       case 
-        attribute \src "ls180.v:4534.3-4536.6"
+        attribute \src "ls180.v:4519.3-4521.6"
         switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:4534.7-4534.54"
+          attribute \src "ls180.v:4519.7-4519.54"
           case 1'1
-            assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4535$1339_Y
+            assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4520$1307_Y
           case 
         end
     end
-    attribute \src "ls180.v:4538.2-4544.5"
-    switch $or$ls180.v:4538$1341_Y
-      attribute \src "ls180.v:4538.6-4538.98"
+    attribute \src "ls180.v:4523.2-4529.5"
+    switch $or$ls180.v:4523$1309_Y
+      attribute \src "ls180.v:4523.6-4523.98"
       case 1'1
         assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid
         assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first
@@ -267345,27 +266965,27 @@ module \ls180
         assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:4545.2-4559.5"
+    attribute \src "ls180.v:4530.2-4544.5"
     switch \sdram_bankmachine1_twtpcon_valid
-      attribute \src "ls180.v:4545.6-4545.38"
+      attribute \src "ls180.v:4530.6-4530.38"
       case 1'1
         assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:4547.3-4551.6"
+        attribute \src "ls180.v:4532.3-4536.6"
         switch 1'0
-          attribute \src "ls180.v:4549.7-4549.11"
+          attribute \src "ls180.v:4534.7-4534.11"
           case 
             assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:4552.6-4552.10"
+      attribute \src "ls180.v:4537.6-4537.10"
       case 
-        attribute \src "ls180.v:4553.3-4558.6"
-        switch $not$ls180.v:4553$1342_Y
-          attribute \src "ls180.v:4553.7-4553.42"
+        attribute \src "ls180.v:4538.3-4543.6"
+        switch $not$ls180.v:4538$1310_Y
+          attribute \src "ls180.v:4538.7-4538.42"
           case 1'1
-            assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4554$1343_Y
-            attribute \src "ls180.v:4555.4-4557.7"
-            switch $eq$ls180.v:4555$1344_Y
-              attribute \src "ls180.v:4555.8-4555.50"
+            assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4539$1311_Y
+            attribute \src "ls180.v:4540.4-4542.7"
+            switch $eq$ls180.v:4540$1312_Y
+              attribute \src "ls180.v:4540.8-4540.50"
               case 1'1
                 assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1
               case 
@@ -267373,60 +266993,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4561.2-4568.5"
+    attribute \src "ls180.v:4546.2-4553.5"
     switch \sdram_bankmachine2_row_close
-      attribute \src "ls180.v:4561.6-4561.34"
+      attribute \src "ls180.v:4546.6-4546.34"
       case 1'1
         assign $0\sdram_bankmachine2_row_opened[0:0] 1'0
-      attribute \src "ls180.v:4563.6-4563.10"
+      attribute \src "ls180.v:4548.6-4548.10"
       case 
-        attribute \src "ls180.v:4564.3-4567.6"
+        attribute \src "ls180.v:4549.3-4552.6"
         switch \sdram_bankmachine2_row_open
-          attribute \src "ls180.v:4564.7-4564.34"
+          attribute \src "ls180.v:4549.7-4549.34"
           case 1'1
             assign $0\sdram_bankmachine2_row_opened[0:0] 1'1
             assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:4569.2-4571.5"
-    switch $and$ls180.v:4569$1347_Y
-      attribute \src "ls180.v:4569.6-4569.176"
+    attribute \src "ls180.v:4554.2-4556.5"
+    switch $and$ls180.v:4554$1315_Y
+      attribute \src "ls180.v:4554.6-4554.176"
       case 1'1
-        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4570$1348_Y
+        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4555$1316_Y
       case 
     end
-    attribute \src "ls180.v:4572.2-4574.5"
+    attribute \src "ls180.v:4557.2-4559.5"
     switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:4572.6-4572.53"
+      attribute \src "ls180.v:4557.6-4557.53"
       case 1'1
-        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4573$1349_Y
+        assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4558$1317_Y
       case 
     end
-    attribute \src "ls180.v:4575.2-4583.5"
-    switch $and$ls180.v:4575$1352_Y
-      attribute \src "ls180.v:4575.6-4575.176"
+    attribute \src "ls180.v:4560.2-4568.5"
+    switch $and$ls180.v:4560$1320_Y
+      attribute \src "ls180.v:4560.6-4560.176"
       case 1'1
-        attribute \src "ls180.v:4576.3-4578.6"
-        switch $not$ls180.v:4576$1353_Y
-          attribute \src "ls180.v:4576.7-4576.57"
+        attribute \src "ls180.v:4561.3-4563.6"
+        switch $not$ls180.v:4561$1321_Y
+          attribute \src "ls180.v:4561.7-4561.57"
           case 1'1
-            assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4577$1354_Y
+            assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4562$1322_Y
           case 
         end
-      attribute \src "ls180.v:4579.6-4579.10"
+      attribute \src "ls180.v:4564.6-4564.10"
       case 
-        attribute \src "ls180.v:4580.3-4582.6"
+        attribute \src "ls180.v:4565.3-4567.6"
         switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:4580.7-4580.54"
+          attribute \src "ls180.v:4565.7-4565.54"
           case 1'1
-            assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4581$1355_Y
+            assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4566$1323_Y
           case 
         end
     end
-    attribute \src "ls180.v:4584.2-4590.5"
-    switch $or$ls180.v:4584$1357_Y
-      attribute \src "ls180.v:4584.6-4584.98"
+    attribute \src "ls180.v:4569.2-4575.5"
+    switch $or$ls180.v:4569$1325_Y
+      attribute \src "ls180.v:4569.6-4569.98"
       case 1'1
         assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid
         assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first
@@ -267435,27 +267055,27 @@ module \ls180
         assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:4591.2-4605.5"
+    attribute \src "ls180.v:4576.2-4590.5"
     switch \sdram_bankmachine2_twtpcon_valid
-      attribute \src "ls180.v:4591.6-4591.38"
+      attribute \src "ls180.v:4576.6-4576.38"
       case 1'1
         assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:4593.3-4597.6"
+        attribute \src "ls180.v:4578.3-4582.6"
         switch 1'0
-          attribute \src "ls180.v:4595.7-4595.11"
+          attribute \src "ls180.v:4580.7-4580.11"
           case 
             assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:4598.6-4598.10"
+      attribute \src "ls180.v:4583.6-4583.10"
       case 
-        attribute \src "ls180.v:4599.3-4604.6"
-        switch $not$ls180.v:4599$1358_Y
-          attribute \src "ls180.v:4599.7-4599.42"
+        attribute \src "ls180.v:4584.3-4589.6"
+        switch $not$ls180.v:4584$1326_Y
+          attribute \src "ls180.v:4584.7-4584.42"
           case 1'1
-            assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4600$1359_Y
-            attribute \src "ls180.v:4601.4-4603.7"
-            switch $eq$ls180.v:4601$1360_Y
-              attribute \src "ls180.v:4601.8-4601.50"
+            assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4585$1327_Y
+            attribute \src "ls180.v:4586.4-4588.7"
+            switch $eq$ls180.v:4586$1328_Y
+              attribute \src "ls180.v:4586.8-4586.50"
               case 1'1
                 assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1
               case 
@@ -267463,60 +267083,60 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4607.2-4614.5"
+    attribute \src "ls180.v:4592.2-4599.5"
     switch \sdram_bankmachine3_row_close
-      attribute \src "ls180.v:4607.6-4607.34"
+      attribute \src "ls180.v:4592.6-4592.34"
       case 1'1
         assign $0\sdram_bankmachine3_row_opened[0:0] 1'0
-      attribute \src "ls180.v:4609.6-4609.10"
+      attribute \src "ls180.v:4594.6-4594.10"
       case 
-        attribute \src "ls180.v:4610.3-4613.6"
+        attribute \src "ls180.v:4595.3-4598.6"
         switch \sdram_bankmachine3_row_open
-          attribute \src "ls180.v:4610.7-4610.34"
+          attribute \src "ls180.v:4595.7-4595.34"
           case 1'1
             assign $0\sdram_bankmachine3_row_opened[0:0] 1'1
             assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
           case 
         end
     end
-    attribute \src "ls180.v:4615.2-4617.5"
-    switch $and$ls180.v:4615$1363_Y
-      attribute \src "ls180.v:4615.6-4615.176"
+    attribute \src "ls180.v:4600.2-4602.5"
+    switch $and$ls180.v:4600$1331_Y
+      attribute \src "ls180.v:4600.6-4600.176"
       case 1'1
-        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4616$1364_Y
+        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4601$1332_Y
       case 
     end
-    attribute \src "ls180.v:4618.2-4620.5"
+    attribute \src "ls180.v:4603.2-4605.5"
     switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read
-      attribute \src "ls180.v:4618.6-4618.53"
+      attribute \src "ls180.v:4603.6-4603.53"
       case 1'1
-        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4619$1365_Y
+        assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4604$1333_Y
       case 
     end
-    attribute \src "ls180.v:4621.2-4629.5"
-    switch $and$ls180.v:4621$1368_Y
-      attribute \src "ls180.v:4621.6-4621.176"
+    attribute \src "ls180.v:4606.2-4614.5"
+    switch $and$ls180.v:4606$1336_Y
+      attribute \src "ls180.v:4606.6-4606.176"
       case 1'1
-        attribute \src "ls180.v:4622.3-4624.6"
-        switch $not$ls180.v:4622$1369_Y
-          attribute \src "ls180.v:4622.7-4622.57"
+        attribute \src "ls180.v:4607.3-4609.6"
+        switch $not$ls180.v:4607$1337_Y
+          attribute \src "ls180.v:4607.7-4607.57"
           case 1'1
-            assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4623$1370_Y
+            assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4608$1338_Y
           case 
         end
-      attribute \src "ls180.v:4625.6-4625.10"
+      attribute \src "ls180.v:4610.6-4610.10"
       case 
-        attribute \src "ls180.v:4626.3-4628.6"
+        attribute \src "ls180.v:4611.3-4613.6"
         switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read
-          attribute \src "ls180.v:4626.7-4626.54"
+          attribute \src "ls180.v:4611.7-4611.54"
           case 1'1
-            assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4627$1371_Y
+            assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4612$1339_Y
           case 
         end
     end
-    attribute \src "ls180.v:4630.2-4636.5"
-    switch $or$ls180.v:4630$1373_Y
-      attribute \src "ls180.v:4630.6-4630.98"
+    attribute \src "ls180.v:4615.2-4621.5"
+    switch $or$ls180.v:4615$1341_Y
+      attribute \src "ls180.v:4615.6-4615.98"
       case 1'1
         assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid
         assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first
@@ -267525,27 +267145,27 @@ module \ls180
         assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr
       case 
     end
-    attribute \src "ls180.v:4637.2-4651.5"
+    attribute \src "ls180.v:4622.2-4636.5"
     switch \sdram_bankmachine3_twtpcon_valid
-      attribute \src "ls180.v:4637.6-4637.38"
+      attribute \src "ls180.v:4622.6-4622.38"
       case 1'1
         assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100
-        attribute \src "ls180.v:4639.3-4643.6"
+        attribute \src "ls180.v:4624.3-4628.6"
         switch 1'0
-          attribute \src "ls180.v:4641.7-4641.11"
+          attribute \src "ls180.v:4626.7-4626.11"
           case 
             assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:4644.6-4644.10"
+      attribute \src "ls180.v:4629.6-4629.10"
       case 
-        attribute \src "ls180.v:4645.3-4650.6"
-        switch $not$ls180.v:4645$1374_Y
-          attribute \src "ls180.v:4645.7-4645.42"
+        attribute \src "ls180.v:4630.3-4635.6"
+        switch $not$ls180.v:4630$1342_Y
+          attribute \src "ls180.v:4630.7-4630.42"
           case 1'1
-            assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4646$1375_Y
-            attribute \src "ls180.v:4647.4-4649.7"
-            switch $eq$ls180.v:4647$1376_Y
-              attribute \src "ls180.v:4647.8-4647.50"
+            assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4631$1343_Y
+            attribute \src "ls180.v:4632.4-4634.7"
+            switch $eq$ls180.v:4632$1344_Y
+              attribute \src "ls180.v:4632.8-4632.50"
               case 1'1
                 assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1
               case 
@@ -267553,61 +267173,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4653.2-4659.5"
-    switch $not$ls180.v:4653$1377_Y
-      attribute \src "ls180.v:4653.6-4653.18"
+    attribute \src "ls180.v:4638.2-4644.5"
+    switch $not$ls180.v:4638$1345_Y
+      attribute \src "ls180.v:4638.6-4638.18"
       case 1'1
         assign $0\sdram_time0[4:0] 5'11111
-      attribute \src "ls180.v:4655.6-4655.10"
+      attribute \src "ls180.v:4640.6-4640.10"
       case 
-        attribute \src "ls180.v:4656.3-4658.6"
-        switch $not$ls180.v:4656$1378_Y
-          attribute \src "ls180.v:4656.7-4656.25"
+        attribute \src "ls180.v:4641.3-4643.6"
+        switch $not$ls180.v:4641$1346_Y
+          attribute \src "ls180.v:4641.7-4641.25"
           case 1'1
-            assign $0\sdram_time0[4:0] $sub$ls180.v:4657$1379_Y
+            assign $0\sdram_time0[4:0] $sub$ls180.v:4642$1347_Y
           case 
         end
     end
-    attribute \src "ls180.v:4660.2-4666.5"
-    switch $not$ls180.v:4660$1380_Y
-      attribute \src "ls180.v:4660.6-4660.18"
+    attribute \src "ls180.v:4645.2-4651.5"
+    switch $not$ls180.v:4645$1348_Y
+      attribute \src "ls180.v:4645.6-4645.18"
       case 1'1
         assign $0\sdram_time1[3:0] 4'1111
-      attribute \src "ls180.v:4662.6-4662.10"
+      attribute \src "ls180.v:4647.6-4647.10"
       case 
-        attribute \src "ls180.v:4663.3-4665.6"
-        switch $not$ls180.v:4663$1381_Y
-          attribute \src "ls180.v:4663.7-4663.25"
+        attribute \src "ls180.v:4648.3-4650.6"
+        switch $not$ls180.v:4648$1349_Y
+          attribute \src "ls180.v:4648.7-4648.25"
           case 1'1
-            assign $0\sdram_time1[3:0] $sub$ls180.v:4664$1382_Y
+            assign $0\sdram_time1[3:0] $sub$ls180.v:4649$1350_Y
           case 
         end
     end
-    attribute \src "ls180.v:4667.2-4722.5"
+    attribute \src "ls180.v:4652.2-4707.5"
     switch \sdram_choose_cmd_ce
-      attribute \src "ls180.v:4667.6-4667.25"
+      attribute \src "ls180.v:4652.6-4652.25"
       case 1'1
-        attribute \src "ls180.v:4668.3-4721.10"
+        attribute \src "ls180.v:4653.3-4706.10"
         switch \sdram_choose_cmd_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:4670.5-4680.8"
+            attribute \src "ls180.v:4655.5-4665.8"
             switch \sdram_choose_cmd_request [1]
-              attribute \src "ls180.v:4670.9-4670.36"
+              attribute \src "ls180.v:4655.9-4655.36"
               case 1'1
                 assign $0\sdram_choose_cmd_grant[1:0] 2'01
-              attribute \src "ls180.v:4672.9-4672.13"
+              attribute \src "ls180.v:4657.9-4657.13"
               case 
-                attribute \src "ls180.v:4673.6-4679.9"
+                attribute \src "ls180.v:4658.6-4664.9"
                 switch \sdram_choose_cmd_request [2]
-                  attribute \src "ls180.v:4673.10-4673.37"
+                  attribute \src "ls180.v:4658.10-4658.37"
                   case 1'1
                     assign $0\sdram_choose_cmd_grant[1:0] 2'10
-                  attribute \src "ls180.v:4675.10-4675.14"
+                  attribute \src "ls180.v:4660.10-4660.14"
                   case 
-                    attribute \src "ls180.v:4676.7-4678.10"
+                    attribute \src "ls180.v:4661.7-4663.10"
                     switch \sdram_choose_cmd_request [3]
-                      attribute \src "ls180.v:4676.11-4676.38"
+                      attribute \src "ls180.v:4661.11-4661.38"
                       case 1'1
                         assign $0\sdram_choose_cmd_grant[1:0] 2'11
                       case 
@@ -267616,23 +267236,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:4683.5-4693.8"
+            attribute \src "ls180.v:4668.5-4678.8"
             switch \sdram_choose_cmd_request [2]
-              attribute \src "ls180.v:4683.9-4683.36"
+              attribute \src "ls180.v:4668.9-4668.36"
               case 1'1
                 assign $0\sdram_choose_cmd_grant[1:0] 2'10
-              attribute \src "ls180.v:4685.9-4685.13"
+              attribute \src "ls180.v:4670.9-4670.13"
               case 
-                attribute \src "ls180.v:4686.6-4692.9"
+                attribute \src "ls180.v:4671.6-4677.9"
                 switch \sdram_choose_cmd_request [3]
-                  attribute \src "ls180.v:4686.10-4686.37"
+                  attribute \src "ls180.v:4671.10-4671.37"
                   case 1'1
                     assign $0\sdram_choose_cmd_grant[1:0] 2'11
-                  attribute \src "ls180.v:4688.10-4688.14"
+                  attribute \src "ls180.v:4673.10-4673.14"
                   case 
-                    attribute \src "ls180.v:4689.7-4691.10"
+                    attribute \src "ls180.v:4674.7-4676.10"
                     switch \sdram_choose_cmd_request [0]
-                      attribute \src "ls180.v:4689.11-4689.38"
+                      attribute \src "ls180.v:4674.11-4674.38"
                       case 1'1
                         assign $0\sdram_choose_cmd_grant[1:0] 2'00
                       case 
@@ -267641,23 +267261,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:4696.5-4706.8"
+            attribute \src "ls180.v:4681.5-4691.8"
             switch \sdram_choose_cmd_request [3]
-              attribute \src "ls180.v:4696.9-4696.36"
+              attribute \src "ls180.v:4681.9-4681.36"
               case 1'1
                 assign $0\sdram_choose_cmd_grant[1:0] 2'11
-              attribute \src "ls180.v:4698.9-4698.13"
+              attribute \src "ls180.v:4683.9-4683.13"
               case 
-                attribute \src "ls180.v:4699.6-4705.9"
+                attribute \src "ls180.v:4684.6-4690.9"
                 switch \sdram_choose_cmd_request [0]
-                  attribute \src "ls180.v:4699.10-4699.37"
+                  attribute \src "ls180.v:4684.10-4684.37"
                   case 1'1
                     assign $0\sdram_choose_cmd_grant[1:0] 2'00
-                  attribute \src "ls180.v:4701.10-4701.14"
+                  attribute \src "ls180.v:4686.10-4686.14"
                   case 
-                    attribute \src "ls180.v:4702.7-4704.10"
+                    attribute \src "ls180.v:4687.7-4689.10"
                     switch \sdram_choose_cmd_request [1]
-                      attribute \src "ls180.v:4702.11-4702.38"
+                      attribute \src "ls180.v:4687.11-4687.38"
                       case 1'1
                         assign $0\sdram_choose_cmd_grant[1:0] 2'01
                       case 
@@ -267666,23 +267286,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:4709.5-4719.8"
+            attribute \src "ls180.v:4694.5-4704.8"
             switch \sdram_choose_cmd_request [0]
-              attribute \src "ls180.v:4709.9-4709.36"
+              attribute \src "ls180.v:4694.9-4694.36"
               case 1'1
                 assign $0\sdram_choose_cmd_grant[1:0] 2'00
-              attribute \src "ls180.v:4711.9-4711.13"
+              attribute \src "ls180.v:4696.9-4696.13"
               case 
-                attribute \src "ls180.v:4712.6-4718.9"
+                attribute \src "ls180.v:4697.6-4703.9"
                 switch \sdram_choose_cmd_request [1]
-                  attribute \src "ls180.v:4712.10-4712.37"
+                  attribute \src "ls180.v:4697.10-4697.37"
                   case 1'1
                     assign $0\sdram_choose_cmd_grant[1:0] 2'01
-                  attribute \src "ls180.v:4714.10-4714.14"
+                  attribute \src "ls180.v:4699.10-4699.14"
                   case 
-                    attribute \src "ls180.v:4715.7-4717.10"
+                    attribute \src "ls180.v:4700.7-4702.10"
                     switch \sdram_choose_cmd_request [2]
-                      attribute \src "ls180.v:4715.11-4715.38"
+                      attribute \src "ls180.v:4700.11-4700.38"
                       case 1'1
                         assign $0\sdram_choose_cmd_grant[1:0] 2'10
                       case 
@@ -267693,31 +267313,31 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:4723.2-4778.5"
+    attribute \src "ls180.v:4708.2-4763.5"
     switch \sdram_choose_req_ce
-      attribute \src "ls180.v:4723.6-4723.25"
+      attribute \src "ls180.v:4708.6-4708.25"
       case 1'1
-        attribute \src "ls180.v:4724.3-4777.10"
+        attribute \src "ls180.v:4709.3-4762.10"
         switch \sdram_choose_req_grant
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
-            attribute \src "ls180.v:4726.5-4736.8"
+            attribute \src "ls180.v:4711.5-4721.8"
             switch \sdram_choose_req_request [1]
-              attribute \src "ls180.v:4726.9-4726.36"
+              attribute \src "ls180.v:4711.9-4711.36"
               case 1'1
                 assign $0\sdram_choose_req_grant[1:0] 2'01
-              attribute \src "ls180.v:4728.9-4728.13"
+              attribute \src "ls180.v:4713.9-4713.13"
               case 
-                attribute \src "ls180.v:4729.6-4735.9"
+                attribute \src "ls180.v:4714.6-4720.9"
                 switch \sdram_choose_req_request [2]
-                  attribute \src "ls180.v:4729.10-4729.37"
+                  attribute \src "ls180.v:4714.10-4714.37"
                   case 1'1
                     assign $0\sdram_choose_req_grant[1:0] 2'10
-                  attribute \src "ls180.v:4731.10-4731.14"
+                  attribute \src "ls180.v:4716.10-4716.14"
                   case 
-                    attribute \src "ls180.v:4732.7-4734.10"
+                    attribute \src "ls180.v:4717.7-4719.10"
                     switch \sdram_choose_req_request [3]
-                      attribute \src "ls180.v:4732.11-4732.38"
+                      attribute \src "ls180.v:4717.11-4717.38"
                       case 1'1
                         assign $0\sdram_choose_req_grant[1:0] 2'11
                       case 
@@ -267726,23 +267346,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'01
-            attribute \src "ls180.v:4739.5-4749.8"
+            attribute \src "ls180.v:4724.5-4734.8"
             switch \sdram_choose_req_request [2]
-              attribute \src "ls180.v:4739.9-4739.36"
+              attribute \src "ls180.v:4724.9-4724.36"
               case 1'1
                 assign $0\sdram_choose_req_grant[1:0] 2'10
-              attribute \src "ls180.v:4741.9-4741.13"
+              attribute \src "ls180.v:4726.9-4726.13"
               case 
-                attribute \src "ls180.v:4742.6-4748.9"
+                attribute \src "ls180.v:4727.6-4733.9"
                 switch \sdram_choose_req_request [3]
-                  attribute \src "ls180.v:4742.10-4742.37"
+                  attribute \src "ls180.v:4727.10-4727.37"
                   case 1'1
                     assign $0\sdram_choose_req_grant[1:0] 2'11
-                  attribute \src "ls180.v:4744.10-4744.14"
+                  attribute \src "ls180.v:4729.10-4729.14"
                   case 
-                    attribute \src "ls180.v:4745.7-4747.10"
+                    attribute \src "ls180.v:4730.7-4732.10"
                     switch \sdram_choose_req_request [0]
-                      attribute \src "ls180.v:4745.11-4745.38"
+                      attribute \src "ls180.v:4730.11-4730.38"
                       case 1'1
                         assign $0\sdram_choose_req_grant[1:0] 2'00
                       case 
@@ -267751,23 +267371,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'10
-            attribute \src "ls180.v:4752.5-4762.8"
+            attribute \src "ls180.v:4737.5-4747.8"
             switch \sdram_choose_req_request [3]
-              attribute \src "ls180.v:4752.9-4752.36"
+              attribute \src "ls180.v:4737.9-4737.36"
               case 1'1
                 assign $0\sdram_choose_req_grant[1:0] 2'11
-              attribute \src "ls180.v:4754.9-4754.13"
+              attribute \src "ls180.v:4739.9-4739.13"
               case 
-                attribute \src "ls180.v:4755.6-4761.9"
+                attribute \src "ls180.v:4740.6-4746.9"
                 switch \sdram_choose_req_request [0]
-                  attribute \src "ls180.v:4755.10-4755.37"
+                  attribute \src "ls180.v:4740.10-4740.37"
                   case 1'1
                     assign $0\sdram_choose_req_grant[1:0] 2'00
-                  attribute \src "ls180.v:4757.10-4757.14"
+                  attribute \src "ls180.v:4742.10-4742.14"
                   case 
-                    attribute \src "ls180.v:4758.7-4760.10"
+                    attribute \src "ls180.v:4743.7-4745.10"
                     switch \sdram_choose_req_request [1]
-                      attribute \src "ls180.v:4758.11-4758.38"
+                      attribute \src "ls180.v:4743.11-4743.38"
                       case 1'1
                         assign $0\sdram_choose_req_grant[1:0] 2'01
                       case 
@@ -267776,23 +267396,23 @@ module \ls180
             end
           attribute \src "ls180.v:0.0-0.0"
           case 2'11
-            attribute \src "ls180.v:4765.5-4775.8"
+            attribute \src "ls180.v:4750.5-4760.8"
             switch \sdram_choose_req_request [0]
-              attribute \src "ls180.v:4765.9-4765.36"
+              attribute \src "ls180.v:4750.9-4750.36"
               case 1'1
                 assign $0\sdram_choose_req_grant[1:0] 2'00
-              attribute \src "ls180.v:4767.9-4767.13"
+              attribute \src "ls180.v:4752.9-4752.13"
               case 
-                attribute \src "ls180.v:4768.6-4774.9"
+                attribute \src "ls180.v:4753.6-4759.9"
                 switch \sdram_choose_req_request [1]
-                  attribute \src "ls180.v:4768.10-4768.37"
+                  attribute \src "ls180.v:4753.10-4753.37"
                   case 1'1
                     assign $0\sdram_choose_req_grant[1:0] 2'01
-                  attribute \src "ls180.v:4770.10-4770.14"
+                  attribute \src "ls180.v:4755.10-4755.14"
                   case 
-                    attribute \src "ls180.v:4771.7-4773.10"
+                    attribute \src "ls180.v:4756.7-4758.10"
                     switch \sdram_choose_req_request [2]
-                      attribute \src "ls180.v:4771.11-4771.38"
+                      attribute \src "ls180.v:4756.11-4756.38"
                       case 1'1
                         assign $0\sdram_choose_req_grant[1:0] 2'10
                       case 
@@ -267803,28 +267423,28 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:4787.2-4801.5"
+    attribute \src "ls180.v:4772.2-4786.5"
     switch \sdram_tccdcon_valid
-      attribute \src "ls180.v:4787.6-4787.25"
+      attribute \src "ls180.v:4772.6-4772.25"
       case 1'1
         assign $0\sdram_tccdcon_count[0:0] 1'0
-        attribute \src "ls180.v:4789.3-4793.6"
+        attribute \src "ls180.v:4774.3-4778.6"
         switch 1'1
-          attribute \src "ls180.v:4789.7-4789.11"
+          attribute \src "ls180.v:4774.7-4774.11"
           case 1'1
             assign $0\sdram_tccdcon_ready[0:0] 1'1
           case 
         end
-      attribute \src "ls180.v:4794.6-4794.10"
+      attribute \src "ls180.v:4779.6-4779.10"
       case 
-        attribute \src "ls180.v:4795.3-4800.6"
-        switch $not$ls180.v:4795$1386_Y
-          attribute \src "ls180.v:4795.7-4795.29"
+        attribute \src "ls180.v:4780.3-4785.6"
+        switch $not$ls180.v:4780$1354_Y
+          attribute \src "ls180.v:4780.7-4780.29"
           case 1'1
-            assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4796$1387_Y
-            attribute \src "ls180.v:4797.4-4799.7"
-            switch $eq$ls180.v:4797$1388_Y
-              attribute \src "ls180.v:4797.8-4797.37"
+            assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4781$1355_Y
+            attribute \src "ls180.v:4782.4-4784.7"
+            switch $eq$ls180.v:4782$1356_Y
+              attribute \src "ls180.v:4782.8-4782.37"
               case 1'1
                 assign $0\sdram_tccdcon_ready[0:0] 1'1
               case 
@@ -267832,27 +267452,27 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4802.2-4816.5"
+    attribute \src "ls180.v:4787.2-4801.5"
     switch \sdram_twtrcon_valid
-      attribute \src "ls180.v:4802.6-4802.25"
+      attribute \src "ls180.v:4787.6-4787.25"
       case 1'1
         assign $0\sdram_twtrcon_count[2:0] 3'100
-        attribute \src "ls180.v:4804.3-4808.6"
+        attribute \src "ls180.v:4789.3-4793.6"
         switch 1'0
-          attribute \src "ls180.v:4806.7-4806.11"
+          attribute \src "ls180.v:4791.7-4791.11"
           case 
             assign $0\sdram_twtrcon_ready[0:0] 1'0
         end
-      attribute \src "ls180.v:4809.6-4809.10"
+      attribute \src "ls180.v:4794.6-4794.10"
       case 
-        attribute \src "ls180.v:4810.3-4815.6"
-        switch $not$ls180.v:4810$1389_Y
-          attribute \src "ls180.v:4810.7-4810.29"
+        attribute \src "ls180.v:4795.3-4800.6"
+        switch $not$ls180.v:4795$1357_Y
+          attribute \src "ls180.v:4795.7-4795.29"
           case 1'1
-            assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4811$1390_Y
-            attribute \src "ls180.v:4812.4-4814.7"
-            switch $eq$ls180.v:4812$1391_Y
-              attribute \src "ls180.v:4812.8-4812.37"
+            assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4796$1358_Y
+            attribute \src "ls180.v:4797.4-4799.7"
+            switch $eq$ls180.v:4797$1359_Y
+              attribute \src "ls180.v:4797.8-4797.37"
               case 1'1
                 assign $0\sdram_twtrcon_ready[0:0] 1'1
               case 
@@ -267860,81 +267480,81 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4823.2-4825.5"
-    switch $or$ls180.v:4823$1416_Y
-      attribute \src "ls180.v:4823.6-4823.40"
+    attribute \src "ls180.v:4808.2-4810.5"
+    switch $or$ls180.v:4808$1384_Y
+      attribute \src "ls180.v:4808.6-4808.40"
       case 1'1
         assign $0\converter_dat_r[31:0] \wb_sdram_dat_r
       case 
     end
-    attribute \src "ls180.v:4827.2-4829.5"
+    attribute \src "ls180.v:4812.2-4814.5"
     switch \converter_counter_subfragments_next_value_ce
-      attribute \src "ls180.v:4827.6-4827.50"
+      attribute \src "ls180.v:4812.6-4812.50"
       case 1'1
         assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value
       case 
     end
-    attribute \src "ls180.v:4830.2-4833.5"
+    attribute \src "ls180.v:4815.2-4818.5"
     switch \converter_reset
-      attribute \src "ls180.v:4830.6-4830.21"
+      attribute \src "ls180.v:4815.6-4815.21"
       case 1'1
         assign $0\converter_counter[0:0] 1'0
         assign $0\subfragments_state[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4834.2-4844.5"
+    attribute \src "ls180.v:4819.2-4829.5"
     switch \litedram_wb_ack
-      attribute \src "ls180.v:4834.6-4834.21"
+      attribute \src "ls180.v:4819.6-4819.21"
       case 1'1
         assign $0\cmd_consumed[0:0] 1'0
         assign $0\wdata_consumed[0:0] 1'0
-      attribute \src "ls180.v:4837.6-4837.10"
+      attribute \src "ls180.v:4822.6-4822.10"
       case 
-        attribute \src "ls180.v:4838.3-4840.6"
-        switch $and$ls180.v:4838$1417_Y
-          attribute \src "ls180.v:4838.7-4838.40"
+        attribute \src "ls180.v:4823.3-4825.6"
+        switch $and$ls180.v:4823$1385_Y
+          attribute \src "ls180.v:4823.7-4823.40"
           case 1'1
             assign $0\cmd_consumed[0:0] 1'1
           case 
         end
-        attribute \src "ls180.v:4841.3-4843.6"
-        switch $and$ls180.v:4841$1418_Y
-          attribute \src "ls180.v:4841.7-4841.44"
+        attribute \src "ls180.v:4826.3-4828.6"
+        switch $and$ls180.v:4826$1386_Y
+          attribute \src "ls180.v:4826.7-4826.44"
           case 1'1
             assign $0\wdata_consumed[0:0] 1'1
           case 
         end
     end
-    attribute \src "ls180.v:4846.2-4867.5"
-    switch $and$ls180.v:4846$1422_Y
-      attribute \src "ls180.v:4846.6-4846.76"
+    attribute \src "ls180.v:4831.2-4852.5"
+    switch $and$ls180.v:4831$1390_Y
+      attribute \src "ls180.v:4831.6-4831.76"
       case 1'1
         assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data
         assign $0\uart_phy_tx_bitcount[3:0] 4'0000
         assign $0\uart_phy_tx_busy[0:0] 1'1
         assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'0
-      attribute \src "ls180.v:4851.6-4851.10"
+      attribute \src "ls180.v:4836.6-4836.10"
       case 
-        attribute \src "ls180.v:4852.3-4866.6"
-        switch $and$ls180.v:4852$1423_Y
-          attribute \src "ls180.v:4852.7-4852.50"
+        attribute \src "ls180.v:4837.3-4851.6"
+        switch $and$ls180.v:4837$1391_Y
+          attribute \src "ls180.v:4837.7-4837.50"
           case 1'1
-            assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4853$1424_Y
-            attribute \src "ls180.v:4854.4-4865.7"
-            switch $eq$ls180.v:4854$1425_Y
-              attribute \src "ls180.v:4854.8-4854.38"
+            assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4838$1392_Y
+            attribute \src "ls180.v:4839.4-4850.7"
+            switch $eq$ls180.v:4839$1393_Y
+              attribute \src "ls180.v:4839.8-4839.38"
               case 1'1
                 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
-              attribute \src "ls180.v:4856.8-4856.12"
+              attribute \src "ls180.v:4841.8-4841.12"
               case 
-                attribute \src "ls180.v:4857.5-4864.8"
-                switch $eq$ls180.v:4857$1426_Y
-                  attribute \src "ls180.v:4857.9-4857.39"
+                attribute \src "ls180.v:4842.5-4849.8"
+                switch $eq$ls180.v:4842$1394_Y
+                  attribute \src "ls180.v:4842.9-4842.39"
                   case 1'1
                     assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
                     assign $0\uart_phy_tx_busy[0:0] 1'0
                     assign $0\uart_phy_sink_ready[0:0] 1'1
-                  attribute \src "ls180.v:4861.9-4861.13"
+                  attribute \src "ls180.v:4846.9-4846.13"
                   case 
                     assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \uart_phy_tx_reg [0]
                     assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] }
@@ -267943,61 +267563,61 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4868.2-4872.5"
+    attribute \src "ls180.v:4853.2-4857.5"
     switch \uart_phy_tx_busy
-      attribute \src "ls180.v:4868.6-4868.22"
+      attribute \src "ls180.v:4853.6-4853.22"
       case 1'1
-        assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4869$1427_Y
-      attribute \src "ls180.v:4870.6-4870.10"
+        assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4854$1395_Y
+      attribute \src "ls180.v:4855.6-4855.10"
       case 
         assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage }
     end
-    attribute \src "ls180.v:4875.2-4899.5"
-    switch $not$ls180.v:4875$1428_Y
-      attribute \src "ls180.v:4875.6-4875.25"
+    attribute \src "ls180.v:4860.2-4884.5"
+    switch $not$ls180.v:4860$1396_Y
+      attribute \src "ls180.v:4860.6-4860.25"
       case 1'1
-        attribute \src "ls180.v:4876.3-4879.6"
-        switch $and$ls180.v:4876$1430_Y
-          attribute \src "ls180.v:4876.7-4876.39"
+        attribute \src "ls180.v:4861.3-4864.6"
+        switch $and$ls180.v:4861$1398_Y
+          attribute \src "ls180.v:4861.7-4861.39"
           case 1'1
             assign $0\uart_phy_rx_busy[0:0] 1'1
             assign $0\uart_phy_rx_bitcount[3:0] 4'0000
           case 
         end
-      attribute \src "ls180.v:4880.6-4880.10"
+      attribute \src "ls180.v:4865.6-4865.10"
       case 
-        attribute \src "ls180.v:4881.3-4898.6"
+        attribute \src "ls180.v:4866.3-4883.6"
         switch \uart_phy_uart_clk_rxen
-          attribute \src "ls180.v:4881.7-4881.29"
+          attribute \src "ls180.v:4866.7-4866.29"
           case 1'1
-            assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4882$1431_Y
-            attribute \src "ls180.v:4883.4-4897.7"
-            switch $eq$ls180.v:4883$1432_Y
-              attribute \src "ls180.v:4883.8-4883.38"
+            assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4867$1399_Y
+            attribute \src "ls180.v:4868.4-4882.7"
+            switch $eq$ls180.v:4868$1400_Y
+              attribute \src "ls180.v:4868.8-4868.38"
               case 1'1
-                attribute \src "ls180.v:4884.5-4886.8"
+                attribute \src "ls180.v:4869.5-4871.8"
                 switch \uart_phy_rx
-                  attribute \src "ls180.v:4884.9-4884.20"
+                  attribute \src "ls180.v:4869.9-4869.20"
                   case 1'1
                     assign $0\uart_phy_rx_busy[0:0] 1'0
                   case 
                 end
-              attribute \src "ls180.v:4887.8-4887.12"
+              attribute \src "ls180.v:4872.8-4872.12"
               case 
-                attribute \src "ls180.v:4888.5-4896.8"
-                switch $eq$ls180.v:4888$1433_Y
-                  attribute \src "ls180.v:4888.9-4888.39"
+                attribute \src "ls180.v:4873.5-4881.8"
+                switch $eq$ls180.v:4873$1401_Y
+                  attribute \src "ls180.v:4873.9-4873.39"
                   case 1'1
                     assign $0\uart_phy_rx_busy[0:0] 1'0
-                    attribute \src "ls180.v:4890.6-4893.9"
+                    attribute \src "ls180.v:4875.6-4878.9"
                     switch \uart_phy_rx
-                      attribute \src "ls180.v:4890.10-4890.21"
+                      attribute \src "ls180.v:4875.10-4875.21"
                       case 1'1
                         assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg
                         assign $0\uart_phy_source_valid[0:0] 1'1
                       case 
                     end
-                  attribute \src "ls180.v:4894.9-4894.13"
+                  attribute \src "ls180.v:4879.9-4879.13"
                   case 
                     assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] }
                 end
@@ -268005,146 +267625,146 @@ module \ls180
           case 
         end
     end
-    attribute \src "ls180.v:4900.2-4904.5"
+    attribute \src "ls180.v:4885.2-4889.5"
     switch \uart_phy_rx_busy
-      attribute \src "ls180.v:4900.6-4900.22"
+      attribute \src "ls180.v:4885.6-4885.22"
       case 1'1
-        assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4901$1434_Y
-      attribute \src "ls180.v:4902.6-4902.10"
+        assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4886$1402_Y
+      attribute \src "ls180.v:4887.6-4887.10"
       case 
         assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
     end
-    attribute \src "ls180.v:4905.2-4907.5"
+    attribute \src "ls180.v:4890.2-4892.5"
     switch \tx_clear
-      attribute \src "ls180.v:4905.6-4905.14"
+      attribute \src "ls180.v:4890.6-4890.14"
       case 1'1
         assign $0\tx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4909.2-4911.5"
-    switch $and$ls180.v:4909$1436_Y
-      attribute \src "ls180.v:4909.6-4909.38"
+    attribute \src "ls180.v:4894.2-4896.5"
+    switch $and$ls180.v:4894$1404_Y
+      attribute \src "ls180.v:4894.6-4894.38"
       case 1'1
         assign $0\tx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4912.2-4914.5"
+    attribute \src "ls180.v:4897.2-4899.5"
     switch \rx_clear
-      attribute \src "ls180.v:4912.6-4912.14"
+      attribute \src "ls180.v:4897.6-4897.14"
       case 1'1
         assign $0\rx_pending[0:0] 1'0
       case 
     end
-    attribute \src "ls180.v:4916.2-4918.5"
-    switch $and$ls180.v:4916$1438_Y
-      attribute \src "ls180.v:4916.6-4916.38"
+    attribute \src "ls180.v:4901.2-4903.5"
+    switch $and$ls180.v:4901$1406_Y
+      attribute \src "ls180.v:4901.6-4901.38"
       case 1'1
         assign $0\rx_pending[0:0] 1'1
       case 
     end
-    attribute \src "ls180.v:4919.2-4925.5"
+    attribute \src "ls180.v:4904.2-4910.5"
     switch \tx_fifo_syncfifo_re
-      attribute \src "ls180.v:4919.6-4919.25"
+      attribute \src "ls180.v:4904.6-4904.25"
       case 1'1
         assign $0\tx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:4921.6-4921.10"
+      attribute \src "ls180.v:4906.6-4906.10"
       case 
-        attribute \src "ls180.v:4922.3-4924.6"
+        attribute \src "ls180.v:4907.3-4909.6"
         switch \tx_fifo_re
-          attribute \src "ls180.v:4922.7-4922.17"
+          attribute \src "ls180.v:4907.7-4907.17"
           case 1'1
             assign $0\tx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:4926.2-4928.5"
-    switch $and$ls180.v:4926$1441_Y
-      attribute \src "ls180.v:4926.6-4926.78"
+    attribute \src "ls180.v:4911.2-4913.5"
+    switch $and$ls180.v:4911$1409_Y
+      attribute \src "ls180.v:4911.6-4911.78"
       case 1'1
-        assign $0\tx_fifo_produce[3:0] $add$ls180.v:4927$1442_Y
+        assign $0\tx_fifo_produce[3:0] $add$ls180.v:4912$1410_Y
       case 
     end
-    attribute \src "ls180.v:4929.2-4931.5"
+    attribute \src "ls180.v:4914.2-4916.5"
     switch \tx_fifo_do_read
-      attribute \src "ls180.v:4929.6-4929.21"
+      attribute \src "ls180.v:4914.6-4914.21"
       case 1'1
-        assign $0\tx_fifo_consume[3:0] $add$ls180.v:4930$1443_Y
+        assign $0\tx_fifo_consume[3:0] $add$ls180.v:4915$1411_Y
       case 
     end
-    attribute \src "ls180.v:4932.2-4940.5"
-    switch $and$ls180.v:4932$1446_Y
-      attribute \src "ls180.v:4932.6-4932.78"
+    attribute \src "ls180.v:4917.2-4925.5"
+    switch $and$ls180.v:4917$1414_Y
+      attribute \src "ls180.v:4917.6-4917.78"
       case 1'1
-        attribute \src "ls180.v:4933.3-4935.6"
-        switch $not$ls180.v:4933$1447_Y
-          attribute \src "ls180.v:4933.7-4933.25"
+        attribute \src "ls180.v:4918.3-4920.6"
+        switch $not$ls180.v:4918$1415_Y
+          attribute \src "ls180.v:4918.7-4918.25"
           case 1'1
-            assign $0\tx_fifo_level0[4:0] $add$ls180.v:4934$1448_Y
+            assign $0\tx_fifo_level0[4:0] $add$ls180.v:4919$1416_Y
           case 
         end
-      attribute \src "ls180.v:4936.6-4936.10"
+      attribute \src "ls180.v:4921.6-4921.10"
       case 
-        attribute \src "ls180.v:4937.3-4939.6"
+        attribute \src "ls180.v:4922.3-4924.6"
         switch \tx_fifo_do_read
-          attribute \src "ls180.v:4937.7-4937.22"
+          attribute \src "ls180.v:4922.7-4922.22"
           case 1'1
-            assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4938$1449_Y
+            assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4923$1417_Y
           case 
         end
     end
-    attribute \src "ls180.v:4941.2-4947.5"
+    attribute \src "ls180.v:4926.2-4932.5"
     switch \rx_fifo_syncfifo_re
-      attribute \src "ls180.v:4941.6-4941.25"
+      attribute \src "ls180.v:4926.6-4926.25"
       case 1'1
         assign $0\rx_fifo_readable[0:0] 1'1
-      attribute \src "ls180.v:4943.6-4943.10"
+      attribute \src "ls180.v:4928.6-4928.10"
       case 
-        attribute \src "ls180.v:4944.3-4946.6"
+        attribute \src "ls180.v:4929.3-4931.6"
         switch \rx_fifo_re
-          attribute \src "ls180.v:4944.7-4944.17"
+          attribute \src "ls180.v:4929.7-4929.17"
           case 1'1
             assign $0\rx_fifo_readable[0:0] 1'0
           case 
         end
     end
-    attribute \src "ls180.v:4948.2-4950.5"
-    switch $and$ls180.v:4948$1452_Y
-      attribute \src "ls180.v:4948.6-4948.78"
+    attribute \src "ls180.v:4933.2-4935.5"
+    switch $and$ls180.v:4933$1420_Y
+      attribute \src "ls180.v:4933.6-4933.78"
       case 1'1
-        assign $0\rx_fifo_produce[3:0] $add$ls180.v:4949$1453_Y
+        assign $0\rx_fifo_produce[3:0] $add$ls180.v:4934$1421_Y
       case 
     end
-    attribute \src "ls180.v:4951.2-4953.5"
+    attribute \src "ls180.v:4936.2-4938.5"
     switch \rx_fifo_do_read
-      attribute \src "ls180.v:4951.6-4951.21"
+      attribute \src "ls180.v:4936.6-4936.21"
       case 1'1
-        assign $0\rx_fifo_consume[3:0] $add$ls180.v:4952$1454_Y
+        assign $0\rx_fifo_consume[3:0] $add$ls180.v:4937$1422_Y
       case 
     end
-    attribute \src "ls180.v:4954.2-4962.5"
-    switch $and$ls180.v:4954$1457_Y
-      attribute \src "ls180.v:4954.6-4954.78"
+    attribute \src "ls180.v:4939.2-4947.5"
+    switch $and$ls180.v:4939$1425_Y
+      attribute \src "ls180.v:4939.6-4939.78"
       case 1'1
-        attribute \src "ls180.v:4955.3-4957.6"
-        switch $not$ls180.v:4955$1458_Y
-          attribute \src "ls180.v:4955.7-4955.25"
+        attribute \src "ls180.v:4940.3-4942.6"
+        switch $not$ls180.v:4940$1426_Y
+          attribute \src "ls180.v:4940.7-4940.25"
           case 1'1
-            assign $0\rx_fifo_level0[4:0] $add$ls180.v:4956$1459_Y
+            assign $0\rx_fifo_level0[4:0] $add$ls180.v:4941$1427_Y
           case 
         end
-      attribute \src "ls180.v:4958.6-4958.10"
+      attribute \src "ls180.v:4943.6-4943.10"
       case 
-        attribute \src "ls180.v:4959.3-4961.6"
+        attribute \src "ls180.v:4944.3-4946.6"
         switch \rx_fifo_do_read
-          attribute \src "ls180.v:4959.7-4959.22"
+          attribute \src "ls180.v:4944.7-4944.22"
           case 1'1
-            assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4960$1460_Y
+            assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4945$1428_Y
           case 
         end
     end
-    attribute \src "ls180.v:4963.2-4976.5"
+    attribute \src "ls180.v:4948.2-4961.5"
     switch \reset
-      attribute \src "ls180.v:4963.6-4963.11"
+      attribute \src "ls180.v:4948.6-4948.11"
       case 1'1
         assign $0\tx_pending[0:0] 1'0
         assign $0\tx_old_trigger[0:0] 1'0
@@ -268160,45 +267780,45 @@ module \ls180
         assign $0\rx_fifo_consume[3:0] 4'0000
       case 
     end
-    attribute \src "ls180.v:4978.2-4980.5"
+    attribute \src "ls180.v:4963.2-4965.5"
     switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0
-      attribute \src "ls180.v:4978.6-4978.62"
+      attribute \src "ls180.v:4963.6-4963.62"
       case 1'1
         assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0
       case 
     end
-    attribute \src "ls180.v:4981.2-4983.5"
+    attribute \src "ls180.v:4966.2-4968.5"
     switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1
-      attribute \src "ls180.v:4981.6-4981.60"
+      attribute \src "ls180.v:4966.6-4966.60"
       case 1'1
         assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1
       case 
     end
-    attribute \src "ls180.v:4984.2-4986.5"
+    attribute \src "ls180.v:4969.2-4971.5"
     switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2
-      attribute \src "ls180.v:4984.6-4984.59"
+      attribute \src "ls180.v:4969.6-4969.59"
       case 1'1
         assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2
       case 
     end
-    attribute \src "ls180.v:4987.2-5021.9"
+    attribute \src "ls180.v:4972.2-5006.9"
     switch \libresocsim_grant
       attribute \src "ls180.v:0.0-0.0"
       case 2'00
-        attribute \src "ls180.v:4989.4-4997.7"
-        switch $not$ls180.v:4989$1461_Y
-          attribute \src "ls180.v:4989.8-4989.33"
+        attribute \src "ls180.v:4974.4-4982.7"
+        switch $not$ls180.v:4974$1429_Y
+          attribute \src "ls180.v:4974.8-4974.33"
           case 1'1
-            attribute \src "ls180.v:4990.5-4996.8"
+            attribute \src "ls180.v:4975.5-4981.8"
             switch \libresocsim_request [1]
-              attribute \src "ls180.v:4990.9-4990.31"
+              attribute \src "ls180.v:4975.9-4975.31"
               case 1'1
                 assign $0\libresocsim_grant[1:0] 2'01
-              attribute \src "ls180.v:4992.9-4992.13"
+              attribute \src "ls180.v:4977.9-4977.13"
               case 
-                attribute \src "ls180.v:4993.6-4995.9"
+                attribute \src "ls180.v:4978.6-4980.9"
                 switch \libresocsim_request [2]
-                  attribute \src "ls180.v:4993.10-4993.32"
+                  attribute \src "ls180.v:4978.10-4978.32"
                   case 1'1
                     assign $0\libresocsim_grant[1:0] 2'10
                   case 
@@ -268208,20 +267828,20 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 2'01
-        attribute \src "ls180.v:5000.4-5008.7"
-        switch $not$ls180.v:5000$1462_Y
-          attribute \src "ls180.v:5000.8-5000.33"
+        attribute \src "ls180.v:4985.4-4993.7"
+        switch $not$ls180.v:4985$1430_Y
+          attribute \src "ls180.v:4985.8-4985.33"
           case 1'1
-            attribute \src "ls180.v:5001.5-5007.8"
+            attribute \src "ls180.v:4986.5-4992.8"
             switch \libresocsim_request [2]
-              attribute \src "ls180.v:5001.9-5001.31"
+              attribute \src "ls180.v:4986.9-4986.31"
               case 1'1
                 assign $0\libresocsim_grant[1:0] 2'10
-              attribute \src "ls180.v:5003.9-5003.13"
+              attribute \src "ls180.v:4988.9-4988.13"
               case 
-                attribute \src "ls180.v:5004.6-5006.9"
+                attribute \src "ls180.v:4989.6-4991.9"
                 switch \libresocsim_request [0]
-                  attribute \src "ls180.v:5004.10-5004.32"
+                  attribute \src "ls180.v:4989.10-4989.32"
                   case 1'1
                     assign $0\libresocsim_grant[1:0] 2'00
                   case 
@@ -268231,20 +267851,20 @@ module \ls180
         end
       attribute \src "ls180.v:0.0-0.0"
       case 2'10
-        attribute \src "ls180.v:5011.4-5019.7"
-        switch $not$ls180.v:5011$1463_Y
-          attribute \src "ls180.v:5011.8-5011.33"
+        attribute \src "ls180.v:4996.4-5004.7"
+        switch $not$ls180.v:4996$1431_Y
+          attribute \src "ls180.v:4996.8-4996.33"
           case 1'1
-            attribute \src "ls180.v:5012.5-5018.8"
+            attribute \src "ls180.v:4997.5-5003.8"
             switch \libresocsim_request [0]
-              attribute \src "ls180.v:5012.9-5012.31"
+              attribute \src "ls180.v:4997.9-4997.31"
               case 1'1
                 assign $0\libresocsim_grant[1:0] 2'00
-              attribute \src "ls180.v:5014.9-5014.13"
+              attribute \src "ls180.v:4999.9-4999.13"
               case 
-                attribute \src "ls180.v:5015.6-5017.9"
+                attribute \src "ls180.v:5000.6-5002.9"
                 switch \libresocsim_request [1]
-                  attribute \src "ls180.v:5015.10-5015.32"
+                  attribute \src "ls180.v:5000.10-5000.32"
                   case 1'1
                     assign $0\libresocsim_grant[1:0] 2'01
                   case 
@@ -268254,26 +267874,26 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5023.2-5029.5"
+    attribute \src "ls180.v:5008.2-5014.5"
     switch \libresocsim_wait
-      attribute \src "ls180.v:5023.6-5023.22"
+      attribute \src "ls180.v:5008.6-5008.22"
       case 1'1
-        attribute \src "ls180.v:5024.3-5026.6"
-        switch $not$ls180.v:5024$1464_Y
-          attribute \src "ls180.v:5024.7-5024.26"
+        attribute \src "ls180.v:5009.3-5011.6"
+        switch $not$ls180.v:5009$1432_Y
+          attribute \src "ls180.v:5009.7-5009.26"
           case 1'1
-            assign $0\libresocsim_count[19:0] $sub$ls180.v:5025$1465_Y
+            assign $0\libresocsim_count[19:0] $sub$ls180.v:5010$1433_Y
           case 
         end
-      attribute \src "ls180.v:5027.6-5027.10"
+      attribute \src "ls180.v:5012.6-5012.10"
       case 
         assign $0\libresocsim_count[19:0] 20'11110100001001000000
     end
-    attribute \src "ls180.v:5031.2-5061.5"
+    attribute \src "ls180.v:5016.2-5046.5"
     switch \libresocsim_csrbank0_sel
-      attribute \src "ls180.v:5031.6-5031.30"
+      attribute \src "ls180.v:5016.6-5016.30"
       case 1'1
-        attribute \src "ls180.v:5032.3-5060.10"
+        attribute \src "ls180.v:5017.3-5045.10"
         switch \libresocsim_interface0_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -268306,46 +267926,46 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5062.2-5064.5"
+    attribute \src "ls180.v:5047.2-5049.5"
     switch \libresocsim_csrbank0_reset0_re
-      attribute \src "ls180.v:5062.6-5062.36"
+      attribute \src "ls180.v:5047.6-5047.36"
       case 1'1
         assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r
       case 
     end
-    attribute \src "ls180.v:5066.2-5068.5"
+    attribute \src "ls180.v:5051.2-5053.5"
     switch \libresocsim_csrbank0_scratch3_re
-      attribute \src "ls180.v:5066.6-5066.38"
+      attribute \src "ls180.v:5051.6-5051.38"
       case 1'1
         assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r
       case 
     end
-    attribute \src "ls180.v:5069.2-5071.5"
+    attribute \src "ls180.v:5054.2-5056.5"
     switch \libresocsim_csrbank0_scratch2_re
-      attribute \src "ls180.v:5069.6-5069.38"
+      attribute \src "ls180.v:5054.6-5054.38"
       case 1'1
         assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r
       case 
     end
-    attribute \src "ls180.v:5072.2-5074.5"
+    attribute \src "ls180.v:5057.2-5059.5"
     switch \libresocsim_csrbank0_scratch1_re
-      attribute \src "ls180.v:5072.6-5072.38"
+      attribute \src "ls180.v:5057.6-5057.38"
       case 1'1
         assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r
       case 
     end
-    attribute \src "ls180.v:5075.2-5077.5"
+    attribute \src "ls180.v:5060.2-5062.5"
     switch \libresocsim_csrbank0_scratch0_re
-      attribute \src "ls180.v:5075.6-5075.38"
+      attribute \src "ls180.v:5060.6-5060.38"
       case 1'1
         assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r
       case 
     end
-    attribute \src "ls180.v:5080.2-5092.5"
+    attribute \src "ls180.v:5065.2-5077.5"
     switch \libresocsim_csrbank1_sel
-      attribute \src "ls180.v:5080.6-5080.30"
+      attribute \src "ls180.v:5065.6-5065.30"
       case 1'1
-        attribute \src "ls180.v:5081.3-5091.10"
+        attribute \src "ls180.v:5066.3-5076.10"
         switch \libresocsim_interface1_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -268360,25 +267980,25 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5093.2-5095.5"
+    attribute \src "ls180.v:5078.2-5080.5"
     switch \libresocsim_csrbank1_oe0_re
-      attribute \src "ls180.v:5093.6-5093.33"
+      attribute \src "ls180.v:5078.6-5078.33"
       case 1'1
         assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r
       case 
     end
-    attribute \src "ls180.v:5097.2-5099.5"
+    attribute \src "ls180.v:5082.2-5084.5"
     switch \libresocsim_csrbank1_out0_re
-      attribute \src "ls180.v:5097.6-5097.34"
+      attribute \src "ls180.v:5082.6-5082.34"
       case 1'1
         assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r
       case 
     end
-    attribute \src "ls180.v:5102.2-5114.5"
+    attribute \src "ls180.v:5087.2-5099.5"
     switch \libresocsim_csrbank2_sel
-      attribute \src "ls180.v:5102.6-5102.30"
+      attribute \src "ls180.v:5087.6-5087.30"
       case 1'1
-        attribute \src "ls180.v:5103.3-5113.10"
+        attribute \src "ls180.v:5088.3-5098.10"
         switch \libresocsim_interface2_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -268393,25 +268013,25 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5115.2-5117.5"
+    attribute \src "ls180.v:5100.2-5102.5"
     switch \libresocsim_csrbank2_oe0_re
-      attribute \src "ls180.v:5115.6-5115.33"
+      attribute \src "ls180.v:5100.6-5100.33"
       case 1'1
         assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r
       case 
     end
-    attribute \src "ls180.v:5119.2-5121.5"
+    attribute \src "ls180.v:5104.2-5106.5"
     switch \libresocsim_csrbank2_out0_re
-      attribute \src "ls180.v:5119.6-5119.34"
+      attribute \src "ls180.v:5104.6-5104.34"
       case 1'1
         assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r
       case 
     end
-    attribute \src "ls180.v:5124.2-5133.5"
+    attribute \src "ls180.v:5109.2-5118.5"
     switch \libresocsim_csrbank3_sel
-      attribute \src "ls180.v:5124.6-5124.30"
+      attribute \src "ls180.v:5109.6-5109.30"
       case 1'1
-        attribute \src "ls180.v:5125.3-5132.10"
+        attribute \src "ls180.v:5110.3-5117.10"
         switch \libresocsim_interface3_bank_bus_adr [0]
           attribute \src "ls180.v:0.0-0.0"
           case 1'0
@@ -268423,18 +268043,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5134.2-5136.5"
+    attribute \src "ls180.v:5119.2-5121.5"
     switch \libresocsim_csrbank3_w0_re
-      attribute \src "ls180.v:5134.6-5134.32"
+      attribute \src "ls180.v:5119.6-5119.32"
       case 1'1
         assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r
       case 
     end
-    attribute \src "ls180.v:5139.2-5172.5"
+    attribute \src "ls180.v:5124.2-5157.5"
     switch \libresocsim_csrbank4_sel
-      attribute \src "ls180.v:5139.6-5139.30"
+      attribute \src "ls180.v:5124.6-5124.30"
       case 1'1
-        attribute \src "ls180.v:5140.3-5171.10"
+        attribute \src "ls180.v:5125.3-5156.10"
         switch \libresocsim_interface4_bank_bus_adr [3:0]
           attribute \src "ls180.v:0.0-0.0"
           case 4'0000
@@ -268470,60 +268090,60 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5173.2-5175.5"
+    attribute \src "ls180.v:5158.2-5160.5"
     switch \libresocsim_csrbank4_dfii_control0_re
-      attribute \src "ls180.v:5173.6-5173.43"
+      attribute \src "ls180.v:5158.6-5158.43"
       case 1'1
         assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r
       case 
     end
-    attribute \src "ls180.v:5177.2-5179.5"
+    attribute \src "ls180.v:5162.2-5164.5"
     switch \libresocsim_csrbank4_dfii_pi0_command0_re
-      attribute \src "ls180.v:5177.6-5177.47"
+      attribute \src "ls180.v:5162.6-5162.47"
       case 1'1
         assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r
       case 
     end
-    attribute \src "ls180.v:5181.2-5183.5"
+    attribute \src "ls180.v:5166.2-5168.5"
     switch \libresocsim_csrbank4_dfii_pi0_address1_re
-      attribute \src "ls180.v:5181.6-5181.47"
+      attribute \src "ls180.v:5166.6-5166.47"
       case 1'1
         assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r
       case 
     end
-    attribute \src "ls180.v:5184.2-5186.5"
+    attribute \src "ls180.v:5169.2-5171.5"
     switch \libresocsim_csrbank4_dfii_pi0_address0_re
-      attribute \src "ls180.v:5184.6-5184.47"
+      attribute \src "ls180.v:5169.6-5169.47"
       case 1'1
         assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r
       case 
     end
-    attribute \src "ls180.v:5188.2-5190.5"
+    attribute \src "ls180.v:5173.2-5175.5"
     switch \libresocsim_csrbank4_dfii_pi0_baddress0_re
-      attribute \src "ls180.v:5188.6-5188.48"
+      attribute \src "ls180.v:5173.6-5173.48"
       case 1'1
         assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r
       case 
     end
-    attribute \src "ls180.v:5192.2-5194.5"
+    attribute \src "ls180.v:5177.2-5179.5"
     switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re
-      attribute \src "ls180.v:5192.6-5192.46"
+      attribute \src "ls180.v:5177.6-5177.46"
       case 1'1
         assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r
       case 
     end
-    attribute \src "ls180.v:5195.2-5197.5"
+    attribute \src "ls180.v:5180.2-5182.5"
     switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re
-      attribute \src "ls180.v:5195.6-5195.46"
+      attribute \src "ls180.v:5180.6-5180.46"
       case 1'1
         assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r
       case 
     end
-    attribute \src "ls180.v:5200.2-5254.5"
+    attribute \src "ls180.v:5185.2-5239.5"
     switch \libresocsim_csrbank5_sel
-      attribute \src "ls180.v:5200.6-5200.30"
+      attribute \src "ls180.v:5185.6-5185.30"
       case 1'1
-        attribute \src "ls180.v:5201.3-5253.10"
+        attribute \src "ls180.v:5186.3-5238.10"
         switch \libresocsim_interface5_bank_bus_adr [4:0]
           attribute \src "ls180.v:0.0-0.0"
           case 5'00000
@@ -268580,88 +268200,88 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5255.2-5257.5"
+    attribute \src "ls180.v:5240.2-5242.5"
     switch \libresocsim_csrbank5_load3_re
-      attribute \src "ls180.v:5255.6-5255.35"
+      attribute \src "ls180.v:5240.6-5240.35"
       case 1'1
         assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r
       case 
     end
-    attribute \src "ls180.v:5258.2-5260.5"
+    attribute \src "ls180.v:5243.2-5245.5"
     switch \libresocsim_csrbank5_load2_re
-      attribute \src "ls180.v:5258.6-5258.35"
+      attribute \src "ls180.v:5243.6-5243.35"
       case 1'1
         assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r
       case 
     end
-    attribute \src "ls180.v:5261.2-5263.5"
+    attribute \src "ls180.v:5246.2-5248.5"
     switch \libresocsim_csrbank5_load1_re
-      attribute \src "ls180.v:5261.6-5261.35"
+      attribute \src "ls180.v:5246.6-5246.35"
       case 1'1
         assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r
       case 
     end
-    attribute \src "ls180.v:5264.2-5266.5"
+    attribute \src "ls180.v:5249.2-5251.5"
     switch \libresocsim_csrbank5_load0_re
-      attribute \src "ls180.v:5264.6-5264.35"
+      attribute \src "ls180.v:5249.6-5249.35"
       case 1'1
         assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r
       case 
     end
-    attribute \src "ls180.v:5268.2-5270.5"
+    attribute \src "ls180.v:5253.2-5255.5"
     switch \libresocsim_csrbank5_reload3_re
-      attribute \src "ls180.v:5268.6-5268.37"
+      attribute \src "ls180.v:5253.6-5253.37"
       case 1'1
         assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r
       case 
     end
-    attribute \src "ls180.v:5271.2-5273.5"
+    attribute \src "ls180.v:5256.2-5258.5"
     switch \libresocsim_csrbank5_reload2_re
-      attribute \src "ls180.v:5271.6-5271.37"
+      attribute \src "ls180.v:5256.6-5256.37"
       case 1'1
         assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r
       case 
     end
-    attribute \src "ls180.v:5274.2-5276.5"
+    attribute \src "ls180.v:5259.2-5261.5"
     switch \libresocsim_csrbank5_reload1_re
-      attribute \src "ls180.v:5274.6-5274.37"
+      attribute \src "ls180.v:5259.6-5259.37"
       case 1'1
         assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r
       case 
     end
-    attribute \src "ls180.v:5277.2-5279.5"
+    attribute \src "ls180.v:5262.2-5264.5"
     switch \libresocsim_csrbank5_reload0_re
-      attribute \src "ls180.v:5277.6-5277.37"
+      attribute \src "ls180.v:5262.6-5262.37"
       case 1'1
         assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r
       case 
     end
-    attribute \src "ls180.v:5281.2-5283.5"
+    attribute \src "ls180.v:5266.2-5268.5"
     switch \libresocsim_csrbank5_en0_re
-      attribute \src "ls180.v:5281.6-5281.33"
+      attribute \src "ls180.v:5266.6-5266.33"
       case 1'1
         assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r
       case 
     end
-    attribute \src "ls180.v:5285.2-5287.5"
+    attribute \src "ls180.v:5270.2-5272.5"
     switch \libresocsim_csrbank5_update_value0_re
-      attribute \src "ls180.v:5285.6-5285.43"
+      attribute \src "ls180.v:5270.6-5270.43"
       case 1'1
         assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r
       case 
     end
-    attribute \src "ls180.v:5289.2-5291.5"
+    attribute \src "ls180.v:5274.2-5276.5"
     switch \libresocsim_csrbank5_ev_enable0_re
-      attribute \src "ls180.v:5289.6-5289.40"
+      attribute \src "ls180.v:5274.6-5274.40"
       case 1'1
         assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:5294.2-5321.5"
+    attribute \src "ls180.v:5279.2-5306.5"
     switch \libresocsim_csrbank6_sel
-      attribute \src "ls180.v:5294.6-5294.30"
+      attribute \src "ls180.v:5279.6-5279.30"
       case 1'1
-        attribute \src "ls180.v:5295.3-5320.10"
+        attribute \src "ls180.v:5280.3-5305.10"
         switch \libresocsim_interface6_bank_bus_adr [2:0]
           attribute \src "ls180.v:0.0-0.0"
           case 3'000
@@ -268691,18 +268311,18 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5322.2-5324.5"
+    attribute \src "ls180.v:5307.2-5309.5"
     switch \libresocsim_csrbank6_ev_enable0_re
-      attribute \src "ls180.v:5322.6-5322.40"
+      attribute \src "ls180.v:5307.6-5307.40"
       case 1'1
         assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r
       case 
     end
-    attribute \src "ls180.v:5327.2-5342.5"
+    attribute \src "ls180.v:5312.2-5327.5"
     switch \libresocsim_csrbank7_sel
-      attribute \src "ls180.v:5327.6-5327.30"
+      attribute \src "ls180.v:5312.6-5312.30"
       case 1'1
-        attribute \src "ls180.v:5328.3-5341.10"
+        attribute \src "ls180.v:5313.3-5326.10"
         switch \libresocsim_interface7_bank_bus_adr [1:0]
           attribute \src "ls180.v:0.0-0.0"
           case 2'00
@@ -268720,37 +268340,37 @@ module \ls180
         end
       case 
     end
-    attribute \src "ls180.v:5343.2-5345.5"
+    attribute \src "ls180.v:5328.2-5330.5"
     switch \libresocsim_csrbank7_tuning_word3_re
-      attribute \src "ls180.v:5343.6-5343.42"
+      attribute \src "ls180.v:5328.6-5328.42"
       case 1'1
         assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r
       case 
     end
-    attribute \src "ls180.v:5346.2-5348.5"
+    attribute \src "ls180.v:5331.2-5333.5"
     switch \libresocsim_csrbank7_tuning_word2_re
-      attribute \src "ls180.v:5346.6-5346.42"
+      attribute \src "ls180.v:5331.6-5331.42"
       case 1'1
         assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r
       case 
     end
-    attribute \src "ls180.v:5349.2-5351.5"
+    attribute \src "ls180.v:5334.2-5336.5"
     switch \libresocsim_csrbank7_tuning_word1_re
-      attribute \src "ls180.v:5349.6-5349.42"
+      attribute \src "ls180.v:5334.6-5334.42"
       case 1'1
         assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r
       case 
     end
-    attribute \src "ls180.v:5352.2-5354.5"
+    attribute \src "ls180.v:5337.2-5339.5"
     switch \libresocsim_csrbank7_tuning_word0_re
-      attribute \src "ls180.v:5352.6-5352.42"
+      attribute \src "ls180.v:5337.6-5337.42"
       case 1'1
         assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r
       case 
     end
-    attribute \src "ls180.v:5356.2-5503.5"
+    attribute \src "ls180.v:5341.2-5488.5"
     switch \sys_rst_1
-      attribute \src "ls180.v:5356.6-5356.15"
+      attribute \src "ls180.v:5341.6-5341.15"
       case 1'1
         assign $0\libresocsim_reset_storage[0:0] 1'0
         assign $0\libresocsim_reset_re[0:0] 1'0
@@ -268758,6 +268378,9 @@ module \ls180
         assign $0\libresocsim_scratch_re[0:0] 1'0
         assign $0\libresocsim_bus_errors[31:0] 0
         assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+        assign $0\libresocsim_converter0_counter[0:0] 1'0
+        assign $0\libresocsim_converter1_counter[0:0] 1'0
+        assign $0\libresocsim_converter2_counter[0:0] 1'0
         assign $0\libresocsim_ram_bus_ack[0:0] 1'0
         assign $0\libresocsim_load_storage[31:0] 0
         assign $0\libresocsim_load_re[0:0] 1'0
@@ -268774,8 +268397,6 @@ module \ls180
         assign $0\libresocsim_eventmanager_re[0:0] 1'0
         assign $0\libresocsim_value[31:0] 0
         assign $0\ram_bus_ram_bus_ack[0:0] 1'0
-        assign $0\converter0_counter[0:0] 1'0
-        assign $0\converter1_counter[0:0] 1'0
         assign $0\dfi_p0_rddata_valid[0:0] 1'0
         assign $0\rddata_en[2:0] 3'000
         assign $0\sdram_storage[3:0] 4'0001
@@ -268840,7 +268461,6 @@ module \ls180
         assign $0\sdram_twtrcon_count[2:0] 3'000
         assign $0\sdram_time0[4:0] 5'00000
         assign $0\sdram_time1[3:0] 4'0000
-        assign $0\socbushandler_counter[0:0] 1'0
         assign $0\converter_counter[0:0] 1'0
         assign $0\cmd_consumed[0:0] 1'0
         assign $0\wdata_consumed[0:0] 1'0
@@ -268907,6 +268527,12 @@ module \ls180
       update \libresocsim_scratch_re $0\libresocsim_scratch_re[0:0]
       update \libresocsim_bus_errors $0\libresocsim_bus_errors[31:0]
       update \libresocsim_libresoc_constraintmanager_uart_tx $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+      update \libresocsim_converter0_counter $0\libresocsim_converter0_counter[0:0]
+      update \libresocsim_converter0_dat_r $0\libresocsim_converter0_dat_r[63:0]
+      update \libresocsim_converter1_counter $0\libresocsim_converter1_counter[0:0]
+      update \libresocsim_converter1_dat_r $0\libresocsim_converter1_dat_r[63:0]
+      update \libresocsim_converter2_counter $0\libresocsim_converter2_counter[0:0]
+      update \libresocsim_converter2_dat_r $0\libresocsim_converter2_dat_r[63:0]
       update \libresocsim_ram_bus_ack $0\libresocsim_ram_bus_ack[0:0]
       update \libresocsim_load_storage $0\libresocsim_load_storage[31:0]
       update \libresocsim_load_re $0\libresocsim_load_re[0:0]
@@ -268923,10 +268549,6 @@ module \ls180
       update \libresocsim_eventmanager_re $0\libresocsim_eventmanager_re[0:0]
       update \libresocsim_value $0\libresocsim_value[31:0]
       update \ram_bus_ram_bus_ack $0\ram_bus_ram_bus_ack[0:0]
-      update \converter0_counter $0\converter0_counter[0:0]
-      update \converter0_dat_r $0\converter0_dat_r[63:0]
-      update \converter1_counter $0\converter1_counter[0:0]
-      update \converter1_dat_r $0\converter1_dat_r[63:0]
       update \dfi_p0_rddata_valid $0\dfi_p0_rddata_valid[0:0]
       update \rddata_en $0\rddata_en[2:0]
       update \sdram_storage $0\sdram_storage[3:0]
@@ -269015,8 +268637,6 @@ module \ls180
       update \sdram_twtrcon_count $0\sdram_twtrcon_count[2:0]
       update \sdram_time0 $0\sdram_time0[4:0]
       update \sdram_time1 $0\sdram_time1[3:0]
-      update \socbushandler_counter $0\socbushandler_counter[0:0]
-      update \socbushandler_dat_r $0\socbushandler_dat_r[63:0]
       update \converter_counter $0\converter_counter[0:0]
       update \converter_dat_r $0\converter_dat_r[31:0]
       update \cmd_consumed $0\cmd_consumed[0:0]
@@ -269095,40 +268715,48 @@ module \ls180
       update \regs0 $0\regs0[0:0]
       update \regs1 $0\regs1[0:0]
   end
-  attribute \src "ls180.v:431.11-431.63"
-  process $proc$ls180.v:431$1782
+  attribute \src "ls180.v:429.5-429.61"
+  process $proc$ls180.v:429$1712
+    assign { } { }
+    assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
+    sync always
+      update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:444.11-444.63"
+  process $proc$ls180.v:444$1713
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:432.5-432.59"
-  process $proc$ls180.v:432$1783
+  attribute \src "ls180.v:445.5-445.59"
+  process $proc$ls180.v:445$1714
     assign { } { }
     assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
       update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:433.11-433.65"
-  process $proc$ls180.v:433$1784
+  attribute \src "ls180.v:446.11-446.65"
+  process $proc$ls180.v:446$1715
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:434.11-434.65"
-  process $proc$ls180.v:434$1785
+  attribute \src "ls180.v:447.11-447.65"
+  process $proc$ls180.v:447$1716
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:435.11-435.68"
-  process $proc$ls180.v:435$1786
+  attribute \src "ls180.v:448.11-448.68"
+  process $proc$ls180.v:448$1717
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
@@ -269136,430 +268764,319 @@ module \ls180
       update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
   end
   attribute \src "ls180.v:45.5-45.37"
-  process $proc$ls180.v:45$1627
+  process $proc$ls180.v:45$1547
     assign { } { }
     assign $1\libresocsim_reset_storage[0:0] 1'0
     sync always
     sync init
       update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0]
   end
-  attribute \src "ls180.v:456.5-456.54"
-  process $proc$ls180.v:456$1787
+  attribute \src "ls180.v:46.5-46.32"
+  process $proc$ls180.v:46$1548
+    assign { } { }
+    assign $1\libresocsim_reset_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_reset_re $1\libresocsim_reset_re[0:0]
+  end
+  attribute \src "ls180.v:469.5-469.54"
+  process $proc$ls180.v:469$1718
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:458.5-458.54"
-  process $proc$ls180.v:458$1788
+  attribute \src "ls180.v:47.12-47.55"
+  process $proc$ls180.v:47$1549
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
+    assign $1\libresocsim_scratch_storage[31:0] 305419896
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0]
+      update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0]
   end
-  attribute \src "ls180.v:459.5-459.53"
-  process $proc$ls180.v:459$1789
+  attribute \src "ls180.v:471.5-471.54"
+  process $proc$ls180.v:471$1719
     assign { } { }
-    assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
+    assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0]
+      update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:46.5-46.32"
-  process $proc$ls180.v:46$1628
+  attribute \src "ls180.v:472.5-472.53"
+  process $proc$ls180.v:472$1720
     assign { } { }
-    assign $1\libresocsim_reset_re[0:0] 1'0
+    assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_reset_re $1\libresocsim_reset_re[0:0]
+      update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0]
   end
-  attribute \src "ls180.v:460.5-460.59"
-  process $proc$ls180.v:460$1790
+  attribute \src "ls180.v:473.5-473.59"
+  process $proc$ls180.v:473$1721
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
   end
-  attribute \src "ls180.v:461.12-461.69"
-  process $proc$ls180.v:461$1791
+  attribute \src "ls180.v:474.12-474.69"
+  process $proc$ls180.v:474$1722
     assign { } { }
     assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
   end
-  attribute \src "ls180.v:462.12-462.42"
-  process $proc$ls180.v:462$1792
+  attribute \src "ls180.v:475.12-475.42"
+  process $proc$ls180.v:475$1723
     assign { } { }
     assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0]
   end
-  attribute \src "ls180.v:463.5-463.41"
-  process $proc$ls180.v:463$1793
+  attribute \src "ls180.v:476.5-476.41"
+  process $proc$ls180.v:476$1724
     assign { } { }
     assign $1\sdram_bankmachine0_row_opened[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0]
   end
-  attribute \src "ls180.v:465.5-465.39"
-  process $proc$ls180.v:465$1794
+  attribute \src "ls180.v:478.5-478.39"
+  process $proc$ls180.v:478$1725
     assign { } { }
     assign $1\sdram_bankmachine0_row_open[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0]
   end
-  attribute \src "ls180.v:466.5-466.40"
-  process $proc$ls180.v:466$1795
+  attribute \src "ls180.v:479.5-479.40"
+  process $proc$ls180.v:479$1726
     assign { } { }
     assign $1\sdram_bankmachine0_row_close[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0]
   end
-  attribute \src "ls180.v:467.5-467.49"
-  process $proc$ls180.v:467$1796
+  attribute \src "ls180.v:48.5-48.34"
+  process $proc$ls180.v:48$1550
+    assign { } { }
+    assign $1\libresocsim_scratch_re[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0]
+  end
+  attribute \src "ls180.v:480.5-480.49"
+  process $proc$ls180.v:480$1727
     assign { } { }
     assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0]
   end
-  attribute \src "ls180.v:469.32-469.71"
-  process $proc$ls180.v:469$1797
+  attribute \src "ls180.v:482.32-482.71"
+  process $proc$ls180.v:482$1728
     assign { } { }
     assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0]
   end
-  attribute \src "ls180.v:47.12-47.55"
-  process $proc$ls180.v:47$1629
-    assign { } { }
-    assign $1\libresocsim_scratch_storage[31:0] 305419896
-    sync always
-    sync init
-      update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0]
-  end
-  attribute \src "ls180.v:470.11-470.50"
-  process $proc$ls180.v:470$1798
+  attribute \src "ls180.v:483.11-483.50"
+  process $proc$ls180.v:483$1729
     assign { } { }
     assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0]
   end
-  attribute \src "ls180.v:472.32-472.70"
-  process $proc$ls180.v:472$1799
+  attribute \src "ls180.v:485.32-485.70"
+  process $proc$ls180.v:485$1730
     assign { } { }
     assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:474.32-474.71"
-  process $proc$ls180.v:474$1800
+  attribute \src "ls180.v:487.32-487.71"
+  process $proc$ls180.v:487$1731
     assign { } { }
     assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:48.5-48.34"
-  process $proc$ls180.v:48$1630
-    assign { } { }
-    assign $1\libresocsim_scratch_re[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0]
-  end
-  attribute \src "ls180.v:480.5-480.46"
-  process $proc$ls180.v:480$1801
+  attribute \src "ls180.v:493.5-493.46"
+  process $proc$ls180.v:493$1732
     assign { } { }
     assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:481.5-481.46"
-  process $proc$ls180.v:481$1802
+  attribute \src "ls180.v:494.5-494.46"
+  process $proc$ls180.v:494$1733
     assign { } { }
     assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:483.5-483.42"
-  process $proc$ls180.v:483$1803
+  attribute \src "ls180.v:496.5-496.42"
+  process $proc$ls180.v:496$1734
     assign { } { }
     assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:484.5-484.40"
-  process $proc$ls180.v:484$1804
+  attribute \src "ls180.v:497.5-497.40"
+  process $proc$ls180.v:497$1735
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:485.5-485.40"
-  process $proc$ls180.v:485$1805
+  attribute \src "ls180.v:498.5-498.40"
+  process $proc$ls180.v:498$1736
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:486.12-486.52"
-  process $proc$ls180.v:486$1806
+  attribute \src "ls180.v:499.12-499.52"
+  process $proc$ls180.v:499$1737
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:488.5-488.46"
-  process $proc$ls180.v:488$1807
+  attribute \src "ls180.v:501.5-501.46"
+  process $proc$ls180.v:501$1738
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:489.5-489.46"
-  process $proc$ls180.v:489$1808
+  attribute \src "ls180.v:502.5-502.46"
+  process $proc$ls180.v:502$1739
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:490.5-490.45"
-  process $proc$ls180.v:490$1809
+  attribute \src "ls180.v:503.5-503.45"
+  process $proc$ls180.v:503$1740
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:491.5-491.49"
-  process $proc$ls180.v:491$1810
+  attribute \src "ls180.v:504.5-504.49"
+  process $proc$ls180.v:504$1741
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
   end
-  attribute \src "ls180.v:492.5-492.50"
-  process $proc$ls180.v:492$1811
+  attribute \src "ls180.v:505.5-505.50"
+  process $proc$ls180.v:505$1742
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0]
   end
-  attribute \src "ls180.v:493.5-493.51"
-  process $proc$ls180.v:493$1812
+  attribute \src "ls180.v:506.5-506.51"
+  process $proc$ls180.v:506$1743
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0]
   end
-  attribute \src "ls180.v:494.5-494.45"
-  process $proc$ls180.v:494$1813
+  attribute \src "ls180.v:507.5-507.45"
+  process $proc$ls180.v:507$1744
     assign { } { }
     assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:497.5-497.62"
-  process $proc$ls180.v:497$1814
+  attribute \src "ls180.v:510.5-510.62"
+  process $proc$ls180.v:510$1745
     assign { } { }
     assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
       update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:498.5-498.61"
-  process $proc$ls180.v:498$1815
+  attribute \src "ls180.v:511.5-511.61"
+  process $proc$ls180.v:511$1746
     assign { } { }
     assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
       update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:513.11-513.63"
-  process $proc$ls180.v:513$1816
+  attribute \src "ls180.v:526.11-526.63"
+  process $proc$ls180.v:526$1747
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
       update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:514.5-514.59"
-  process $proc$ls180.v:514$1817
+  attribute \src "ls180.v:527.5-527.59"
+  process $proc$ls180.v:527$1748
     assign { } { }
     assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
       update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:515.11-515.65"
-  process $proc$ls180.v:515$1818
+  attribute \src "ls180.v:528.11-528.65"
+  process $proc$ls180.v:528$1749
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:516.11-516.65"
-  process $proc$ls180.v:516$1819
+  attribute \src "ls180.v:529.11-529.65"
+  process $proc$ls180.v:529$1750
     assign { } { }
     assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:517.11-517.68"
-  process $proc$ls180.v:517$1820
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
-  end
   attribute \src "ls180.v:53.12-53.42"
-  process $proc$ls180.v:53$1631
+  process $proc$ls180.v:53$1551
     assign { } { }
     assign $1\libresocsim_bus_errors[31:0] 0
     sync always
     sync init
       update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0]
   end
-  attribute \src "ls180.v:538.5-538.54"
-  process $proc$ls180.v:538$1821
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
-  end
-  attribute \src "ls180.v:540.5-540.54"
-  process $proc$ls180.v:540$1822
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0]
-  end
-  attribute \src "ls180.v:541.5-541.53"
-  process $proc$ls180.v:541$1823
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0]
-  end
-  attribute \src "ls180.v:542.5-542.59"
-  process $proc$ls180.v:542$1824
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
-  end
-  attribute \src "ls180.v:543.12-543.69"
-  process $proc$ls180.v:543$1825
-    assign { } { }
-    assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
-    sync always
-    sync init
-      update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
-  end
-  attribute \src "ls180.v:544.12-544.42"
-  process $proc$ls180.v:544$1826
-    assign { } { }
-    assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000
-    sync always
-    sync init
-      update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0]
-  end
-  attribute \src "ls180.v:545.5-545.41"
-  process $proc$ls180.v:545$1827
-    assign { } { }
-    assign $1\sdram_bankmachine1_row_opened[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0]
-  end
-  attribute \src "ls180.v:547.5-547.39"
-  process $proc$ls180.v:547$1828
-    assign { } { }
-    assign $1\sdram_bankmachine1_row_open[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0]
-  end
-  attribute \src "ls180.v:548.5-548.40"
-  process $proc$ls180.v:548$1829
-    assign { } { }
-    assign $1\sdram_bankmachine1_row_close[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0]
-  end
-  attribute \src "ls180.v:549.5-549.49"
-  process $proc$ls180.v:549$1830
+  attribute \src "ls180.v:530.11-530.68"
+  process $proc$ls180.v:530$1751
     assign { } { }
-    assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
-    sync always
-    sync init
-      update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0]
-  end
-  attribute \src "ls180.v:55.12-55.50"
-  process $proc$ls180.v:55$1632
-    assign { } { }
-    assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
-    sync always
-    sync init
-      update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0]
-  end
-  attribute \src "ls180.v:551.32-551.71"
-  process $proc$ls180.v:551$1831
-    assign { } { }
-    assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+    assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
-      update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0]
+      update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:5510.1-5528.4"
-  process $proc$ls180.v:5510$1466
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
+  attribute \src "ls180.v:5495.1-5505.4"
+  process $proc$ls180.v:5495$1434
     assign { } { }
     assign { } { }
     assign { } { }
@@ -269585,237 +269102,120 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467 $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491
-    assign $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492
-    assign $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493
-    assign $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470 $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494
-    assign $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495
-    assign $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496
-    assign $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473 $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497
-    assign $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498
-    assign $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499
-    assign $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476 $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500
-    assign $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501
-    assign $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502
-    assign $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479 $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503
-    assign $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504
-    assign $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505
-    assign $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482 $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506
-    assign $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507
-    assign $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508
-    assign $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485 $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509
-    assign $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510
-    assign $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511
-    assign $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488 $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512
-    assign $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513
-    assign $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514
-    assign $0\memadr[5:0] \libresocsim_adr
-    attribute \src "ls180.v:5511.2-5512.55"
+    assign $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447
+    assign $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448
+    assign $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449
+    assign $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450
+    assign $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451
+    assign $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452
+    assign $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453
+    assign $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454
+    assign $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455
+    assign $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456
+    assign $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457
+    assign $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458
+    assign $0\memadr[6:0] \libresocsim_adr
+    attribute \src "ls180.v:5496.2-5497.55"
     switch \libresocsim_we [0]
-      attribute \src "ls180.v:5511.6-5511.23"
+      attribute \src "ls180.v:5496.6-5496.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 { 56'00000000000000000000000000000000000000000000000000000000 \libresocsim_dat_w [7:0] }
-        assign $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 64'0000000000000000000000000000000000000000000000000000000011111111
+        assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 \libresocsim_adr
+        assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 { 24'000000000000000000000000 \libresocsim_dat_w [7:0] }
+        assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 255
       case 
-        assign $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 7'xxxxxxx
+        assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0
     end
-    attribute \src "ls180.v:5513.2-5514.57"
+    attribute \src "ls180.v:5498.2-5499.57"
     switch \libresocsim_we [1]
-      attribute \src "ls180.v:5513.6-5513.23"
+      attribute \src "ls180.v:5498.6-5498.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 { 48'000000000000000000000000000000000000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 64'0000000000000000000000000000000000000000000000001111111100000000
+        assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 \libresocsim_adr
+        assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 { 16'0000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx }
+        assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 65280
       case 
-        assign $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 7'xxxxxxx
+        assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 0
     end
-    attribute \src "ls180.v:5515.2-5516.59"
+    attribute \src "ls180.v:5500.2-5501.59"
     switch \libresocsim_we [2]
-      attribute \src "ls180.v:5515.6-5515.23"
+      attribute \src "ls180.v:5500.6-5500.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 { 40'0000000000000000000000000000000000000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 64'0000000000000000000000000000000000000000111111110000000000000000
+        assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 \libresocsim_adr
+        assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 { 8'00000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 16711680
       case 
-        assign $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 7'xxxxxxx
+        assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 0
     end
-    attribute \src "ls180.v:5517.2-5518.59"
+    attribute \src "ls180.v:5502.2-5503.59"
     switch \libresocsim_we [3]
-      attribute \src "ls180.v:5517.6-5517.23"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 { 32'00000000000000000000000000000000 \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 64'0000000000000000000000000000000011111111000000000000000000000000
-      case 
-        assign $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5519.2-5520.59"
-    switch \libresocsim_we [4]
-      attribute \src "ls180.v:5519.6-5519.23"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 { 24'000000000000000000000000 \libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 64'0000000000000000000000001111111100000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5521.2-5522.59"
-    switch \libresocsim_we [5]
-      attribute \src "ls180.v:5521.6-5521.23"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 { 16'0000000000000000 \libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 64'0000000000000000111111110000000000000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5523.2-5524.59"
-    switch \libresocsim_we [6]
-      attribute \src "ls180.v:5523.6-5523.23"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 { 8'00000000 \libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 64'0000000011111111000000000000000000000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5525.2-5526.59"
-    switch \libresocsim_we [7]
-      attribute \src "ls180.v:5525.6-5525.23"
+      attribute \src "ls180.v:5502.6-5502.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 \libresocsim_adr
-        assign $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 { \libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 64'1111111100000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 \libresocsim_adr
+        assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 { \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 32'11111111000000000000000000000000
       case 
-        assign $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 6'xxxxxx
-        assign $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 7'xxxxxxx
+        assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 0
     end
     sync posedge \sys_clk_1
-      update \memadr $0\memadr[5:0]
-      update $memwr$\mem$ls180.v:5512$1_ADDR $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467
-      update $memwr$\mem$ls180.v:5512$1_DATA $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468
-      update $memwr$\mem$ls180.v:5512$1_EN $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469
-      update $memwr$\mem$ls180.v:5514$2_ADDR $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470
-      update $memwr$\mem$ls180.v:5514$2_DATA $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471
-      update $memwr$\mem$ls180.v:5514$2_EN $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472
-      update $memwr$\mem$ls180.v:5516$3_ADDR $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473
-      update $memwr$\mem$ls180.v:5516$3_DATA $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474
-      update $memwr$\mem$ls180.v:5516$3_EN $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475
-      update $memwr$\mem$ls180.v:5518$4_ADDR $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476
-      update $memwr$\mem$ls180.v:5518$4_DATA $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477
-      update $memwr$\mem$ls180.v:5518$4_EN $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478
-      update $memwr$\mem$ls180.v:5520$5_ADDR $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479
-      update $memwr$\mem$ls180.v:5520$5_DATA $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480
-      update $memwr$\mem$ls180.v:5520$5_EN $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481
-      update $memwr$\mem$ls180.v:5522$6_ADDR $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482
-      update $memwr$\mem$ls180.v:5522$6_DATA $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483
-      update $memwr$\mem$ls180.v:5522$6_EN $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484
-      update $memwr$\mem$ls180.v:5524$7_ADDR $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485
-      update $memwr$\mem$ls180.v:5524$7_DATA $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486
-      update $memwr$\mem$ls180.v:5524$7_EN $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487
-      update $memwr$\mem$ls180.v:5526$8_ADDR $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488
-      update $memwr$\mem$ls180.v:5526$8_DATA $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489
-      update $memwr$\mem$ls180.v:5526$8_EN $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490
-      attribute \src "ls180.v:5512.3-5512.54"
-      memwr \mem $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 0'
-      attribute \src "ls180.v:5514.3-5514.56"
-      memwr \mem $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 1'1
-      attribute \src "ls180.v:5516.3-5516.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 2'11
-      attribute \src "ls180.v:5518.3-5518.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 3'111
-      attribute \src "ls180.v:5520.3-5520.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 4'1111
-      attribute \src "ls180.v:5522.3-5522.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 5'11111
-      attribute \src "ls180.v:5524.3-5524.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 6'111111
-      attribute \src "ls180.v:5526.3-5526.58"
-      memwr \mem $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 7'1111111
-  end
-  attribute \src "ls180.v:552.11-552.50"
-  process $proc$ls180.v:552$1832
+      update \memadr $0\memadr[6:0]
+      update $memwr$\mem$ls180.v:5497$1_ADDR $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435
+      update $memwr$\mem$ls180.v:5497$1_DATA $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436
+      update $memwr$\mem$ls180.v:5497$1_EN $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437
+      update $memwr$\mem$ls180.v:5499$2_ADDR $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438
+      update $memwr$\mem$ls180.v:5499$2_DATA $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439
+      update $memwr$\mem$ls180.v:5499$2_EN $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440
+      update $memwr$\mem$ls180.v:5501$3_ADDR $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441
+      update $memwr$\mem$ls180.v:5501$3_DATA $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442
+      update $memwr$\mem$ls180.v:5501$3_EN $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443
+      update $memwr$\mem$ls180.v:5503$4_ADDR $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444
+      update $memwr$\mem$ls180.v:5503$4_DATA $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445
+      update $memwr$\mem$ls180.v:5503$4_EN $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446
+      attribute \src "ls180.v:5497.3-5497.54"
+      memwr \mem $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0'
+      attribute \src "ls180.v:5499.3-5499.56"
+      memwr \mem $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 1'1
+      attribute \src "ls180.v:5501.3-5501.58"
+      memwr \mem $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 2'11
+      attribute \src "ls180.v:5503.3-5503.58"
+      memwr \mem $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 3'111
+  end
+  attribute \src "ls180.v:55.12-55.50"
+  process $proc$ls180.v:55$1552
     assign { } { }
-    assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000
+    assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
     sync always
     sync init
-      update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0]
+      update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0]
   end
-  attribute \src "ls180.v:5538.1-5556.4"
-  process $proc$ls180.v:5538$1516
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
-    assign { } { }
+  attribute \src "ls180.v:551.5-551.54"
+  process $proc$ls180.v:551$1752
     assign { } { }
+    assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
+  end
+  attribute \src "ls180.v:5515.1-5525.4"
+  process $proc$ls180.v:5515$1460
     assign { } { }
     assign { } { }
     assign { } { }
@@ -269841,212 +269241,112 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541
-    assign $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542
-    assign $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543
-    assign $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544
-    assign $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545
-    assign $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546
-    assign $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547
-    assign $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548
-    assign $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549
-    assign $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550
-    assign $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551
-    assign $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552
-    assign $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553
-    assign $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554
-    assign $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555
-    assign $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556
-    assign $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557
-    assign $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558
-    assign $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559
-    assign $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560
-    assign $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561
-    assign $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562
-    assign $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563
-    assign $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564
-    assign $0\memadr_1[3:0] \ram_adr
-    attribute \src "ls180.v:5539.2-5540.41"
+    assign $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473
+    assign $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474
+    assign $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475
+    assign $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476
+    assign $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477
+    assign $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478
+    assign $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479
+    assign $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480
+    assign $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481
+    assign $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482
+    assign $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483
+    assign $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484
+    assign $0\memadr_1[4:0] \ram_adr
+    attribute \src "ls180.v:5516.2-5517.41"
     switch \ram_we [0]
-      attribute \src "ls180.v:5539.6-5539.15"
+      attribute \src "ls180.v:5516.6-5516.15"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 { 56'00000000000000000000000000000000000000000000000000000000 \ram_dat_w [7:0] }
-        assign $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 64'0000000000000000000000000000000000000000000000000000000011111111
+        assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 \ram_adr
+        assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 { 24'000000000000000000000000 \ram_dat_w [7:0] }
+        assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 255
       case 
-        assign $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 5'xxxxx
+        assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0
     end
-    attribute \src "ls180.v:5541.2-5542.43"
+    attribute \src "ls180.v:5518.2-5519.43"
     switch \ram_we [1]
-      attribute \src "ls180.v:5541.6-5541.15"
+      attribute \src "ls180.v:5518.6-5518.15"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 { 48'000000000000000000000000000000000000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 64'0000000000000000000000000000000000000000000000001111111100000000
+        assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 \ram_adr
+        assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 { 16'0000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx }
+        assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 65280
       case 
-        assign $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 5'xxxxx
+        assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 0
     end
-    attribute \src "ls180.v:5543.2-5544.45"
+    attribute \src "ls180.v:5520.2-5521.45"
     switch \ram_we [2]
-      attribute \src "ls180.v:5543.6-5543.15"
+      attribute \src "ls180.v:5520.6-5520.15"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 { 40'0000000000000000000000000000000000000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 64'0000000000000000000000000000000000000000111111110000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 \ram_adr
+        assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 { 8'00000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+        assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 16711680
       case 
-        assign $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 5'xxxxx
+        assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 0
     end
-    attribute \src "ls180.v:5545.2-5546.45"
+    attribute \src "ls180.v:5522.2-5523.45"
     switch \ram_we [3]
-      attribute \src "ls180.v:5545.6-5545.15"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 { 32'00000000000000000000000000000000 \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 64'0000000000000000000000000000000011111111000000000000000000000000
-      case 
-        assign $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5547.2-5548.45"
-    switch \ram_we [4]
-      attribute \src "ls180.v:5547.6-5547.15"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 { 24'000000000000000000000000 \ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 64'0000000000000000000000001111111100000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5549.2-5550.45"
-    switch \ram_we [5]
-      attribute \src "ls180.v:5549.6-5549.15"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 { 16'0000000000000000 \ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 64'0000000000000000111111110000000000000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5551.2-5552.45"
-    switch \ram_we [6]
-      attribute \src "ls180.v:5551.6-5551.15"
-      case 1'1
-        assign { } { }
-        assign { } { }
-        assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 { 8'00000000 \ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 64'0000000011111111000000000000000000000000000000000000000000000000
-      case 
-        assign $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "ls180.v:5553.2-5554.45"
-    switch \ram_we [7]
-      attribute \src "ls180.v:5553.6-5553.15"
+      attribute \src "ls180.v:5522.6-5522.15"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 \ram_adr
-        assign $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 { \ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
-        assign $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 64'1111111100000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 \ram_adr
+        assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 { \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+        assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 32'11111111000000000000000000000000
       case 
-        assign $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 4'xxxx
-        assign $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 5'xxxxx
+        assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 0
     end
     sync posedge \sys_clk_1
-      update \memadr_1 $0\memadr_1[3:0]
-      update $memwr$\mem_1$ls180.v:5540$9_ADDR $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517
-      update $memwr$\mem_1$ls180.v:5540$9_DATA $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518
-      update $memwr$\mem_1$ls180.v:5540$9_EN $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519
-      update $memwr$\mem_1$ls180.v:5542$10_ADDR $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520
-      update $memwr$\mem_1$ls180.v:5542$10_DATA $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521
-      update $memwr$\mem_1$ls180.v:5542$10_EN $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522
-      update $memwr$\mem_1$ls180.v:5544$11_ADDR $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523
-      update $memwr$\mem_1$ls180.v:5544$11_DATA $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524
-      update $memwr$\mem_1$ls180.v:5544$11_EN $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525
-      update $memwr$\mem_1$ls180.v:5546$12_ADDR $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526
-      update $memwr$\mem_1$ls180.v:5546$12_DATA $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527
-      update $memwr$\mem_1$ls180.v:5546$12_EN $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528
-      update $memwr$\mem_1$ls180.v:5548$13_ADDR $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529
-      update $memwr$\mem_1$ls180.v:5548$13_DATA $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530
-      update $memwr$\mem_1$ls180.v:5548$13_EN $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531
-      update $memwr$\mem_1$ls180.v:5550$14_ADDR $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532
-      update $memwr$\mem_1$ls180.v:5550$14_DATA $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533
-      update $memwr$\mem_1$ls180.v:5550$14_EN $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534
-      update $memwr$\mem_1$ls180.v:5552$15_ADDR $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535
-      update $memwr$\mem_1$ls180.v:5552$15_DATA $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536
-      update $memwr$\mem_1$ls180.v:5552$15_EN $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537
-      update $memwr$\mem_1$ls180.v:5554$16_ADDR $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538
-      update $memwr$\mem_1$ls180.v:5554$16_DATA $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539
-      update $memwr$\mem_1$ls180.v:5554$16_EN $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540
-      attribute \src "ls180.v:5540.3-5540.40"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 0'
-      attribute \src "ls180.v:5542.3-5542.42"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 1'1
-      attribute \src "ls180.v:5544.3-5544.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 2'11
-      attribute \src "ls180.v:5546.3-5546.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 3'111
-      attribute \src "ls180.v:5548.3-5548.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 4'1111
-      attribute \src "ls180.v:5550.3-5550.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 5'11111
-      attribute \src "ls180.v:5552.3-5552.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 6'111111
-      attribute \src "ls180.v:5554.3-5554.44"
-      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 7'1111111
-  end
-  attribute \src "ls180.v:554.32-554.70"
-  process $proc$ls180.v:554$1833
-    assign { } { }
-    assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1
-    sync always
-      update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:556.32-556.71"
-  process $proc$ls180.v:556$1834
+      update \memadr_1 $0\memadr_1[4:0]
+      update $memwr$\mem_1$ls180.v:5517$5_ADDR $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461
+      update $memwr$\mem_1$ls180.v:5517$5_DATA $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462
+      update $memwr$\mem_1$ls180.v:5517$5_EN $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463
+      update $memwr$\mem_1$ls180.v:5519$6_ADDR $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464
+      update $memwr$\mem_1$ls180.v:5519$6_DATA $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465
+      update $memwr$\mem_1$ls180.v:5519$6_EN $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466
+      update $memwr$\mem_1$ls180.v:5521$7_ADDR $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467
+      update $memwr$\mem_1$ls180.v:5521$7_DATA $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468
+      update $memwr$\mem_1$ls180.v:5521$7_EN $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469
+      update $memwr$\mem_1$ls180.v:5523$8_ADDR $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470
+      update $memwr$\mem_1$ls180.v:5523$8_DATA $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471
+      update $memwr$\mem_1$ls180.v:5523$8_EN $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472
+      attribute \src "ls180.v:5517.3-5517.40"
+      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0'
+      attribute \src "ls180.v:5519.3-5519.42"
+      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 1'1
+      attribute \src "ls180.v:5521.3-5521.44"
+      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 2'11
+      attribute \src "ls180.v:5523.3-5523.44"
+      memwr \mem_1 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 3'111
+  end
+  attribute \src "ls180.v:553.5-553.54"
+  process $proc$ls180.v:553$1753
     assign { } { }
-    assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1
+    assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
     sync always
-      update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0]
     sync init
+      update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:5566.1-5570.4"
-  process $proc$ls180.v:5566$1566
+  attribute \src "ls180.v:5535.1-5539.4"
+  process $proc$ls180.v:5535$1486
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270054,39 +269354,47 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567 $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570
-    assign $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571
-    assign $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572
-    assign $0\memdat[24:0] $memrd$\storage$ls180.v:5569$1573_DATA
-    attribute \src "ls180.v:5567.2-5568.119"
+    assign $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490
+    assign $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491
+    assign $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492
+    assign $0\memdat[24:0] $memrd$\storage$ls180.v:5538$1493_DATA
+    attribute \src "ls180.v:5536.2-5537.119"
     switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:5567.6-5567.55"
+      attribute \src "ls180.v:5536.6-5536.55"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
-        assign $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
-        assign $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 25'1111111111111111111111111
+        assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+        assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+        assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'1111111111111111111111111
       case 
-        assign $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 3'xxx
-        assign $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 25'0000000000000000000000000
+        assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 3'xxx
+        assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'0000000000000000000000000
     end
     sync posedge \sys_clk_1
       update \memdat $0\memdat[24:0]
-      update $memwr$\storage$ls180.v:5568$17_ADDR $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567
-      update $memwr$\storage$ls180.v:5568$17_DATA $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568
-      update $memwr$\storage$ls180.v:5568$17_EN $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569
-      attribute \src "ls180.v:5568.3-5568.118"
-      memwr \storage $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 0'
-  end
-  attribute \src "ls180.v:5572.1-5573.4"
-  process $proc$ls180.v:5572$1574
+      update $memwr$\storage$ls180.v:5537$9_ADDR $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487
+      update $memwr$\storage$ls180.v:5537$9_DATA $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488
+      update $memwr$\storage$ls180.v:5537$9_EN $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489
+      attribute \src "ls180.v:5537.3-5537.118"
+      memwr \storage $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 0'
+  end
+  attribute \src "ls180.v:554.5-554.53"
+  process $proc$ls180.v:554$1754
+    assign { } { }
+    assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0]
+  end
+  attribute \src "ls180.v:5541.1-5542.4"
+  process $proc$ls180.v:5541$1494
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:5580.1-5584.4"
-  process $proc$ls180.v:5580$1576
+  attribute \src "ls180.v:5549.1-5553.4"
+  process $proc$ls180.v:5549$1496
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270094,39 +269402,55 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580
-    assign $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581
-    assign $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582
-    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5583$1583_DATA
-    attribute \src "ls180.v:5581.2-5582.121"
+    assign $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500
+    assign $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501
+    assign $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502
+    assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5552$1503_DATA
+    attribute \src "ls180.v:5550.2-5551.121"
     switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:5581.6-5581.55"
+      attribute \src "ls180.v:5550.6-5550.55"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
-        assign $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
-        assign $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 25'1111111111111111111111111
+        assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+        assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+        assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'1111111111111111111111111
       case 
-        assign $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 3'xxx
-        assign $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 25'0000000000000000000000000
+        assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 3'xxx
+        assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'0000000000000000000000000
     end
     sync posedge \sys_clk_1
       update \memdat_1 $0\memdat_1[24:0]
-      update $memwr$\storage_1$ls180.v:5582$18_ADDR $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577
-      update $memwr$\storage_1$ls180.v:5582$18_DATA $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578
-      update $memwr$\storage_1$ls180.v:5582$18_EN $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579
-      attribute \src "ls180.v:5582.3-5582.120"
-      memwr \storage_1 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 0'
-  end
-  attribute \src "ls180.v:5586.1-5587.4"
-  process $proc$ls180.v:5586$1584
+      update $memwr$\storage_1$ls180.v:5551$10_ADDR $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497
+      update $memwr$\storage_1$ls180.v:5551$10_DATA $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498
+      update $memwr$\storage_1$ls180.v:5551$10_EN $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499
+      attribute \src "ls180.v:5551.3-5551.120"
+      memwr \storage_1 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 0'
+  end
+  attribute \src "ls180.v:555.5-555.59"
+  process $proc$ls180.v:555$1755
+    assign { } { }
+    assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
+  end
+  attribute \src "ls180.v:5555.1-5556.4"
+  process $proc$ls180.v:5555$1504
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:5594.1-5598.4"
-  process $proc$ls180.v:5594$1586
+  attribute \src "ls180.v:556.12-556.69"
+  process $proc$ls180.v:556$1756
+    assign { } { }
+    assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+    sync always
+    sync init
+      update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
+  end
+  attribute \src "ls180.v:5563.1-5567.4"
+  process $proc$ls180.v:5563$1506
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270134,39 +269458,47 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590
-    assign $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591
-    assign $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592
-    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5597$1593_DATA
-    attribute \src "ls180.v:5595.2-5596.121"
+    assign $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510
+    assign $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511
+    assign $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512
+    assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5566$1513_DATA
+    attribute \src "ls180.v:5564.2-5565.121"
     switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:5595.6-5595.55"
+      attribute \src "ls180.v:5564.6-5564.55"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
-        assign $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
-        assign $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 25'1111111111111111111111111
+        assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+        assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+        assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'1111111111111111111111111
       case 
-        assign $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 3'xxx
-        assign $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 25'0000000000000000000000000
+        assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 3'xxx
+        assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'0000000000000000000000000
     end
     sync posedge \sys_clk_1
       update \memdat_2 $0\memdat_2[24:0]
-      update $memwr$\storage_2$ls180.v:5596$19_ADDR $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587
-      update $memwr$\storage_2$ls180.v:5596$19_DATA $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588
-      update $memwr$\storage_2$ls180.v:5596$19_EN $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589
-      attribute \src "ls180.v:5596.3-5596.120"
-      memwr \storage_2 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 0'
-  end
-  attribute \src "ls180.v:5600.1-5601.4"
-  process $proc$ls180.v:5600$1594
+      update $memwr$\storage_2$ls180.v:5565$11_ADDR $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507
+      update $memwr$\storage_2$ls180.v:5565$11_DATA $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508
+      update $memwr$\storage_2$ls180.v:5565$11_EN $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509
+      attribute \src "ls180.v:5565.3-5565.120"
+      memwr \storage_2 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 0'
+  end
+  attribute \src "ls180.v:5569.1-5570.4"
+  process $proc$ls180.v:5569$1514
     sync posedge \sys_clk_1
   end
-  attribute \src "ls180.v:5608.1-5612.4"
-  process $proc$ls180.v:5608$1596
+  attribute \src "ls180.v:557.12-557.42"
+  process $proc$ls180.v:557$1757
+    assign { } { }
+    assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000
+    sync always
+    sync init
+      update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0]
+  end
+  attribute \src "ls180.v:5577.1-5581.4"
+  process $proc$ls180.v:5577$1516
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270174,47 +269506,47 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600
-    assign $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601
-    assign $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602
-    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5611$1603_DATA
-    attribute \src "ls180.v:5609.2-5610.121"
+    assign $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520
+    assign $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521
+    assign $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522
+    assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5580$1523_DATA
+    attribute \src "ls180.v:5578.2-5579.121"
     switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
-      attribute \src "ls180.v:5609.6-5609.55"
+      attribute \src "ls180.v:5578.6-5578.55"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
-        assign $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
-        assign $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 25'1111111111111111111111111
+        assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+        assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+        assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'1111111111111111111111111
       case 
-        assign $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 3'xxx
-        assign $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 25'xxxxxxxxxxxxxxxxxxxxxxxxx
-        assign $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 25'0000000000000000000000000
+        assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 3'xxx
+        assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+        assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'0000000000000000000000000
     end
     sync posedge \sys_clk_1
       update \memdat_3 $0\memdat_3[24:0]
-      update $memwr$\storage_3$ls180.v:5610$20_ADDR $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597
-      update $memwr$\storage_3$ls180.v:5610$20_DATA $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598
-      update $memwr$\storage_3$ls180.v:5610$20_EN $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599
-      attribute \src "ls180.v:5610.3-5610.120"
-      memwr \storage_3 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 0'
-  end
-  attribute \src "ls180.v:5614.1-5615.4"
-  process $proc$ls180.v:5614$1604
-    sync posedge \sys_clk_1
+      update $memwr$\storage_3$ls180.v:5579$12_ADDR $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517
+      update $memwr$\storage_3$ls180.v:5579$12_DATA $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518
+      update $memwr$\storage_3$ls180.v:5579$12_EN $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519
+      attribute \src "ls180.v:5579.3-5579.120"
+      memwr \storage_3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 0'
   end
-  attribute \src "ls180.v:562.5-562.46"
-  process $proc$ls180.v:562$1835
+  attribute \src "ls180.v:558.5-558.41"
+  process $proc$ls180.v:558$1758
     assign { } { }
-    assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+    assign $1\sdram_bankmachine1_row_opened[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0]
+      update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0]
   end
-  attribute \src "ls180.v:5623.1-5627.4"
-  process $proc$ls180.v:5623$1606
+  attribute \src "ls180.v:5583.1-5584.4"
+  process $proc$ls180.v:5583$1524
+    sync posedge \sys_clk_1
+  end
+  attribute \src "ls180.v:5592.1-5596.4"
+  process $proc$ls180.v:5592$1526
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270222,56 +269554,56 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610
-    assign $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611
-    assign $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612
-    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5626$1613_DATA
-    attribute \src "ls180.v:5624.2-5625.57"
+    assign $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530
+    assign $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531
+    assign $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532
+    assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5595$1533_DATA
+    attribute \src "ls180.v:5593.2-5594.57"
     switch \tx_fifo_wrport_we
-      attribute \src "ls180.v:5624.6-5624.23"
+      attribute \src "ls180.v:5593.6-5593.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 \tx_fifo_wrport_adr
-        assign $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 \tx_fifo_wrport_dat_w
-        assign $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 10'1111111111
+        assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 \tx_fifo_wrport_adr
+        assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 \tx_fifo_wrport_dat_w
+        assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'1111111111
       case 
-        assign $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 4'xxxx
-        assign $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 10'xxxxxxxxxx
-        assign $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 10'0000000000
+        assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 4'xxxx
+        assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 10'xxxxxxxxxx
+        assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'0000000000
     end
     sync posedge \sys_clk_1
       update \memdat_4 $0\memdat_4[9:0]
-      update $memwr$\storage_4$ls180.v:5625$21_ADDR $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607
-      update $memwr$\storage_4$ls180.v:5625$21_DATA $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608
-      update $memwr$\storage_4$ls180.v:5625$21_EN $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609
-      attribute \src "ls180.v:5625.3-5625.56"
-      memwr \storage_4 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 0'
-  end
-  attribute \src "ls180.v:5629.1-5632.4"
-  process $proc$ls180.v:5629$1614
+      update $memwr$\storage_4$ls180.v:5594$13_ADDR $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527
+      update $memwr$\storage_4$ls180.v:5594$13_DATA $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528
+      update $memwr$\storage_4$ls180.v:5594$13_EN $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529
+      attribute \src "ls180.v:5594.3-5594.56"
+      memwr \storage_4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 0'
+  end
+  attribute \src "ls180.v:5598.1-5601.4"
+  process $proc$ls180.v:5598$1534
     assign $0\memdat_5[9:0] \memdat_5
-    attribute \src "ls180.v:5630.2-5631.45"
+    attribute \src "ls180.v:5599.2-5600.45"
     switch \tx_fifo_rdport_re
-      attribute \src "ls180.v:5630.6-5630.23"
+      attribute \src "ls180.v:5599.6-5599.23"
       case 1'1
-        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5631$1615_DATA
+        assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5600$1535_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_5 $0\memdat_5[9:0]
   end
-  attribute \src "ls180.v:563.5-563.46"
-  process $proc$ls180.v:563$1836
+  attribute \src "ls180.v:560.5-560.39"
+  process $proc$ls180.v:560$1759
     assign { } { }
-    assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+    assign $1\sdram_bankmachine1_row_open[0:0] 1'0
     sync always
     sync init
-      update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0]
+      update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0]
   end
-  attribute \src "ls180.v:5640.1-5644.4"
-  process $proc$ls180.v:5640$1616
+  attribute \src "ls180.v:5609.1-5613.4"
+  process $proc$ls180.v:5609$1536
     assign { } { }
     assign { } { }
     assign { } { }
@@ -270279,1640 +269611,1528 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620
-    assign $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621
-    assign $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622
-    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5643$1623_DATA
-    attribute \src "ls180.v:5641.2-5642.57"
+    assign $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540
+    assign $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541
+    assign $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542
+    assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5612$1543_DATA
+    attribute \src "ls180.v:5610.2-5611.57"
     switch \rx_fifo_wrport_we
-      attribute \src "ls180.v:5641.6-5641.23"
+      attribute \src "ls180.v:5610.6-5610.23"
       case 1'1
         assign { } { }
         assign { } { }
         assign { } { }
-        assign $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 \rx_fifo_wrport_adr
-        assign $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 \rx_fifo_wrport_dat_w
-        assign $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 10'1111111111
+        assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 \rx_fifo_wrport_adr
+        assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 \rx_fifo_wrport_dat_w
+        assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'1111111111
       case 
-        assign $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 4'xxxx
-        assign $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 10'xxxxxxxxxx
-        assign $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 10'0000000000
+        assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 4'xxxx
+        assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 10'xxxxxxxxxx
+        assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'0000000000
     end
     sync posedge \sys_clk_1
       update \memdat_6 $0\memdat_6[9:0]
-      update $memwr$\storage_5$ls180.v:5642$22_ADDR $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617
-      update $memwr$\storage_5$ls180.v:5642$22_DATA $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618
-      update $memwr$\storage_5$ls180.v:5642$22_EN $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619
-      attribute \src "ls180.v:5642.3-5642.56"
-      memwr \storage_5 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 0'
-  end
-  attribute \src "ls180.v:5646.1-5649.4"
-  process $proc$ls180.v:5646$1624
+      update $memwr$\storage_5$ls180.v:5611$14_ADDR $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537
+      update $memwr$\storage_5$ls180.v:5611$14_DATA $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538
+      update $memwr$\storage_5$ls180.v:5611$14_EN $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539
+      attribute \src "ls180.v:5611.3-5611.56"
+      memwr \storage_5 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 0'
+  end
+  attribute \src "ls180.v:561.5-561.40"
+  process $proc$ls180.v:561$1760
+    assign { } { }
+    assign $1\sdram_bankmachine1_row_close[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0]
+  end
+  attribute \src "ls180.v:5615.1-5618.4"
+  process $proc$ls180.v:5615$1544
     assign $0\memdat_7[9:0] \memdat_7
-    attribute \src "ls180.v:5647.2-5648.45"
+    attribute \src "ls180.v:5616.2-5617.45"
     switch \rx_fifo_rdport_re
-      attribute \src "ls180.v:5647.6-5647.23"
+      attribute \src "ls180.v:5616.6-5616.23"
       case 1'1
-        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5648$1625_DATA
+        assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5617$1545_DATA
       case 
     end
     sync posedge \sys_clk_1
       update \memdat_7 $0\memdat_7[9:0]
   end
-  attribute \src "ls180.v:565.5-565.42"
-  process $proc$ls180.v:565$1837
+  attribute \src "ls180.v:562.5-562.49"
+  process $proc$ls180.v:562$1761
+    assign { } { }
+    assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0]
+  end
+  attribute \src "ls180.v:564.32-564.71"
+  process $proc$ls180.v:564$1762
+    assign { } { }
+    assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0]
+  end
+  attribute \src "ls180.v:565.11-565.50"
+  process $proc$ls180.v:565$1763
+    assign { } { }
+    assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000
+    sync always
+    sync init
+      update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0]
+  end
+  attribute \src "ls180.v:567.32-567.70"
+  process $proc$ls180.v:567$1764
+    assign { } { }
+    assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1
+    sync always
+      update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:569.32-569.71"
+  process $proc$ls180.v:569$1765
+    assign { } { }
+    assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1
+    sync always
+      update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:575.5-575.46"
+  process $proc$ls180.v:575$1766
+    assign { } { }
+    assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0]
+  end
+  attribute \src "ls180.v:576.5-576.46"
+  process $proc$ls180.v:576$1767
+    assign { } { }
+    assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+    sync always
+    sync init
+      update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0]
+  end
+  attribute \src "ls180.v:578.5-578.42"
+  process $proc$ls180.v:578$1768
     assign { } { }
     assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:566.5-566.40"
-  process $proc$ls180.v:566$1838
+  attribute \src "ls180.v:579.5-579.40"
+  process $proc$ls180.v:579$1769
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:567.5-567.40"
-  process $proc$ls180.v:567$1839
+  attribute \src "ls180.v:580.5-580.40"
+  process $proc$ls180.v:580$1770
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:568.12-568.52"
-  process $proc$ls180.v:568$1840
+  attribute \src "ls180.v:581.12-581.52"
+  process $proc$ls180.v:581$1771
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:570.5-570.46"
-  process $proc$ls180.v:570$1841
+  attribute \src "ls180.v:583.5-583.46"
+  process $proc$ls180.v:583$1772
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:571.5-571.46"
-  process $proc$ls180.v:571$1842
+  attribute \src "ls180.v:584.5-584.46"
+  process $proc$ls180.v:584$1773
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:572.5-572.45"
-  process $proc$ls180.v:572$1843
+  attribute \src "ls180.v:585.5-585.45"
+  process $proc$ls180.v:585$1774
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:573.5-573.49"
-  process $proc$ls180.v:573$1844
+  attribute \src "ls180.v:586.5-586.49"
+  process $proc$ls180.v:586$1775
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
   end
-  attribute \src "ls180.v:574.5-574.50"
-  process $proc$ls180.v:574$1845
+  attribute \src "ls180.v:587.5-587.50"
+  process $proc$ls180.v:587$1776
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0]
   end
-  attribute \src "ls180.v:575.5-575.51"
-  process $proc$ls180.v:575$1846
+  attribute \src "ls180.v:588.5-588.51"
+  process $proc$ls180.v:588$1777
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0]
   end
-  attribute \src "ls180.v:576.5-576.45"
-  process $proc$ls180.v:576$1847
+  attribute \src "ls180.v:589.5-589.45"
+  process $proc$ls180.v:589$1778
     assign { } { }
     assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:579.5-579.62"
-  process $proc$ls180.v:579$1848
+  attribute \src "ls180.v:592.5-592.62"
+  process $proc$ls180.v:592$1779
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
       update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:580.5-580.61"
-  process $proc$ls180.v:580$1849
+  attribute \src "ls180.v:593.5-593.61"
+  process $proc$ls180.v:593$1780
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
       update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:595.11-595.63"
-  process $proc$ls180.v:595$1850
+  attribute \src "ls180.v:608.11-608.63"
+  process $proc$ls180.v:608$1781
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:596.5-596.59"
-  process $proc$ls180.v:596$1851
+  attribute \src "ls180.v:609.5-609.59"
+  process $proc$ls180.v:609$1782
     assign { } { }
     assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
       update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:597.11-597.65"
-  process $proc$ls180.v:597$1852
+  attribute \src "ls180.v:610.11-610.65"
+  process $proc$ls180.v:610$1783
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:598.11-598.65"
-  process $proc$ls180.v:598$1853
+  attribute \src "ls180.v:611.11-611.65"
+  process $proc$ls180.v:611$1784
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:599.11-599.68"
-  process $proc$ls180.v:599$1854
+  attribute \src "ls180.v:612.11-612.68"
+  process $proc$ls180.v:612$1785
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:620.5-620.54"
-  process $proc$ls180.v:620$1855
+  attribute \src "ls180.v:62.5-62.41"
+  process $proc$ls180.v:62$1553
+    assign { } { }
+    assign $1\libresocsim_libresoc_dbus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_libresoc_dbus_ack $1\libresocsim_libresoc_dbus_ack[0:0]
+  end
+  attribute \src "ls180.v:633.5-633.54"
+  process $proc$ls180.v:633$1786
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:622.5-622.54"
-  process $proc$ls180.v:622$1856
+  attribute \src "ls180.v:635.5-635.54"
+  process $proc$ls180.v:635$1787
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:623.5-623.53"
-  process $proc$ls180.v:623$1857
+  attribute \src "ls180.v:636.5-636.53"
+  process $proc$ls180.v:636$1788
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0]
   end
-  attribute \src "ls180.v:624.5-624.59"
-  process $proc$ls180.v:624$1858
+  attribute \src "ls180.v:637.5-637.59"
+  process $proc$ls180.v:637$1789
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
   end
-  attribute \src "ls180.v:625.12-625.69"
-  process $proc$ls180.v:625$1859
+  attribute \src "ls180.v:638.12-638.69"
+  process $proc$ls180.v:638$1790
     assign { } { }
     assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
   end
-  attribute \src "ls180.v:626.12-626.42"
-  process $proc$ls180.v:626$1860
+  attribute \src "ls180.v:639.12-639.42"
+  process $proc$ls180.v:639$1791
     assign { } { }
     assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0]
   end
-  attribute \src "ls180.v:627.5-627.41"
-  process $proc$ls180.v:627$1861
+  attribute \src "ls180.v:64.5-64.41"
+  process $proc$ls180.v:64$1554
+    assign { } { }
+    assign $0\libresocsim_libresoc_dbus_err[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_dbus_err $0\libresocsim_libresoc_dbus_err[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:640.5-640.41"
+  process $proc$ls180.v:640$1792
     assign { } { }
     assign $1\sdram_bankmachine2_row_opened[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0]
   end
-  attribute \src "ls180.v:629.5-629.39"
-  process $proc$ls180.v:629$1862
+  attribute \src "ls180.v:642.5-642.39"
+  process $proc$ls180.v:642$1793
     assign { } { }
     assign $1\sdram_bankmachine2_row_open[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0]
   end
-  attribute \src "ls180.v:630.5-630.40"
-  process $proc$ls180.v:630$1863
+  attribute \src "ls180.v:643.5-643.40"
+  process $proc$ls180.v:643$1794
     assign { } { }
     assign $1\sdram_bankmachine2_row_close[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0]
   end
-  attribute \src "ls180.v:631.5-631.49"
-  process $proc$ls180.v:631$1864
+  attribute \src "ls180.v:644.5-644.49"
+  process $proc$ls180.v:644$1795
     assign { } { }
     assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0]
   end
-  attribute \src "ls180.v:633.32-633.71"
-  process $proc$ls180.v:633$1865
+  attribute \src "ls180.v:646.32-646.71"
+  process $proc$ls180.v:646$1796
     assign { } { }
     assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0]
   end
-  attribute \src "ls180.v:634.11-634.50"
-  process $proc$ls180.v:634$1866
+  attribute \src "ls180.v:647.11-647.50"
+  process $proc$ls180.v:647$1797
     assign { } { }
     assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0]
   end
-  attribute \src "ls180.v:636.32-636.70"
-  process $proc$ls180.v:636$1867
+  attribute \src "ls180.v:649.32-649.70"
+  process $proc$ls180.v:649$1798
     assign { } { }
     assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:638.32-638.71"
-  process $proc$ls180.v:638$1868
+  attribute \src "ls180.v:651.32-651.71"
+  process $proc$ls180.v:651$1799
     assign { } { }
     assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:64.11-64.47"
-  process $proc$ls180.v:64$1633
-    assign { } { }
-    assign $0\libresocsim_libresoc_dbus_cti[2:0] 3'000
-    sync always
-      update \libresocsim_libresoc_dbus_cti $0\libresocsim_libresoc_dbus_cti[2:0]
-    sync init
-  end
-  attribute \src "ls180.v:644.5-644.46"
-  process $proc$ls180.v:644$1869
+  attribute \src "ls180.v:657.5-657.46"
+  process $proc$ls180.v:657$1800
     assign { } { }
     assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0]
   end
-  attribute \src "ls180.v:645.5-645.46"
-  process $proc$ls180.v:645$1870
+  attribute \src "ls180.v:658.5-658.46"
+  process $proc$ls180.v:658$1801
     assign { } { }
     assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0]
   end
-  attribute \src "ls180.v:647.5-647.42"
-  process $proc$ls180.v:647$1871
+  attribute \src "ls180.v:660.5-660.42"
+  process $proc$ls180.v:660$1802
     assign { } { }
     assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0]
   end
-  attribute \src "ls180.v:648.5-648.40"
-  process $proc$ls180.v:648$1872
+  attribute \src "ls180.v:661.5-661.40"
+  process $proc$ls180.v:661$1803
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0]
   end
-  attribute \src "ls180.v:649.5-649.40"
-  process $proc$ls180.v:649$1873
+  attribute \src "ls180.v:662.5-662.40"
+  process $proc$ls180.v:662$1804
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:65.11-65.47"
-  process $proc$ls180.v:65$1634
-    assign { } { }
-    assign $0\libresocsim_libresoc_dbus_bte[1:0] 2'00
-    sync always
-      update \libresocsim_libresoc_dbus_bte $0\libresocsim_libresoc_dbus_bte[1:0]
-    sync init
-  end
-  attribute \src "ls180.v:650.12-650.52"
-  process $proc$ls180.v:650$1874
+  attribute \src "ls180.v:663.12-663.52"
+  process $proc$ls180.v:663$1805
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0]
   end
-  attribute \src "ls180.v:652.5-652.46"
-  process $proc$ls180.v:652$1875
+  attribute \src "ls180.v:665.5-665.46"
+  process $proc$ls180.v:665$1806
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:653.5-653.46"
-  process $proc$ls180.v:653$1876
+  attribute \src "ls180.v:666.5-666.46"
+  process $proc$ls180.v:666$1807
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:654.5-654.45"
-  process $proc$ls180.v:654$1877
+  attribute \src "ls180.v:667.5-667.45"
+  process $proc$ls180.v:667$1808
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:655.5-655.49"
-  process $proc$ls180.v:655$1878
+  attribute \src "ls180.v:668.5-668.49"
+  process $proc$ls180.v:668$1809
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
   end
-  attribute \src "ls180.v:656.5-656.50"
-  process $proc$ls180.v:656$1879
+  attribute \src "ls180.v:669.5-669.50"
+  process $proc$ls180.v:669$1810
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0]
   end
-  attribute \src "ls180.v:657.5-657.51"
-  process $proc$ls180.v:657$1880
+  attribute \src "ls180.v:670.5-670.51"
+  process $proc$ls180.v:670$1811
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0]
   end
-  attribute \src "ls180.v:658.5-658.45"
-  process $proc$ls180.v:658$1881
+  attribute \src "ls180.v:671.5-671.45"
+  process $proc$ls180.v:671$1812
     assign { } { }
     assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0]
   end
-  attribute \src "ls180.v:661.5-661.62"
-  process $proc$ls180.v:661$1882
+  attribute \src "ls180.v:674.5-674.62"
+  process $proc$ls180.v:674$1813
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
     sync always
       update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:662.5-662.61"
-  process $proc$ls180.v:662$1883
+  attribute \src "ls180.v:675.5-675.61"
+  process $proc$ls180.v:675$1814
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
     sync always
       update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:677.11-677.63"
-  process $proc$ls180.v:677$1884
+  attribute \src "ls180.v:690.11-690.63"
+  process $proc$ls180.v:690$1815
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
   end
-  attribute \src "ls180.v:678.5-678.59"
-  process $proc$ls180.v:678$1885
+  attribute \src "ls180.v:691.5-691.59"
+  process $proc$ls180.v:691$1816
     assign { } { }
     assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
     sync always
       update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:679.11-679.65"
-  process $proc$ls180.v:679$1886
+  attribute \src "ls180.v:692.11-692.65"
+  process $proc$ls180.v:692$1817
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
   end
-  attribute \src "ls180.v:680.11-680.65"
-  process $proc$ls180.v:680$1887
+  attribute \src "ls180.v:693.11-693.65"
+  process $proc$ls180.v:693$1818
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
   end
-  attribute \src "ls180.v:681.11-681.68"
-  process $proc$ls180.v:681$1888
+  attribute \src "ls180.v:694.11-694.68"
+  process $proc$ls180.v:694$1819
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
   end
-  attribute \src "ls180.v:702.5-702.54"
-  process $proc$ls180.v:702$1889
+  attribute \src "ls180.v:71.5-71.41"
+  process $proc$ls180.v:71$1555
+    assign { } { }
+    assign $1\libresocsim_libresoc_ibus_ack[0:0] 1'0
+    sync always
+    sync init
+      update \libresocsim_libresoc_ibus_ack $1\libresocsim_libresoc_ibus_ack[0:0]
+  end
+  attribute \src "ls180.v:715.5-715.54"
+  process $proc$ls180.v:715$1820
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
   end
-  attribute \src "ls180.v:704.5-704.54"
-  process $proc$ls180.v:704$1890
+  attribute \src "ls180.v:717.5-717.54"
+  process $proc$ls180.v:717$1821
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0]
   end
-  attribute \src "ls180.v:705.5-705.53"
-  process $proc$ls180.v:705$1891
+  attribute \src "ls180.v:718.5-718.53"
+  process $proc$ls180.v:718$1822
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0]
   end
-  attribute \src "ls180.v:706.5-706.59"
-  process $proc$ls180.v:706$1892
+  attribute \src "ls180.v:719.5-719.59"
+  process $proc$ls180.v:719$1823
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
   end
-  attribute \src "ls180.v:707.12-707.69"
-  process $proc$ls180.v:707$1893
+  attribute \src "ls180.v:720.12-720.69"
+  process $proc$ls180.v:720$1824
     assign { } { }
     assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
     sync always
     sync init
       update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
   end
-  attribute \src "ls180.v:708.12-708.42"
-  process $proc$ls180.v:708$1894
+  attribute \src "ls180.v:721.12-721.42"
+  process $proc$ls180.v:721$1825
     assign { } { }
     assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000
     sync always
     sync init
       update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0]
   end
-  attribute \src "ls180.v:709.5-709.41"
-  process $proc$ls180.v:709$1895
+  attribute \src "ls180.v:722.5-722.41"
+  process $proc$ls180.v:722$1826
     assign { } { }
     assign $1\sdram_bankmachine3_row_opened[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0]
   end
-  attribute \src "ls180.v:711.5-711.39"
-  process $proc$ls180.v:711$1896
+  attribute \src "ls180.v:724.5-724.39"
+  process $proc$ls180.v:724$1827
     assign { } { }
     assign $1\sdram_bankmachine3_row_open[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0]
   end
-  attribute \src "ls180.v:712.5-712.40"
-  process $proc$ls180.v:712$1897
+  attribute \src "ls180.v:725.5-725.40"
+  process $proc$ls180.v:725$1828
     assign { } { }
     assign $1\sdram_bankmachine3_row_close[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0]
   end
-  attribute \src "ls180.v:713.5-713.49"
-  process $proc$ls180.v:713$1898
+  attribute \src "ls180.v:726.5-726.49"
+  process $proc$ls180.v:726$1829
     assign { } { }
     assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0]
   end
-  attribute \src "ls180.v:715.32-715.71"
-  process $proc$ls180.v:715$1899
+  attribute \src "ls180.v:728.32-728.71"
+  process $proc$ls180.v:728$1830
     assign { } { }
     assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0]
   end
-  attribute \src "ls180.v:716.11-716.50"
-  process $proc$ls180.v:716$1900
+  attribute \src "ls180.v:729.11-729.50"
+  process $proc$ls180.v:729$1831
     assign { } { }
     assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000
     sync always
     sync init
       update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0]
   end
-  attribute \src "ls180.v:718.32-718.70"
-  process $proc$ls180.v:718$1901
+  attribute \src "ls180.v:73.5-73.41"
+  process $proc$ls180.v:73$1556
+    assign { } { }
+    assign $0\libresocsim_libresoc_ibus_err[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_ibus_err $0\libresocsim_libresoc_ibus_err[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:731.32-731.70"
+  process $proc$ls180.v:731$1832
     assign { } { }
     assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:720.32-720.71"
-  process $proc$ls180.v:720$1902
+  attribute \src "ls180.v:733.32-733.71"
+  process $proc$ls180.v:733$1833
     assign { } { }
     assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1
     sync always
       update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:723.5-723.39"
-  process $proc$ls180.v:723$1903
+  attribute \src "ls180.v:736.5-736.39"
+  process $proc$ls180.v:736$1834
     assign { } { }
     assign $0\sdram_choose_cmd_want_reads[0:0] 1'0
     sync always
       update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0]
     sync init
   end
-  attribute \src "ls180.v:724.5-724.40"
-  process $proc$ls180.v:724$1904
+  attribute \src "ls180.v:737.5-737.40"
+  process $proc$ls180.v:737$1835
     assign { } { }
     assign $0\sdram_choose_cmd_want_writes[0:0] 1'0
     sync always
       update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0]
     sync init
   end
-  attribute \src "ls180.v:725.5-725.38"
-  process $proc$ls180.v:725$1905
+  attribute \src "ls180.v:738.5-738.38"
+  process $proc$ls180.v:738$1836
     assign { } { }
     assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0
     sync always
       update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0]
     sync init
   end
-  attribute \src "ls180.v:726.5-726.43"
-  process $proc$ls180.v:726$1906
+  attribute \src "ls180.v:739.5-739.43"
+  process $proc$ls180.v:739$1837
     assign { } { }
     assign $0\sdram_choose_cmd_want_activates[0:0] 1'0
     sync always
       update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0]
     sync init
   end
-  attribute \src "ls180.v:728.5-728.38"
-  process $proc$ls180.v:728$1907
+  attribute \src "ls180.v:741.5-741.38"
+  process $proc$ls180.v:741$1838
     assign { } { }
     assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0
     sync always
       update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:731.5-731.44"
-  process $proc$ls180.v:731$1908
+  attribute \src "ls180.v:744.5-744.44"
+  process $proc$ls180.v:744$1839
     assign { } { }
     assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:732.5-732.44"
-  process $proc$ls180.v:732$1909
+  attribute \src "ls180.v:745.5-745.44"
+  process $proc$ls180.v:745$1840
     assign { } { }
     assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:733.5-733.43"
-  process $proc$ls180.v:733$1910
+  attribute \src "ls180.v:746.5-746.43"
+  process $proc$ls180.v:746$1841
     assign { } { }
     assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:737.11-737.41"
-  process $proc$ls180.v:737$1911
+  attribute \src "ls180.v:750.11-750.41"
+  process $proc$ls180.v:750$1842
     assign { } { }
     assign $1\sdram_choose_cmd_valids[3:0] 4'0000
     sync always
     sync init
       update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0]
   end
-  attribute \src "ls180.v:739.11-739.40"
-  process $proc$ls180.v:739$1912
+  attribute \src "ls180.v:752.11-752.40"
+  process $proc$ls180.v:752$1843
     assign { } { }
     assign $1\sdram_choose_cmd_grant[1:0] 2'00
     sync always
     sync init
       update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0]
   end
-  attribute \src "ls180.v:741.5-741.39"
-  process $proc$ls180.v:741$1913
+  attribute \src "ls180.v:754.5-754.39"
+  process $proc$ls180.v:754$1844
     assign { } { }
     assign $1\sdram_choose_req_want_reads[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0]
   end
-  attribute \src "ls180.v:742.5-742.40"
-  process $proc$ls180.v:742$1914
+  attribute \src "ls180.v:755.5-755.40"
+  process $proc$ls180.v:755$1845
     assign { } { }
     assign $1\sdram_choose_req_want_writes[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0]
   end
-  attribute \src "ls180.v:744.5-744.43"
-  process $proc$ls180.v:744$1915
+  attribute \src "ls180.v:757.5-757.43"
+  process $proc$ls180.v:757$1846
     assign { } { }
     assign $1\sdram_choose_req_want_activates[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0]
   end
-  attribute \src "ls180.v:746.5-746.38"
-  process $proc$ls180.v:746$1916
+  attribute \src "ls180.v:759.5-759.38"
+  process $proc$ls180.v:759$1847
     assign { } { }
     assign $1\sdram_choose_req_cmd_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0]
   end
-  attribute \src "ls180.v:749.5-749.44"
-  process $proc$ls180.v:749$1917
+  attribute \src "ls180.v:762.5-762.44"
+  process $proc$ls180.v:762$1848
     assign { } { }
     assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0]
   end
-  attribute \src "ls180.v:75.11-75.47"
-  process $proc$ls180.v:75$1635
-    assign { } { }
-    assign $0\libresocsim_libresoc_ibus_cti[2:0] 3'000
-    sync always
-      update \libresocsim_libresoc_ibus_cti $0\libresocsim_libresoc_ibus_cti[2:0]
-    sync init
-  end
-  attribute \src "ls180.v:750.5-750.44"
-  process $proc$ls180.v:750$1918
+  attribute \src "ls180.v:763.5-763.44"
+  process $proc$ls180.v:763$1849
     assign { } { }
     assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0]
   end
-  attribute \src "ls180.v:751.5-751.43"
-  process $proc$ls180.v:751$1919
+  attribute \src "ls180.v:764.5-764.43"
+  process $proc$ls180.v:764$1850
     assign { } { }
     assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0
     sync always
     sync init
       update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0]
   end
-  attribute \src "ls180.v:755.11-755.41"
-  process $proc$ls180.v:755$1920
+  attribute \src "ls180.v:768.11-768.41"
+  process $proc$ls180.v:768$1851
     assign { } { }
     assign $1\sdram_choose_req_valids[3:0] 4'0000
     sync always
     sync init
       update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0]
   end
-  attribute \src "ls180.v:757.11-757.40"
-  process $proc$ls180.v:757$1921
+  attribute \src "ls180.v:770.11-770.40"
+  process $proc$ls180.v:770$1852
     assign { } { }
     assign $1\sdram_choose_req_grant[1:0] 2'00
     sync always
     sync init
       update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0]
   end
-  attribute \src "ls180.v:759.12-759.31"
-  process $proc$ls180.v:759$1922
+  attribute \src "ls180.v:772.12-772.31"
+  process $proc$ls180.v:772$1853
     assign { } { }
     assign $0\sdram_nop_a[12:0] 13'0000000000000
     sync always
       update \sdram_nop_a $0\sdram_nop_a[12:0]
     sync init
   end
-  attribute \src "ls180.v:76.11-76.47"
-  process $proc$ls180.v:76$1636
-    assign { } { }
-    assign $0\libresocsim_libresoc_ibus_bte[1:0] 2'00
-    sync always
-      update \libresocsim_libresoc_ibus_bte $0\libresocsim_libresoc_ibus_bte[1:0]
-    sync init
-  end
-  attribute \src "ls180.v:760.11-760.30"
-  process $proc$ls180.v:760$1923
+  attribute \src "ls180.v:773.11-773.30"
+  process $proc$ls180.v:773$1854
     assign { } { }
     assign $0\sdram_nop_ba[1:0] 2'00
     sync always
       update \sdram_nop_ba $0\sdram_nop_ba[1:0]
     sync init
   end
-  attribute \src "ls180.v:761.11-761.35"
-  process $proc$ls180.v:761$1924
+  attribute \src "ls180.v:774.11-774.35"
+  process $proc$ls180.v:774$1855
     assign { } { }
     assign $1\sdram_steerer_sel[1:0] 2'00
     sync always
     sync init
       update \sdram_steerer_sel $1\sdram_steerer_sel[1:0]
   end
-  attribute \src "ls180.v:762.5-762.26"
-  process $proc$ls180.v:762$1925
+  attribute \src "ls180.v:775.5-775.26"
+  process $proc$ls180.v:775$1856
     assign { } { }
     assign $0\sdram_steerer0[0:0] 1'1
     sync always
       update \sdram_steerer0 $0\sdram_steerer0[0:0]
     sync init
   end
-  attribute \src "ls180.v:763.5-763.26"
-  process $proc$ls180.v:763$1926
+  attribute \src "ls180.v:776.5-776.26"
+  process $proc$ls180.v:776$1857
     assign { } { }
     assign $0\sdram_steerer1[0:0] 1'1
     sync always
       update \sdram_steerer1 $0\sdram_steerer1[0:0]
     sync init
   end
-  attribute \src "ls180.v:765.32-765.58"
-  process $proc$ls180.v:765$1927
+  attribute \src "ls180.v:778.32-778.58"
+  process $proc$ls180.v:778$1858
     assign { } { }
     assign $0\sdram_trrdcon_ready[0:0] 1'1
     sync always
       update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:767.32-767.58"
-  process $proc$ls180.v:767$1928
+  attribute \src "ls180.v:780.32-780.58"
+  process $proc$ls180.v:780$1859
     assign { } { }
     assign $0\sdram_tfawcon_ready[0:0] 1'1
     sync always
       update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:769.32-769.58"
-  process $proc$ls180.v:769$1929
+  attribute \src "ls180.v:782.32-782.58"
+  process $proc$ls180.v:782$1860
     assign { } { }
     assign $1\sdram_tccdcon_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0]
   end
-  attribute \src "ls180.v:770.5-770.31"
-  process $proc$ls180.v:770$1930
+  attribute \src "ls180.v:783.5-783.31"
+  process $proc$ls180.v:783$1861
     assign { } { }
     assign $1\sdram_tccdcon_count[0:0] 1'0
     sync always
     sync init
       update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0]
   end
-  attribute \src "ls180.v:772.32-772.58"
-  process $proc$ls180.v:772$1931
+  attribute \src "ls180.v:785.32-785.58"
+  process $proc$ls180.v:785$1862
     assign { } { }
     assign $1\sdram_twtrcon_ready[0:0] 1'0
     sync always
     sync init
       update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0]
   end
-  attribute \src "ls180.v:773.11-773.37"
-  process $proc$ls180.v:773$1932
+  attribute \src "ls180.v:786.11-786.37"
+  process $proc$ls180.v:786$1863
     assign { } { }
     assign $1\sdram_twtrcon_count[2:0] 3'000
     sync always
     sync init
       update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0]
   end
-  attribute \src "ls180.v:776.5-776.21"
-  process $proc$ls180.v:776$1933
+  attribute \src "ls180.v:789.5-789.21"
+  process $proc$ls180.v:789$1864
     assign { } { }
     assign $1\sdram_en0[0:0] 1'0
     sync always
     sync init
       update \sdram_en0 $1\sdram_en0[0:0]
   end
-  attribute \src "ls180.v:778.11-778.29"
-  process $proc$ls180.v:778$1934
+  attribute \src "ls180.v:791.11-791.29"
+  process $proc$ls180.v:791$1865
     assign { } { }
     assign $1\sdram_time0[4:0] 5'00000
     sync always
     sync init
       update \sdram_time0 $1\sdram_time0[4:0]
   end
-  attribute \src "ls180.v:779.5-779.21"
-  process $proc$ls180.v:779$1935
+  attribute \src "ls180.v:792.5-792.21"
+  process $proc$ls180.v:792$1866
     assign { } { }
     assign $1\sdram_en1[0:0] 1'0
     sync always
     sync init
       update \sdram_en1 $1\sdram_en1[0:0]
   end
-  attribute \src "ls180.v:78.12-78.53"
-  process $proc$ls180.v:78$1637
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_adr $1\libresocsim_libresoc_xics_icp_adr[29:0]
-  end
-  attribute \src "ls180.v:781.11-781.29"
-  process $proc$ls180.v:781$1936
+  attribute \src "ls180.v:794.11-794.29"
+  process $proc$ls180.v:794$1867
     assign { } { }
     assign $1\sdram_time1[3:0] 4'0000
     sync always
     sync init
       update \sdram_time1 $1\sdram_time1[3:0]
   end
-  attribute \src "ls180.v:79.12-79.55"
-  process $proc$ls180.v:79$1638
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_dat_w $1\libresocsim_libresoc_xics_icp_dat_w[31:0]
-  end
-  attribute \src "ls180.v:796.12-796.32"
-  process $proc$ls180.v:796$1937
-    assign { } { }
-    assign $1\wb_sdram_adr[29:0] 30'000000000000000000000000000000
-    sync always
-    sync init
-      update \wb_sdram_adr $1\wb_sdram_adr[29:0]
-  end
-  attribute \src "ls180.v:797.12-797.34"
-  process $proc$ls180.v:797$1938
-    assign { } { }
-    assign $1\wb_sdram_dat_w[31:0] 0
-    sync always
-    sync init
-      update \wb_sdram_dat_w $1\wb_sdram_dat_w[31:0]
-  end
-  attribute \src "ls180.v:799.11-799.30"
-  process $proc$ls180.v:799$1939
-    assign { } { }
-    assign $1\wb_sdram_sel[3:0] 4'0000
-    sync always
-    sync init
-      update \wb_sdram_sel $1\wb_sdram_sel[3:0]
-  end
-  attribute \src "ls180.v:800.5-800.24"
-  process $proc$ls180.v:800$1940
-    assign { } { }
-    assign $1\wb_sdram_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \wb_sdram_cyc $1\wb_sdram_cyc[0:0]
-  end
-  attribute \src "ls180.v:801.5-801.24"
-  process $proc$ls180.v:801$1941
-    assign { } { }
-    assign $1\wb_sdram_stb[0:0] 1'0
-    sync always
-    sync init
-      update \wb_sdram_stb $1\wb_sdram_stb[0:0]
-  end
-  attribute \src "ls180.v:802.5-802.24"
-  process $proc$ls180.v:802$1942
+  attribute \src "ls180.v:815.5-815.24"
+  process $proc$ls180.v:815$1868
     assign { } { }
     assign $1\wb_sdram_ack[0:0] 1'0
     sync always
     sync init
       update \wb_sdram_ack $1\wb_sdram_ack[0:0]
   end
-  attribute \src "ls180.v:803.5-803.23"
-  process $proc$ls180.v:803$1943
-    assign { } { }
-    assign $1\wb_sdram_we[0:0] 1'0
-    sync always
-    sync init
-      update \wb_sdram_we $1\wb_sdram_we[0:0]
-  end
-  attribute \src "ls180.v:81.11-81.51"
-  process $proc$ls180.v:81$1639
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_sel $1\libresocsim_libresoc_xics_icp_sel[3:0]
-  end
-  attribute \src "ls180.v:810.5-810.49"
-  process $proc$ls180.v:810$1944
+  attribute \src "ls180.v:819.5-819.24"
+  process $proc$ls180.v:819$1869
     assign { } { }
-    assign $1\socbushandler_converted_interface_ack[0:0] 1'0
+    assign $0\wb_sdram_err[0:0] 1'0
     sync always
+      update \wb_sdram_err $0\wb_sdram_err[0:0]
     sync init
-      update \socbushandler_converted_interface_ack $1\socbushandler_converted_interface_ack[0:0]
   end
-  attribute \src "ls180.v:814.5-814.49"
-  process $proc$ls180.v:814$1945
-    assign { } { }
-    assign $0\socbushandler_converted_interface_err[0:0] 1'0
-    sync always
-      update \socbushandler_converted_interface_err $0\socbushandler_converted_interface_err[0:0]
-    sync init
-  end
-  attribute \src "ls180.v:815.5-815.30"
-  process $proc$ls180.v:815$1946
-    assign { } { }
-    assign $1\socbushandler_skip[0:0] 1'0
-    sync always
-    sync init
-      update \socbushandler_skip $1\socbushandler_skip[0:0]
-  end
-  attribute \src "ls180.v:816.5-816.33"
-  process $proc$ls180.v:816$1947
-    assign { } { }
-    assign $1\socbushandler_counter[0:0] 1'0
-    sync always
-    sync init
-      update \socbushandler_counter $1\socbushandler_counter[0:0]
-  end
-  attribute \src "ls180.v:818.12-818.39"
-  process $proc$ls180.v:818$1948
-    assign { } { }
-    assign $1\socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync always
-    sync init
-      update \socbushandler_dat_r $1\socbushandler_dat_r[63:0]
-  end
-  attribute \src "ls180.v:819.12-819.35"
-  process $proc$ls180.v:819$1949
+  attribute \src "ls180.v:820.12-820.35"
+  process $proc$ls180.v:820$1870
     assign { } { }
     assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000
     sync always
     sync init
       update \litedram_wb_adr $1\litedram_wb_adr[29:0]
   end
-  attribute \src "ls180.v:82.5-82.45"
-  process $proc$ls180.v:82$1640
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_cyc $1\libresocsim_libresoc_xics_icp_cyc[0:0]
-  end
-  attribute \src "ls180.v:820.12-820.37"
-  process $proc$ls180.v:820$1950
+  attribute \src "ls180.v:821.12-821.37"
+  process $proc$ls180.v:821$1871
     assign { } { }
     assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000
     sync always
     sync init
       update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0]
   end
-  attribute \src "ls180.v:822.11-822.33"
-  process $proc$ls180.v:822$1951
+  attribute \src "ls180.v:823.11-823.33"
+  process $proc$ls180.v:823$1872
     assign { } { }
     assign $1\litedram_wb_sel[1:0] 2'00
     sync always
     sync init
       update \litedram_wb_sel $1\litedram_wb_sel[1:0]
   end
-  attribute \src "ls180.v:823.5-823.27"
-  process $proc$ls180.v:823$1952
+  attribute \src "ls180.v:824.5-824.27"
+  process $proc$ls180.v:824$1873
     assign { } { }
     assign $1\litedram_wb_cyc[0:0] 1'0
     sync always
     sync init
       update \litedram_wb_cyc $1\litedram_wb_cyc[0:0]
   end
-  attribute \src "ls180.v:824.5-824.27"
-  process $proc$ls180.v:824$1953
+  attribute \src "ls180.v:825.5-825.27"
+  process $proc$ls180.v:825$1874
     assign { } { }
     assign $1\litedram_wb_stb[0:0] 1'0
     sync always
     sync init
       update \litedram_wb_stb $1\litedram_wb_stb[0:0]
   end
-  attribute \src "ls180.v:826.5-826.26"
-  process $proc$ls180.v:826$1954
+  attribute \src "ls180.v:827.5-827.26"
+  process $proc$ls180.v:827$1875
     assign { } { }
     assign $1\litedram_wb_we[0:0] 1'0
     sync always
     sync init
       update \litedram_wb_we $1\litedram_wb_we[0:0]
   end
-  attribute \src "ls180.v:827.5-827.26"
-  process $proc$ls180.v:827$1955
+  attribute \src "ls180.v:828.5-828.26"
+  process $proc$ls180.v:828$1876
     assign { } { }
     assign $1\converter_skip[0:0] 1'0
     sync always
     sync init
       update \converter_skip $1\converter_skip[0:0]
   end
-  attribute \src "ls180.v:828.5-828.29"
-  process $proc$ls180.v:828$1956
+  attribute \src "ls180.v:829.5-829.29"
+  process $proc$ls180.v:829$1877
     assign { } { }
     assign $1\converter_counter[0:0] 1'0
     sync always
     sync init
       update \converter_counter $1\converter_counter[0:0]
   end
-  attribute \src "ls180.v:83.5-83.45"
-  process $proc$ls180.v:83$1641
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_stb[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_stb $1\libresocsim_libresoc_xics_icp_stb[0:0]
-  end
-  attribute \src "ls180.v:830.12-830.35"
-  process $proc$ls180.v:830$1957
+  attribute \src "ls180.v:831.12-831.35"
+  process $proc$ls180.v:831$1878
     assign { } { }
     assign $1\converter_dat_r[31:0] 0
     sync always
     sync init
       update \converter_dat_r $1\converter_dat_r[31:0]
   end
-  attribute \src "ls180.v:831.5-831.24"
-  process $proc$ls180.v:831$1958
+  attribute \src "ls180.v:832.5-832.24"
+  process $proc$ls180.v:832$1879
     assign { } { }
     assign $1\cmd_consumed[0:0] 1'0
     sync always
     sync init
       update \cmd_consumed $1\cmd_consumed[0:0]
   end
-  attribute \src "ls180.v:832.5-832.26"
-  process $proc$ls180.v:832$1959
+  attribute \src "ls180.v:833.5-833.26"
+  process $proc$ls180.v:833$1880
     assign { } { }
     assign $1\wdata_consumed[0:0] 1'0
     sync always
     sync init
       update \wdata_consumed $1\wdata_consumed[0:0]
   end
-  attribute \src "ls180.v:836.12-836.42"
-  process $proc$ls180.v:836$1960
+  attribute \src "ls180.v:837.12-837.42"
+  process $proc$ls180.v:837$1881
     assign { } { }
     assign $1\uart_phy_storage[31:0] 9895604
     sync always
     sync init
       update \uart_phy_storage $1\uart_phy_storage[31:0]
   end
-  attribute \src "ls180.v:837.5-837.23"
-  process $proc$ls180.v:837$1961
+  attribute \src "ls180.v:838.5-838.23"
+  process $proc$ls180.v:838$1882
     assign { } { }
     assign $1\uart_phy_re[0:0] 1'0
     sync always
     sync init
       update \uart_phy_re $1\uart_phy_re[0:0]
   end
-  attribute \src "ls180.v:839.5-839.31"
-  process $proc$ls180.v:839$1962
+  attribute \src "ls180.v:840.5-840.31"
+  process $proc$ls180.v:840$1883
     assign { } { }
     assign $1\uart_phy_sink_ready[0:0] 1'0
     sync always
     sync init
       update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0]
   end
-  attribute \src "ls180.v:843.5-843.34"
-  process $proc$ls180.v:843$1963
+  attribute \src "ls180.v:844.5-844.34"
+  process $proc$ls180.v:844$1884
     assign { } { }
     assign $1\uart_phy_uart_clk_txen[0:0] 1'0
     sync always
     sync init
       update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0]
   end
-  attribute \src "ls180.v:844.12-844.49"
-  process $proc$ls180.v:844$1964
+  attribute \src "ls180.v:845.12-845.49"
+  process $proc$ls180.v:845$1885
     assign { } { }
     assign $1\uart_phy_phase_accumulator_tx[31:0] 0
     sync always
     sync init
       update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0]
   end
-  attribute \src "ls180.v:845.11-845.33"
-  process $proc$ls180.v:845$1965
+  attribute \src "ls180.v:846.11-846.33"
+  process $proc$ls180.v:846$1886
     assign { } { }
     assign $1\uart_phy_tx_reg[7:0] 8'00000000
     sync always
     sync init
       update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0]
   end
-  attribute \src "ls180.v:846.11-846.38"
-  process $proc$ls180.v:846$1966
+  attribute \src "ls180.v:847.11-847.38"
+  process $proc$ls180.v:847$1887
     assign { } { }
     assign $1\uart_phy_tx_bitcount[3:0] 4'0000
     sync always
     sync init
       update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0]
   end
-  attribute \src "ls180.v:847.5-847.28"
-  process $proc$ls180.v:847$1967
+  attribute \src "ls180.v:848.5-848.28"
+  process $proc$ls180.v:848$1888
     assign { } { }
     assign $1\uart_phy_tx_busy[0:0] 1'0
     sync always
     sync init
       update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0]
   end
-  attribute \src "ls180.v:848.5-848.33"
-  process $proc$ls180.v:848$1968
+  attribute \src "ls180.v:849.5-849.33"
+  process $proc$ls180.v:849$1889
     assign { } { }
     assign $1\uart_phy_source_valid[0:0] 1'0
     sync always
     sync init
       update \uart_phy_source_valid $1\uart_phy_source_valid[0:0]
   end
-  attribute \src "ls180.v:85.5-85.44"
-  process $proc$ls180.v:85$1642
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_icp_we[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_icp_we $1\libresocsim_libresoc_xics_icp_we[0:0]
-  end
-  attribute \src "ls180.v:850.5-850.33"
-  process $proc$ls180.v:850$1969
+  attribute \src "ls180.v:851.5-851.33"
+  process $proc$ls180.v:851$1890
     assign { } { }
     assign $0\uart_phy_source_first[0:0] 1'0
     sync always
       update \uart_phy_source_first $0\uart_phy_source_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:851.5-851.32"
-  process $proc$ls180.v:851$1970
+  attribute \src "ls180.v:852.5-852.32"
+  process $proc$ls180.v:852$1891
     assign { } { }
     assign $0\uart_phy_source_last[0:0] 1'0
     sync always
       update \uart_phy_source_last $0\uart_phy_source_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:852.11-852.46"
-  process $proc$ls180.v:852$1971
+  attribute \src "ls180.v:853.11-853.46"
+  process $proc$ls180.v:853$1892
     assign { } { }
     assign $1\uart_phy_source_payload_data[7:0] 8'00000000
     sync always
     sync init
       update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0]
   end
-  attribute \src "ls180.v:853.5-853.34"
-  process $proc$ls180.v:853$1972
+  attribute \src "ls180.v:854.5-854.34"
+  process $proc$ls180.v:854$1893
     assign { } { }
     assign $1\uart_phy_uart_clk_rxen[0:0] 1'0
     sync always
     sync init
       update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0]
   end
-  attribute \src "ls180.v:854.12-854.49"
-  process $proc$ls180.v:854$1973
+  attribute \src "ls180.v:855.12-855.49"
+  process $proc$ls180.v:855$1894
     assign { } { }
     assign $1\uart_phy_phase_accumulator_rx[31:0] 0
     sync always
     sync init
       update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0]
   end
-  attribute \src "ls180.v:856.5-856.25"
-  process $proc$ls180.v:856$1974
+  attribute \src "ls180.v:857.5-857.25"
+  process $proc$ls180.v:857$1895
     assign { } { }
     assign $1\uart_phy_rx_r[0:0] 1'0
     sync always
     sync init
       update \uart_phy_rx_r $1\uart_phy_rx_r[0:0]
   end
-  attribute \src "ls180.v:857.11-857.33"
-  process $proc$ls180.v:857$1975
+  attribute \src "ls180.v:858.11-858.33"
+  process $proc$ls180.v:858$1896
     assign { } { }
     assign $1\uart_phy_rx_reg[7:0] 8'00000000
     sync always
     sync init
       update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0]
   end
-  attribute \src "ls180.v:858.11-858.38"
-  process $proc$ls180.v:858$1976
+  attribute \src "ls180.v:859.11-859.38"
+  process $proc$ls180.v:859$1897
     assign { } { }
     assign $1\uart_phy_rx_bitcount[3:0] 4'0000
     sync always
     sync init
       update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0]
   end
-  attribute \src "ls180.v:859.5-859.28"
-  process $proc$ls180.v:859$1977
+  attribute \src "ls180.v:860.5-860.28"
+  process $proc$ls180.v:860$1898
     assign { } { }
     assign $1\uart_phy_rx_busy[0:0] 1'0
     sync always
     sync init
       update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0]
   end
-  attribute \src "ls180.v:87.12-87.53"
-  process $proc$ls180.v:87$1643
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_adr $1\libresocsim_libresoc_xics_ics_adr[29:0]
-  end
-  attribute \src "ls180.v:870.5-870.22"
-  process $proc$ls180.v:870$1978
+  attribute \src "ls180.v:871.5-871.22"
+  process $proc$ls180.v:871$1899
     assign { } { }
     assign $1\tx_pending[0:0] 1'0
     sync always
     sync init
       update \tx_pending $1\tx_pending[0:0]
   end
-  attribute \src "ls180.v:872.5-872.20"
-  process $proc$ls180.v:872$1979
+  attribute \src "ls180.v:873.5-873.20"
+  process $proc$ls180.v:873$1900
     assign { } { }
     assign $1\tx_clear[0:0] 1'0
     sync always
     sync init
       update \tx_clear $1\tx_clear[0:0]
   end
-  attribute \src "ls180.v:873.5-873.26"
-  process $proc$ls180.v:873$1980
+  attribute \src "ls180.v:874.5-874.26"
+  process $proc$ls180.v:874$1901
     assign { } { }
     assign $1\tx_old_trigger[0:0] 1'0
     sync always
     sync init
       update \tx_old_trigger $1\tx_old_trigger[0:0]
   end
-  attribute \src "ls180.v:875.5-875.22"
-  process $proc$ls180.v:875$1981
+  attribute \src "ls180.v:876.5-876.22"
+  process $proc$ls180.v:876$1902
     assign { } { }
     assign $1\rx_pending[0:0] 1'0
     sync always
     sync init
       update \rx_pending $1\rx_pending[0:0]
   end
-  attribute \src "ls180.v:877.5-877.20"
-  process $proc$ls180.v:877$1982
+  attribute \src "ls180.v:878.5-878.20"
+  process $proc$ls180.v:878$1903
     assign { } { }
     assign $1\rx_clear[0:0] 1'0
     sync always
     sync init
       update \rx_clear $1\rx_clear[0:0]
   end
-  attribute \src "ls180.v:878.5-878.26"
-  process $proc$ls180.v:878$1983
+  attribute \src "ls180.v:879.5-879.26"
+  process $proc$ls180.v:879$1904
     assign { } { }
     assign $1\rx_old_trigger[0:0] 1'0
     sync always
     sync init
       update \rx_old_trigger $1\rx_old_trigger[0:0]
   end
-  attribute \src "ls180.v:88.12-88.55"
-  process $proc$ls180.v:88$1644
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_dat_w[31:0] 0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_dat_w $1\libresocsim_libresoc_xics_ics_dat_w[31:0]
-  end
-  attribute \src "ls180.v:882.11-882.39"
-  process $proc$ls180.v:882$1984
+  attribute \src "ls180.v:883.11-883.39"
+  process $proc$ls180.v:883$1905
     assign { } { }
     assign $1\eventmanager_status_w[1:0] 2'00
     sync always
     sync init
       update \eventmanager_status_w $1\eventmanager_status_w[1:0]
   end
-  attribute \src "ls180.v:886.11-886.40"
-  process $proc$ls180.v:886$1985
+  attribute \src "ls180.v:887.11-887.40"
+  process $proc$ls180.v:887$1906
     assign { } { }
     assign $1\eventmanager_pending_w[1:0] 2'00
     sync always
     sync init
       update \eventmanager_pending_w $1\eventmanager_pending_w[1:0]
   end
-  attribute \src "ls180.v:887.11-887.38"
-  process $proc$ls180.v:887$1986
+  attribute \src "ls180.v:888.11-888.38"
+  process $proc$ls180.v:888$1907
     assign { } { }
     assign $1\eventmanager_storage[1:0] 2'00
     sync always
     sync init
       update \eventmanager_storage $1\eventmanager_storage[1:0]
   end
-  attribute \src "ls180.v:888.5-888.27"
-  process $proc$ls180.v:888$1987
+  attribute \src "ls180.v:889.5-889.27"
+  process $proc$ls180.v:889$1908
     assign { } { }
     assign $1\eventmanager_re[0:0] 1'0
     sync always
     sync init
       update \eventmanager_re $1\eventmanager_re[0:0]
   end
-  attribute \src "ls180.v:90.11-90.51"
-  process $proc$ls180.v:90$1645
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_sel $1\libresocsim_libresoc_xics_ics_sel[3:0]
-  end
-  attribute \src "ls180.v:905.5-905.30"
-  process $proc$ls180.v:905$1988
+  attribute \src "ls180.v:906.5-906.30"
+  process $proc$ls180.v:906$1909
     assign { } { }
     assign $0\tx_fifo_sink_first[0:0] 1'0
     sync always
       update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0]
     sync init
   end
-  attribute \src "ls180.v:906.5-906.29"
-  process $proc$ls180.v:906$1989
+  attribute \src "ls180.v:907.5-907.29"
+  process $proc$ls180.v:907$1910
     assign { } { }
     assign $0\tx_fifo_sink_last[0:0] 1'0
     sync always
       update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0]
     sync init
   end
-  attribute \src "ls180.v:91.5-91.45"
-  process $proc$ls180.v:91$1646
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_cyc $1\libresocsim_libresoc_xics_ics_cyc[0:0]
-  end
-  attribute \src "ls180.v:914.5-914.28"
-  process $proc$ls180.v:914$1990
+  attribute \src "ls180.v:915.5-915.28"
+  process $proc$ls180.v:915$1911
     assign { } { }
     assign $1\tx_fifo_readable[0:0] 1'0
     sync always
     sync init
       update \tx_fifo_readable $1\tx_fifo_readable[0:0]
   end
-  attribute \src "ls180.v:92.5-92.45"
-  process $proc$ls180.v:92$1647
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_stb[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_stb $1\libresocsim_libresoc_xics_ics_stb[0:0]
-  end
-  attribute \src "ls180.v:921.11-921.32"
-  process $proc$ls180.v:921$1991
+  attribute \src "ls180.v:922.11-922.32"
+  process $proc$ls180.v:922$1912
     assign { } { }
     assign $1\tx_fifo_level0[4:0] 5'00000
     sync always
     sync init
       update \tx_fifo_level0 $1\tx_fifo_level0[4:0]
   end
-  attribute \src "ls180.v:922.5-922.27"
-  process $proc$ls180.v:922$1992
+  attribute \src "ls180.v:923.5-923.27"
+  process $proc$ls180.v:923$1913
     assign { } { }
     assign $0\tx_fifo_replace[0:0] 1'0
     sync always
       update \tx_fifo_replace $0\tx_fifo_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:923.11-923.33"
-  process $proc$ls180.v:923$1993
+  attribute \src "ls180.v:924.11-924.33"
+  process $proc$ls180.v:924$1914
     assign { } { }
     assign $1\tx_fifo_produce[3:0] 4'0000
     sync always
     sync init
       update \tx_fifo_produce $1\tx_fifo_produce[3:0]
   end
-  attribute \src "ls180.v:924.11-924.33"
-  process $proc$ls180.v:924$1994
+  attribute \src "ls180.v:925.11-925.33"
+  process $proc$ls180.v:925$1915
     assign { } { }
     assign $1\tx_fifo_consume[3:0] 4'0000
     sync always
     sync init
       update \tx_fifo_consume $1\tx_fifo_consume[3:0]
   end
-  attribute \src "ls180.v:925.11-925.36"
-  process $proc$ls180.v:925$1995
+  attribute \src "ls180.v:926.11-926.36"
+  process $proc$ls180.v:926$1916
     assign { } { }
     assign $1\tx_fifo_wrport_adr[3:0] 4'0000
     sync always
     sync init
       update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:94.5-94.44"
-  process $proc$ls180.v:94$1648
-    assign { } { }
-    assign $1\libresocsim_libresoc_xics_ics_we[0:0] 1'0
-    sync always
-    sync init
-      update \libresocsim_libresoc_xics_ics_we $1\libresocsim_libresoc_xics_ics_we[0:0]
-  end
-  attribute \src "ls180.v:951.5-951.28"
-  process $proc$ls180.v:951$1996
+  attribute \src "ls180.v:952.5-952.28"
+  process $proc$ls180.v:952$1917
     assign { } { }
     assign $1\rx_fifo_readable[0:0] 1'0
     sync always
     sync init
       update \rx_fifo_readable $1\rx_fifo_readable[0:0]
   end
-  attribute \src "ls180.v:958.11-958.32"
-  process $proc$ls180.v:958$1997
+  attribute \src "ls180.v:959.11-959.32"
+  process $proc$ls180.v:959$1918
     assign { } { }
     assign $1\rx_fifo_level0[4:0] 5'00000
     sync always
     sync init
       update \rx_fifo_level0 $1\rx_fifo_level0[4:0]
   end
-  attribute \src "ls180.v:959.5-959.27"
-  process $proc$ls180.v:959$1998
+  attribute \src "ls180.v:960.5-960.27"
+  process $proc$ls180.v:960$1919
     assign { } { }
     assign $0\rx_fifo_replace[0:0] 1'0
     sync always
       update \rx_fifo_replace $0\rx_fifo_replace[0:0]
     sync init
   end
-  attribute \src "ls180.v:960.11-960.33"
-  process $proc$ls180.v:960$1999
+  attribute \src "ls180.v:961.11-961.33"
+  process $proc$ls180.v:961$1920
     assign { } { }
     assign $1\rx_fifo_produce[3:0] 4'0000
     sync always
     sync init
       update \rx_fifo_produce $1\rx_fifo_produce[3:0]
   end
-  attribute \src "ls180.v:961.11-961.33"
-  process $proc$ls180.v:961$2000
+  attribute \src "ls180.v:962.11-962.33"
+  process $proc$ls180.v:962$1921
     assign { } { }
     assign $1\rx_fifo_consume[3:0] 4'0000
     sync always
     sync init
       update \rx_fifo_consume $1\rx_fifo_consume[3:0]
   end
-  attribute \src "ls180.v:962.11-962.36"
-  process $proc$ls180.v:962$2001
+  attribute \src "ls180.v:963.11-963.36"
+  process $proc$ls180.v:963$1922
     assign { } { }
     assign $1\rx_fifo_wrport_adr[3:0] 4'0000
     sync always
     sync init
       update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0]
   end
-  attribute \src "ls180.v:977.5-977.17"
-  process $proc$ls180.v:977$2002
+  attribute \src "ls180.v:978.5-978.17"
+  process $proc$ls180.v:978$1923
     assign { } { }
     assign $0\reset[0:0] 1'0
     sync always
       update \reset $0\reset[0:0]
     sync init
   end
-  attribute \src "ls180.v:978.11-978.34"
-  process $proc$ls180.v:978$2003
+  attribute \src "ls180.v:979.11-979.34"
+  process $proc$ls180.v:979$1924
     assign { } { }
     assign $1\gpio0_oe_storage[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_oe_storage $1\gpio0_oe_storage[7:0]
   end
-  attribute \src "ls180.v:979.5-979.23"
-  process $proc$ls180.v:979$2004
+  attribute \src "ls180.v:980.5-980.23"
+  process $proc$ls180.v:980$1925
     assign { } { }
     assign $1\gpio0_oe_re[0:0] 1'0
     sync always
     sync init
       update \gpio0_oe_re $1\gpio0_oe_re[0:0]
   end
-  attribute \src "ls180.v:980.11-980.30"
-  process $proc$ls180.v:980$2005
+  attribute \src "ls180.v:981.11-981.30"
+  process $proc$ls180.v:981$1926
     assign { } { }
     assign $1\gpio0_status[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_status $1\gpio0_status[7:0]
   end
-  attribute \src "ls180.v:982.11-982.35"
-  process $proc$ls180.v:982$2006
+  attribute \src "ls180.v:983.11-983.35"
+  process $proc$ls180.v:983$1927
     assign { } { }
     assign $1\gpio0_out_storage[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_out_storage $1\gpio0_out_storage[7:0]
   end
-  attribute \src "ls180.v:983.5-983.24"
-  process $proc$ls180.v:983$2007
+  attribute \src "ls180.v:984.5-984.24"
+  process $proc$ls180.v:984$1928
     assign { } { }
     assign $1\gpio0_out_re[0:0] 1'0
     sync always
     sync init
       update \gpio0_out_re $1\gpio0_out_re[0:0]
   end
-  attribute \src "ls180.v:984.11-984.35"
-  process $proc$ls180.v:984$2008
+  attribute \src "ls180.v:985.11-985.35"
+  process $proc$ls180.v:985$1929
     assign { } { }
     assign $1\gpio0_pads_gpio0i[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0]
   end
-  attribute \src "ls180.v:985.11-985.35"
-  process $proc$ls180.v:985$2009
+  attribute \src "ls180.v:986.11-986.35"
+  process $proc$ls180.v:986$1930
     assign { } { }
     assign $1\gpio0_pads_gpio0o[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0]
   end
-  attribute \src "ls180.v:986.11-986.36"
-  process $proc$ls180.v:986$2010
+  attribute \src "ls180.v:987.11-987.36"
+  process $proc$ls180.v:987$1931
     assign { } { }
     assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000
     sync always
     sync init
       update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0]
   end
-  attribute \src "ls180.v:987.11-987.34"
-  process $proc$ls180.v:987$2011
+  attribute \src "ls180.v:988.11-988.34"
+  process $proc$ls180.v:988$1932
     assign { } { }
     assign $1\gpio1_oe_storage[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_oe_storage $1\gpio1_oe_storage[7:0]
   end
-  attribute \src "ls180.v:988.5-988.23"
-  process $proc$ls180.v:988$2012
+  attribute \src "ls180.v:989.5-989.23"
+  process $proc$ls180.v:989$1933
     assign { } { }
     assign $1\gpio1_oe_re[0:0] 1'0
     sync always
     sync init
       update \gpio1_oe_re $1\gpio1_oe_re[0:0]
   end
-  attribute \src "ls180.v:989.11-989.30"
-  process $proc$ls180.v:989$2013
+  attribute \src "ls180.v:990.11-990.30"
+  process $proc$ls180.v:990$1934
     assign { } { }
     assign $1\gpio1_status[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_status $1\gpio1_status[7:0]
   end
-  attribute \src "ls180.v:991.11-991.35"
-  process $proc$ls180.v:991$2014
+  attribute \src "ls180.v:992.11-992.35"
+  process $proc$ls180.v:992$1935
     assign { } { }
     assign $1\gpio1_out_storage[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_out_storage $1\gpio1_out_storage[7:0]
   end
-  attribute \src "ls180.v:992.5-992.24"
-  process $proc$ls180.v:992$2015
+  attribute \src "ls180.v:993.5-993.24"
+  process $proc$ls180.v:993$1936
     assign { } { }
     assign $1\gpio1_out_re[0:0] 1'0
     sync always
     sync init
       update \gpio1_out_re $1\gpio1_out_re[0:0]
   end
-  attribute \src "ls180.v:993.11-993.35"
-  process $proc$ls180.v:993$2016
+  attribute \src "ls180.v:994.11-994.35"
+  process $proc$ls180.v:994$1937
     assign { } { }
     assign $1\gpio1_pads_gpio1i[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0]
   end
-  attribute \src "ls180.v:994.11-994.35"
-  process $proc$ls180.v:994$2017
+  attribute \src "ls180.v:995.11-995.35"
+  process $proc$ls180.v:995$1938
     assign { } { }
     assign $1\gpio1_pads_gpio1o[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0]
   end
-  attribute \src "ls180.v:995.11-995.36"
-  process $proc$ls180.v:995$2018
+  attribute \src "ls180.v:996.11-996.36"
+  process $proc$ls180.v:996$1939
     assign { } { }
     assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000
     sync always
     sync init
       update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0]
   end
-  attribute \src "ls180.v:996.11-996.26"
-  process $proc$ls180.v:996$2019
+  attribute \src "ls180.v:997.11-997.26"
+  process $proc$ls180.v:997$1940
     assign { } { }
     assign $1\eint_tmp[2:0] 3'000
     sync always
     sync init
       update \eint_tmp $1\eint_tmp[2:0]
   end
-  attribute \src "ls180.v:998.12-998.25"
-  process $proc$ls180.v:998$2020
+  attribute \src "ls180.v:999.12-999.25"
+  process $proc$ls180.v:999$1941
     assign { } { }
     assign $1\dummy[35:0] 36'000000000000000000000000000000000000
     sync always
@@ -271929,23 +271149,23 @@ module \ls180
   connect \jtag_tdo \libresocsim_libresoc_jtag_tdo
   connect \nc_1 \nc
   connect \libresocsim_bus_error \libresocsim_error
-  connect \converter0_reset $not$ls180.v:1526$25_Y
-  connect \interface0_converted_interface_dat_r { \libresocsim_libresoc_xics_icp_dat_r \converter0_dat_r [63:32] }
-  connect \converter1_reset $not$ls180.v:1586$36_Y
-  connect \interface1_converted_interface_dat_r { \libresocsim_libresoc_xics_ics_dat_r \converter1_dat_r [63:32] }
-  connect \socbushandler_reset $not$ls180.v:1646$47_Y
-  connect \socbushandler_converted_interface_dat_r { \wb_sdram_dat_r \socbushandler_dat_r [63:32] }
+  connect \libresocsim_converter0_reset $not$ls180.v:1519$17_Y
+  connect \libresocsim_libresoc_ibus_dat_r { \libresocsim_interface0_converted_interface_dat_r \libresocsim_converter0_dat_r [63:32] }
+  connect \libresocsim_converter1_reset $not$ls180.v:1579$28_Y
+  connect \libresocsim_libresoc_dbus_dat_r { \libresocsim_interface1_converted_interface_dat_r \libresocsim_converter1_dat_r [63:32] }
+  connect \libresocsim_converter2_reset $not$ls180.v:1639$39_Y
+  connect \libresocsim_libresoc_jtag_wb_dat_r { \libresocsim_interface2_converted_interface_dat_r \libresocsim_converter2_dat_r [63:32] }
   connect \libresocsim_reset \libresocsim_reset_re
   connect \libresocsim_bus_errors_status \libresocsim_bus_errors
-  connect \libresocsim_adr \libresocsim_ram_bus_adr [5:0]
+  connect \libresocsim_adr \libresocsim_ram_bus_adr [6:0]
   connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r
   connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w
-  connect \libresocsim_zero_trigger $ne$ls180.v:1722$83_Y
+  connect \libresocsim_zero_trigger $ne$ls180.v:1711$63_Y
   connect \libresocsim_eventmanager_status_w \libresocsim_zero_status
   connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending
-  connect \libresocsim_irq $and$ls180.v:1731$86_Y
+  connect \libresocsim_irq $and$ls180.v:1720$66_Y
   connect \libresocsim_zero_status \libresocsim_zero_trigger
-  connect \ram_adr \ram_bus_ram_bus_adr [3:0]
+  connect \ram_adr \ram_bus_ram_bus_adr [4:0]
   connect \ram_bus_ram_bus_dat_r \ram_dat_r
   connect \ram_dat_w \ram_bus_ram_bus_dat_w
   connect \sys_clk_1 \sys_clk
@@ -271988,8 +271208,8 @@ module \ls180
   connect \sdram_inti_p0_reset_n \sdram_reset_n
   connect \sdram_inti_p0_address \sdram_address_storage
   connect \sdram_inti_p0_bank \sdram_baddress_storage
-  connect \sdram_inti_p0_wrdata_en $and$ls180.v:1859$118_Y
-  connect \sdram_inti_p0_rddata_en $and$ls180.v:1860$119_Y
+  connect \sdram_inti_p0_wrdata_en $and$ls180.v:1844$86_Y
+  connect \sdram_inti_p0_rddata_en $and$ls180.v:1845$87_Y
   connect \sdram_inti_p0_wrdata \sdram_wrdata_storage
   connect \sdram_inti_p0_wrdata_mask 2'00
   connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid
@@ -272020,14 +271240,14 @@ module \ls180
   connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock
   connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready
   connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid
-  connect \sdram_timer_wait $not$ls180.v:1891$120_Y
+  connect \sdram_timer_wait $not$ls180.v:1876$88_Y
   connect \sdram_postponer_req_i \sdram_timer_done0
   connect \sdram_wants_refresh \sdram_postponer_req_o
-  connect \sdram_timer_done1 $eq$ls180.v:1894$121_Y
+  connect \sdram_timer_done1 $eq$ls180.v:1879$89_Y
   connect \sdram_timer_done0 \sdram_timer_done1
   connect \sdram_timer_count0 \sdram_timer_count1
-  connect \sdram_sequencer_start1 $or$ls180.v:1897$123_Y
-  connect \sdram_sequencer_done0 $and$ls180.v:1898$125_Y
+  connect \sdram_sequencer_start1 $or$ls180.v:1882$91_Y
+  connect \sdram_sequencer_done0 $and$ls180.v:1883$93_Y
   connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid
   connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
   connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we
@@ -272038,13 +271258,13 @@ module \ls180
   connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last
   connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
   connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
-  connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1940$127_Y
-  connect \sdram_bankmachine0_req_lock $or$ls180.v:1941$128_Y
-  connect \sdram_bankmachine0_row_hit $eq$ls180.v:1942$129_Y
+  connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1925$95_Y
+  connect \sdram_bankmachine0_req_lock $or$ls180.v:1926$96_Y
+  connect \sdram_bankmachine0_row_hit $eq$ls180.v:1927$97_Y
   connect \sdram_bankmachine0_cmd_payload_ba 2'00
-  connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1952$134_Y
-  connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1953$136_Y
-  connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1954$138_Y
+  connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1937$102_Y
+  connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1938$104_Y
+  connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1939$106_Y
   connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
   connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
@@ -272060,13 +271280,13 @@ module \ls180
   connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready
   connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
-  connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1986$146_Y
-  connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1987$147_Y
+  connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1971$114_Y
+  connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1972$115_Y
   connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume
   connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
-  connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1990$148_Y
-  connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1991$149_Y
-  connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1992$151_Y
+  connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1975$116_Y
+  connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1976$117_Y
+  connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1977$119_Y
   connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid
   connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
   connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we
@@ -272077,13 +271297,13 @@ module \ls180
   connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last
   connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
   connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
-  connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2097$157_Y
-  connect \sdram_bankmachine1_req_lock $or$ls180.v:2098$158_Y
-  connect \sdram_bankmachine1_row_hit $eq$ls180.v:2099$159_Y
+  connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2082$125_Y
+  connect \sdram_bankmachine1_req_lock $or$ls180.v:2083$126_Y
+  connect \sdram_bankmachine1_row_hit $eq$ls180.v:2084$127_Y
   connect \sdram_bankmachine1_cmd_payload_ba 2'01
-  connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2109$164_Y
-  connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2110$166_Y
-  connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2111$168_Y
+  connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2094$132_Y
+  connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2095$134_Y
+  connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2096$136_Y
   connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
   connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
@@ -272099,13 +271319,13 @@ module \ls180
   connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready
   connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
-  connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2143$176_Y
-  connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2144$177_Y
+  connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2128$144_Y
+  connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2129$145_Y
   connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume
   connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
-  connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2147$178_Y
-  connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2148$179_Y
-  connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2149$181_Y
+  connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2132$146_Y
+  connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2133$147_Y
+  connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2134$149_Y
   connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid
   connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
   connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we
@@ -272116,13 +271336,13 @@ module \ls180
   connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last
   connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
   connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
-  connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2254$187_Y
-  connect \sdram_bankmachine2_req_lock $or$ls180.v:2255$188_Y
-  connect \sdram_bankmachine2_row_hit $eq$ls180.v:2256$189_Y
+  connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2239$155_Y
+  connect \sdram_bankmachine2_req_lock $or$ls180.v:2240$156_Y
+  connect \sdram_bankmachine2_row_hit $eq$ls180.v:2241$157_Y
   connect \sdram_bankmachine2_cmd_payload_ba 2'10
-  connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2266$194_Y
-  connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2267$196_Y
-  connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2268$198_Y
+  connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2251$162_Y
+  connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2252$164_Y
+  connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2253$166_Y
   connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
   connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
@@ -272138,13 +271358,13 @@ module \ls180
   connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready
   connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
-  connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2300$206_Y
-  connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2301$207_Y
+  connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2285$174_Y
+  connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2286$175_Y
   connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume
   connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
-  connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2304$208_Y
-  connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2305$209_Y
-  connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2306$211_Y
+  connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2289$176_Y
+  connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2290$177_Y
+  connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2291$179_Y
   connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid
   connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
   connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we
@@ -272155,13 +271375,13 @@ module \ls180
   connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last
   connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
   connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
-  connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2411$217_Y
-  connect \sdram_bankmachine3_req_lock $or$ls180.v:2412$218_Y
-  connect \sdram_bankmachine3_row_hit $eq$ls180.v:2413$219_Y
+  connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2396$185_Y
+  connect \sdram_bankmachine3_req_lock $or$ls180.v:2397$186_Y
+  connect \sdram_bankmachine3_row_hit $eq$ls180.v:2398$187_Y
   connect \sdram_bankmachine3_cmd_payload_ba 2'11
-  connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2423$224_Y
-  connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2424$226_Y
-  connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2425$228_Y
+  connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2408$192_Y
+  connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2409$194_Y
+  connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2410$196_Y
   connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
   connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
   connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
@@ -272177,32 +271397,32 @@ module \ls180
   connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
   connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready
   connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
-  connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2457$236_Y
-  connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2458$237_Y
+  connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2442$204_Y
+  connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2443$205_Y
   connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume
   connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
-  connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2461$238_Y
-  connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2462$239_Y
-  connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2463$241_Y
+  connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2446$206_Y
+  connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2447$207_Y
+  connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2448$209_Y
   connect \sdram_choose_req_want_cmds 1'1
-  connect \sdram_trrdcon_valid $and$ls180.v:2559$252_Y
-  connect \sdram_tfawcon_valid $and$ls180.v:2560$258_Y
-  connect \sdram_ras_allowed $and$ls180.v:2561$259_Y
-  connect \sdram_tccdcon_valid $and$ls180.v:2562$262_Y
+  connect \sdram_trrdcon_valid $and$ls180.v:2544$220_Y
+  connect \sdram_tfawcon_valid $and$ls180.v:2545$226_Y
+  connect \sdram_ras_allowed $and$ls180.v:2546$227_Y
+  connect \sdram_tccdcon_valid $and$ls180.v:2547$230_Y
   connect \sdram_cas_allowed \sdram_tccdcon_ready
-  connect \sdram_twtrcon_valid $and$ls180.v:2564$264_Y
-  connect \sdram_read_available $or$ls180.v:2565$271_Y
-  connect \sdram_write_available $or$ls180.v:2566$278_Y
-  connect \sdram_max_time0 $eq$ls180.v:2567$279_Y
-  connect \sdram_max_time1 $eq$ls180.v:2568$280_Y
+  connect \sdram_twtrcon_valid $and$ls180.v:2549$232_Y
+  connect \sdram_read_available $or$ls180.v:2550$239_Y
+  connect \sdram_write_available $or$ls180.v:2551$246_Y
+  connect \sdram_max_time0 $eq$ls180.v:2552$247_Y
+  connect \sdram_max_time1 $eq$ls180.v:2553$248_Y
   connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid
   connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid
   connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid
   connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid
-  connect \sdram_go_to_refresh $and$ls180.v:2573$283_Y
+  connect \sdram_go_to_refresh $and$ls180.v:2558$251_Y
   connect \sdram_interface_rdata \sdram_dfi_p0_rddata
   connect \sdram_dfi_p0_wrdata \sdram_interface_wdata
-  connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2576$284_Y
+  connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2561$252_Y
   connect \sdram_choose_cmd_request \sdram_choose_cmd_valids
   connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0
   connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1
@@ -272210,7 +271430,7 @@ module \ls180
   connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3
   connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4
   connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5
-  connect \sdram_choose_cmd_ce $or$ls180.v:2609$342_Y
+  connect \sdram_choose_cmd_ce $or$ls180.v:2594$310_Y
   connect \sdram_choose_req_request \sdram_choose_req_valids
   connect \sdram_choose_req_cmd_valid \rhs_array_muxed6
   connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7
@@ -272218,31 +271438,31 @@ module \ls180
   connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9
   connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10
   connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11
-  connect \sdram_choose_req_ce $or$ls180.v:2678$428_Y
+  connect \sdram_choose_req_ce $or$ls180.v:2663$396_Y
   connect \sdram_dfi_p0_reset_n 1'1
   connect \sdram_dfi_p0_cke \sdram_steerer0
   connect \sdram_dfi_p0_odt \sdram_steerer1
-  connect \subfragments_roundrobin0_request $and$ls180.v:2755$460_Y
-  connect \subfragments_roundrobin0_ce $and$ls180.v:2756$463_Y
+  connect \subfragments_roundrobin0_request $and$ls180.v:2740$428_Y
+  connect \subfragments_roundrobin0_ce $and$ls180.v:2741$431_Y
   connect \sdram_interface_bank0_addr \rhs_array_muxed12
   connect \sdram_interface_bank0_we \rhs_array_muxed13
   connect \sdram_interface_bank0_valid \rhs_array_muxed14
-  connect \subfragments_roundrobin1_request $and$ls180.v:2760$476_Y
-  connect \subfragments_roundrobin1_ce $and$ls180.v:2761$479_Y
+  connect \subfragments_roundrobin1_request $and$ls180.v:2745$444_Y
+  connect \subfragments_roundrobin1_ce $and$ls180.v:2746$447_Y
   connect \sdram_interface_bank1_addr \rhs_array_muxed15
   connect \sdram_interface_bank1_we \rhs_array_muxed16
   connect \sdram_interface_bank1_valid \rhs_array_muxed17
-  connect \subfragments_roundrobin2_request $and$ls180.v:2765$492_Y
-  connect \subfragments_roundrobin2_ce $and$ls180.v:2766$495_Y
+  connect \subfragments_roundrobin2_request $and$ls180.v:2750$460_Y
+  connect \subfragments_roundrobin2_ce $and$ls180.v:2751$463_Y
   connect \sdram_interface_bank2_addr \rhs_array_muxed18
   connect \sdram_interface_bank2_we \rhs_array_muxed19
   connect \sdram_interface_bank2_valid \rhs_array_muxed20
-  connect \subfragments_roundrobin3_request $and$ls180.v:2770$508_Y
-  connect \subfragments_roundrobin3_ce $and$ls180.v:2771$511_Y
+  connect \subfragments_roundrobin3_request $and$ls180.v:2755$476_Y
+  connect \subfragments_roundrobin3_ce $and$ls180.v:2756$479_Y
   connect \sdram_interface_bank3_addr \rhs_array_muxed21
   connect \sdram_interface_bank3_we \rhs_array_muxed22
   connect \sdram_interface_bank3_valid \rhs_array_muxed23
-  connect \port_cmd_ready $or$ls180.v:2775$575_Y
+  connect \port_cmd_ready $or$ls180.v:2760$543_Y
   connect \port_wdata_ready \subfragments_new_master_wdata_ready
   connect \port_rdata_valid \subfragments_new_master_rdata_valid3
   connect \port_rdata_payload_data \sdram_interface_rdata
@@ -272250,22 +271470,22 @@ module \ls180
   connect \subfragments_roundrobin1_grant 1'0
   connect \subfragments_roundrobin2_grant 1'0
   connect \subfragments_roundrobin3_grant 1'0
-  connect \converter_reset $not$ls180.v:2797$577_Y
+  connect \converter_reset $not$ls180.v:2782$545_Y
   connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] }
-  connect \port_cmd_payload_addr $sub$ls180.v:2857$588_Y [23:0]
+  connect \port_cmd_payload_addr $sub$ls180.v:2842$556_Y [23:0]
   connect \port_cmd_payload_we \litedram_wb_we
   connect \port_wdata_payload_data \litedram_wb_dat_w
   connect \port_wdata_payload_we \litedram_wb_sel
   connect \litedram_wb_dat_r \port_rdata_payload_data
-  connect \port_flush $not$ls180.v:2862$589_Y
-  connect \port_cmd_last $not$ls180.v:2863$590_Y
-  connect \port_cmd_valid $and$ls180.v:2864$593_Y
-  connect \port_wdata_valid $and$ls180.v:2865$597_Y
-  connect \port_rdata_ready $and$ls180.v:2866$600_Y
-  connect \litedram_wb_ack $and$ls180.v:2867$605_Y
-  connect \ack_cmd $or$ls180.v:2868$607_Y
-  connect \ack_wdata $or$ls180.v:2869$609_Y
-  connect \ack_rdata $and$ls180.v:2870$610_Y
+  connect \port_flush $not$ls180.v:2847$557_Y
+  connect \port_cmd_last $not$ls180.v:2848$558_Y
+  connect \port_cmd_valid $and$ls180.v:2849$561_Y
+  connect \port_wdata_valid $and$ls180.v:2850$565_Y
+  connect \port_rdata_ready $and$ls180.v:2851$568_Y
+  connect \litedram_wb_ack $and$ls180.v:2852$573_Y
+  connect \ack_cmd $or$ls180.v:2853$575_Y
+  connect \ack_wdata $or$ls180.v:2854$577_Y
+  connect \ack_rdata $and$ls180.v:2855$578_Y
   connect \uart_sink_valid \uart_phy_source_valid
   connect \uart_phy_source_ready \uart_sink_ready
   connect \uart_sink_first \uart_phy_source_first
@@ -272278,25 +271498,25 @@ module \ls180
   connect \uart_phy_sink_payload_data \uart_source_payload_data
   connect \tx_fifo_sink_valid \rxtx_re
   connect \tx_fifo_sink_payload_data \rxtx_r
-  connect \txfull_status $not$ls180.v:2883$611_Y
-  connect \txempty_status $not$ls180.v:2884$612_Y
+  connect \txfull_status $not$ls180.v:2868$579_Y
+  connect \txempty_status $not$ls180.v:2869$580_Y
   connect \uart_source_valid \tx_fifo_source_valid
   connect \tx_fifo_source_ready \uart_source_ready
   connect \uart_source_first \tx_fifo_source_first
   connect \uart_source_last \tx_fifo_source_last
   connect \uart_source_payload_data \tx_fifo_source_payload_data
-  connect \tx_trigger $not$ls180.v:2890$613_Y
+  connect \tx_trigger $not$ls180.v:2875$581_Y
   connect \rx_fifo_sink_valid \uart_sink_valid
   connect \uart_sink_ready \rx_fifo_sink_ready
   connect \rx_fifo_sink_first \uart_sink_first
   connect \rx_fifo_sink_last \uart_sink_last
   connect \rx_fifo_sink_payload_data \uart_sink_payload_data
-  connect \rxempty_status $not$ls180.v:2896$614_Y
-  connect \rxfull_status $not$ls180.v:2897$615_Y
+  connect \rxempty_status $not$ls180.v:2881$582_Y
+  connect \rxfull_status $not$ls180.v:2882$583_Y
   connect \rxtx_w \rx_fifo_source_payload_data
-  connect \rx_fifo_source_ready $or$ls180.v:2899$617_Y
-  connect \rx_trigger $not$ls180.v:2900$618_Y
-  connect \irq $or$ls180.v:2923$627_Y
+  connect \rx_fifo_source_ready $or$ls180.v:2884$585_Y
+  connect \rx_trigger $not$ls180.v:2885$586_Y
+  connect \irq $or$ls180.v:2908$595_Y
   connect \tx_status \tx_trigger
   connect \rx_status \rx_trigger
   connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data }
@@ -272311,16 +271531,16 @@ module \ls180
   connect \tx_fifo_source_last \tx_fifo_fifo_out_last
   connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data
   connect \tx_fifo_re \tx_fifo_source_ready
-  connect \tx_fifo_syncfifo_re $and$ls180.v:2938$630_Y
-  connect \tx_fifo_level1 $add$ls180.v:2939$631_Y
+  connect \tx_fifo_syncfifo_re $and$ls180.v:2923$598_Y
+  connect \tx_fifo_level1 $add$ls180.v:2924$599_Y
   connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din
-  connect \tx_fifo_wrport_we $and$ls180.v:2949$635_Y
-  connect \tx_fifo_do_read $and$ls180.v:2950$636_Y
+  connect \tx_fifo_wrport_we $and$ls180.v:2934$603_Y
+  connect \tx_fifo_do_read $and$ls180.v:2935$604_Y
   connect \tx_fifo_rdport_adr \tx_fifo_consume
   connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r
   connect \tx_fifo_rdport_re \tx_fifo_do_read
-  connect \tx_fifo_syncfifo_writable $ne$ls180.v:2954$637_Y
-  connect \tx_fifo_syncfifo_readable $ne$ls180.v:2955$638_Y
+  connect \tx_fifo_syncfifo_writable $ne$ls180.v:2939$605_Y
+  connect \tx_fifo_syncfifo_readable $ne$ls180.v:2940$606_Y
   connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data }
   connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout
   connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable
@@ -272333,117 +271553,117 @@ module \ls180
   connect \rx_fifo_source_last \rx_fifo_fifo_out_last
   connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data
   connect \rx_fifo_re \rx_fifo_source_ready
-  connect \rx_fifo_syncfifo_re $and$ls180.v:2968$641_Y
-  connect \rx_fifo_level1 $add$ls180.v:2969$642_Y
+  connect \rx_fifo_syncfifo_re $and$ls180.v:2953$609_Y
+  connect \rx_fifo_level1 $add$ls180.v:2954$610_Y
   connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din
-  connect \rx_fifo_wrport_we $and$ls180.v:2979$646_Y
-  connect \rx_fifo_do_read $and$ls180.v:2980$647_Y
+  connect \rx_fifo_wrport_we $and$ls180.v:2964$614_Y
+  connect \rx_fifo_do_read $and$ls180.v:2965$615_Y
   connect \rx_fifo_rdport_adr \rx_fifo_consume
   connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r
   connect \rx_fifo_rdport_re \rx_fifo_do_read
-  connect \rx_fifo_syncfifo_writable $ne$ls180.v:2984$648_Y
-  connect \rx_fifo_syncfifo_readable $ne$ls180.v:2985$649_Y
+  connect \rx_fifo_syncfifo_writable $ne$ls180.v:2969$616_Y
+  connect \rx_fifo_syncfifo_readable $ne$ls180.v:2970$617_Y
   connect \libresocsim_libresoc_constraintmanager_i2c_scl \i2c_scl_1
   connect \libresocsim_libresoc_constraintmanager_i2c_sda_oe \i2c_oe
   connect \libresocsim_libresoc_constraintmanager_i2c_sda_o \i2c_sda0
   connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_i2c_sda_i
-  connect \libresocsim_shared_adr { 1'0 \rhs_array_muxed24 }
-  connect \libresocsim_shared_dat_w \rhs_array_muxed25 [31:0]
-  connect \libresocsim_shared_sel \rhs_array_muxed26 [3:0]
+  connect \libresocsim_shared_adr \rhs_array_muxed24
+  connect \libresocsim_shared_dat_w \rhs_array_muxed25
+  connect \libresocsim_shared_sel \rhs_array_muxed26
   connect \libresocsim_shared_cyc \rhs_array_muxed27
   connect \libresocsim_shared_stb \rhs_array_muxed28
   connect \libresocsim_shared_we \rhs_array_muxed29
   connect \libresocsim_shared_cti \rhs_array_muxed30
   connect \libresocsim_shared_bte \rhs_array_muxed31
-  connect \libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
-  connect \libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
-  connect \libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
-  connect \libresocsim_libresoc_ibus_ack $and$ls180.v:3098$659_Y
-  connect \libresocsim_libresoc_dbus_ack $and$ls180.v:3099$661_Y
-  connect \libresocsim_libresoc_jtag_wb_ack $and$ls180.v:3100$663_Y
-  connect \libresocsim_libresoc_ibus_err $and$ls180.v:3101$665_Y
-  connect \libresocsim_libresoc_dbus_err $and$ls180.v:3102$667_Y
-  connect \libresocsim_libresoc_jtag_wb_err $and$ls180.v:3103$669_Y
-  connect \libresocsim_request { \libresocsim_libresoc_jtag_wb_cyc \libresocsim_libresoc_dbus_cyc \libresocsim_libresoc_ibus_cyc }
+  connect \libresocsim_interface0_converted_interface_dat_r \libresocsim_shared_dat_r
+  connect \libresocsim_interface1_converted_interface_dat_r \libresocsim_shared_dat_r
+  connect \libresocsim_interface2_converted_interface_dat_r \libresocsim_shared_dat_r
+  connect \libresocsim_interface0_converted_interface_ack $and$ls180.v:3083$627_Y
+  connect \libresocsim_interface1_converted_interface_ack $and$ls180.v:3084$629_Y
+  connect \libresocsim_interface2_converted_interface_ack $and$ls180.v:3085$631_Y
+  connect \libresocsim_interface0_converted_interface_err $and$ls180.v:3086$633_Y
+  connect \libresocsim_interface1_converted_interface_err $and$ls180.v:3087$635_Y
+  connect \libresocsim_interface2_converted_interface_err $and$ls180.v:3088$637_Y
+  connect \libresocsim_request { \libresocsim_interface2_converted_interface_cyc \libresocsim_interface1_converted_interface_cyc \libresocsim_interface0_converted_interface_cyc }
   connect \libresocsim_ram_bus_adr \libresocsim_shared_adr
-  connect \libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \libresocsim_ram_bus_sel { 4'0000 \libresocsim_shared_sel }
+  connect \libresocsim_ram_bus_dat_w \libresocsim_shared_dat_w
+  connect \libresocsim_ram_bus_sel \libresocsim_shared_sel
   connect \libresocsim_ram_bus_stb \libresocsim_shared_stb
   connect \libresocsim_ram_bus_we \libresocsim_shared_we
   connect \libresocsim_ram_bus_cti \libresocsim_shared_cti
   connect \libresocsim_ram_bus_bte \libresocsim_shared_bte
   connect \ram_bus_ram_bus_adr \libresocsim_shared_adr
-  connect \ram_bus_ram_bus_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \ram_bus_ram_bus_sel { 4'0000 \libresocsim_shared_sel }
+  connect \ram_bus_ram_bus_dat_w \libresocsim_shared_dat_w
+  connect \ram_bus_ram_bus_sel \libresocsim_shared_sel
   connect \ram_bus_ram_bus_stb \libresocsim_shared_stb
   connect \ram_bus_ram_bus_we \libresocsim_shared_we
   connect \ram_bus_ram_bus_cti \libresocsim_shared_cti
   connect \ram_bus_ram_bus_bte \libresocsim_shared_bte
-  connect \interface0_converted_interface_adr \libresocsim_shared_adr
-  connect \interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \interface0_converted_interface_sel { 4'0000 \libresocsim_shared_sel }
-  connect \interface0_converted_interface_stb \libresocsim_shared_stb
-  connect \interface0_converted_interface_we \libresocsim_shared_we
-  connect \interface0_converted_interface_cti \libresocsim_shared_cti
-  connect \interface0_converted_interface_bte \libresocsim_shared_bte
-  connect \interface1_converted_interface_adr \libresocsim_shared_adr
-  connect \interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \interface1_converted_interface_sel { 4'0000 \libresocsim_shared_sel }
-  connect \interface1_converted_interface_stb \libresocsim_shared_stb
-  connect \interface1_converted_interface_we \libresocsim_shared_we
-  connect \interface1_converted_interface_cti \libresocsim_shared_cti
-  connect \interface1_converted_interface_bte \libresocsim_shared_bte
-  connect \socbushandler_converted_interface_adr \libresocsim_shared_adr
-  connect \socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \socbushandler_converted_interface_sel { 4'0000 \libresocsim_shared_sel }
-  connect \socbushandler_converted_interface_stb \libresocsim_shared_stb
-  connect \socbushandler_converted_interface_we \libresocsim_shared_we
-  connect \socbushandler_converted_interface_cti \libresocsim_shared_cti
-  connect \socbushandler_converted_interface_bte \libresocsim_shared_bte
-  connect \libresocsim_libresocsim_converted_interface_adr \libresocsim_shared_adr
-  connect \libresocsim_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
-  connect \libresocsim_libresocsim_converted_interface_sel { 4'0000 \libresocsim_shared_sel }
-  connect \libresocsim_libresocsim_converted_interface_stb \libresocsim_shared_stb
-  connect \libresocsim_libresocsim_converted_interface_we \libresocsim_shared_we
-  connect \libresocsim_libresocsim_converted_interface_cti \libresocsim_shared_cti
-  connect \libresocsim_libresocsim_converted_interface_bte \libresocsim_shared_bte
-  connect \libresocsim_ram_bus_cyc $and$ls180.v:3156$677_Y
-  connect \ram_bus_ram_bus_cyc $and$ls180.v:3157$678_Y
-  connect \interface0_converted_interface_cyc $and$ls180.v:3158$679_Y
-  connect \interface1_converted_interface_cyc $and$ls180.v:3159$680_Y
-  connect \socbushandler_converted_interface_cyc $and$ls180.v:3160$681_Y
-  connect \libresocsim_libresocsim_converted_interface_cyc $and$ls180.v:3161$682_Y
-  connect \libresocsim_shared_err $or$ls180.v:3162$687_Y
-  connect \libresocsim_wait $and$ls180.v:3163$690_Y
-  connect \libresocsim_done $eq$ls180.v:3176$708_Y
-  connect \libresocsim_csrbank0_sel $eq$ls180.v:3177$709_Y
+  connect \libresocsim_libresoc_xics_icp_adr \libresocsim_shared_adr
+  connect \libresocsim_libresoc_xics_icp_dat_w \libresocsim_shared_dat_w
+  connect \libresocsim_libresoc_xics_icp_sel \libresocsim_shared_sel
+  connect \libresocsim_libresoc_xics_icp_stb \libresocsim_shared_stb
+  connect \libresocsim_libresoc_xics_icp_we \libresocsim_shared_we
+  connect \libresocsim_libresoc_xics_icp_cti \libresocsim_shared_cti
+  connect \libresocsim_libresoc_xics_icp_bte \libresocsim_shared_bte
+  connect \libresocsim_libresoc_xics_ics_adr \libresocsim_shared_adr
+  connect \libresocsim_libresoc_xics_ics_dat_w \libresocsim_shared_dat_w
+  connect \libresocsim_libresoc_xics_ics_sel \libresocsim_shared_sel
+  connect \libresocsim_libresoc_xics_ics_stb \libresocsim_shared_stb
+  connect \libresocsim_libresoc_xics_ics_we \libresocsim_shared_we
+  connect \libresocsim_libresoc_xics_ics_cti \libresocsim_shared_cti
+  connect \libresocsim_libresoc_xics_ics_bte \libresocsim_shared_bte
+  connect \wb_sdram_adr \libresocsim_shared_adr
+  connect \wb_sdram_dat_w \libresocsim_shared_dat_w
+  connect \wb_sdram_sel \libresocsim_shared_sel
+  connect \wb_sdram_stb \libresocsim_shared_stb
+  connect \wb_sdram_we \libresocsim_shared_we
+  connect \wb_sdram_cti \libresocsim_shared_cti
+  connect \wb_sdram_bte \libresocsim_shared_bte
+  connect \libresocsim_libresocsim_wishbone_adr \libresocsim_shared_adr
+  connect \libresocsim_libresocsim_wishbone_dat_w \libresocsim_shared_dat_w
+  connect \libresocsim_libresocsim_wishbone_sel \libresocsim_shared_sel
+  connect \libresocsim_libresocsim_wishbone_stb \libresocsim_shared_stb
+  connect \libresocsim_libresocsim_wishbone_we \libresocsim_shared_we
+  connect \libresocsim_libresocsim_wishbone_cti \libresocsim_shared_cti
+  connect \libresocsim_libresocsim_wishbone_bte \libresocsim_shared_bte
+  connect \libresocsim_ram_bus_cyc $and$ls180.v:3141$645_Y
+  connect \ram_bus_ram_bus_cyc $and$ls180.v:3142$646_Y
+  connect \libresocsim_libresoc_xics_icp_cyc $and$ls180.v:3143$647_Y
+  connect \libresocsim_libresoc_xics_ics_cyc $and$ls180.v:3144$648_Y
+  connect \wb_sdram_cyc $and$ls180.v:3145$649_Y
+  connect \libresocsim_libresocsim_wishbone_cyc $and$ls180.v:3146$650_Y
+  connect \libresocsim_shared_err $or$ls180.v:3147$655_Y
+  connect \libresocsim_wait $and$ls180.v:3148$658_Y
+  connect \libresocsim_done $eq$ls180.v:3161$676_Y
+  connect \libresocsim_csrbank0_sel $eq$ls180.v:3162$677_Y
   connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3179$712_Y
-  connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3180$716_Y
+  connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3164$680_Y
+  connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3165$684_Y
   connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3182$719_Y
-  connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3183$723_Y
+  connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3167$687_Y
+  connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3168$691_Y
   connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3185$726_Y
-  connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3186$730_Y
+  connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3170$694_Y
+  connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3171$698_Y
   connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3188$733_Y
-  connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3189$737_Y
+  connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3173$701_Y
+  connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3174$705_Y
   connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3191$740_Y
-  connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3192$744_Y
+  connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3176$708_Y
+  connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3177$712_Y
   connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3194$747_Y
-  connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3195$751_Y
+  connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3179$715_Y
+  connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3180$719_Y
   connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3197$754_Y
-  connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3198$758_Y
+  connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3182$722_Y
+  connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3183$726_Y
   connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3200$761_Y
-  connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3201$765_Y
+  connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3185$729_Y
+  connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3186$733_Y
   connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w
-  connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3203$768_Y
-  connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3204$772_Y
+  connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3188$736_Y
+  connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3189$740_Y
   connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage
   connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24]
   connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16]
@@ -272454,41 +271674,41 @@ module \ls180
   connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8]
   connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0]
   connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we
-  connect \libresocsim_csrbank1_sel $eq$ls180.v:3215$773_Y
+  connect \libresocsim_csrbank1_sel $eq$ls180.v:3200$741_Y
   connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w
-  connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3217$776_Y
-  connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3218$780_Y
+  connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3202$744_Y
+  connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3203$748_Y
   connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w
-  connect \libresocsim_csrbank1_in_re $and$ls180.v:3220$783_Y
-  connect \libresocsim_csrbank1_in_we $and$ls180.v:3221$787_Y
+  connect \libresocsim_csrbank1_in_re $and$ls180.v:3205$751_Y
+  connect \libresocsim_csrbank1_in_we $and$ls180.v:3206$755_Y
   connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w
-  connect \libresocsim_csrbank1_out0_re $and$ls180.v:3223$790_Y
-  connect \libresocsim_csrbank1_out0_we $and$ls180.v:3224$794_Y
+  connect \libresocsim_csrbank1_out0_re $and$ls180.v:3208$758_Y
+  connect \libresocsim_csrbank1_out0_we $and$ls180.v:3209$762_Y
   connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage
   connect \libresocsim_csrbank1_in_w \gpio0_status
   connect \gpio0_we \libresocsim_csrbank1_in_we
   connect \libresocsim_csrbank1_out0_w \gpio0_out_storage
-  connect \libresocsim_csrbank2_sel $eq$ls180.v:3229$795_Y
+  connect \libresocsim_csrbank2_sel $eq$ls180.v:3214$763_Y
   connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w
-  connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3231$798_Y
-  connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3232$802_Y
+  connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3216$766_Y
+  connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3217$770_Y
   connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w
-  connect \libresocsim_csrbank2_in_re $and$ls180.v:3234$805_Y
-  connect \libresocsim_csrbank2_in_we $and$ls180.v:3235$809_Y
+  connect \libresocsim_csrbank2_in_re $and$ls180.v:3219$773_Y
+  connect \libresocsim_csrbank2_in_we $and$ls180.v:3220$777_Y
   connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w
-  connect \libresocsim_csrbank2_out0_re $and$ls180.v:3237$812_Y
-  connect \libresocsim_csrbank2_out0_we $and$ls180.v:3238$816_Y
+  connect \libresocsim_csrbank2_out0_re $and$ls180.v:3222$780_Y
+  connect \libresocsim_csrbank2_out0_we $and$ls180.v:3223$784_Y
   connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage
   connect \libresocsim_csrbank2_in_w \gpio1_status
   connect \gpio1_we \libresocsim_csrbank2_in_we
   connect \libresocsim_csrbank2_out0_w \gpio1_out_storage
-  connect \libresocsim_csrbank3_sel $eq$ls180.v:3243$817_Y
+  connect \libresocsim_csrbank3_sel $eq$ls180.v:3228$785_Y
   connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0]
-  connect \libresocsim_csrbank3_w0_re $and$ls180.v:3245$820_Y
-  connect \libresocsim_csrbank3_w0_we $and$ls180.v:3246$824_Y
+  connect \libresocsim_csrbank3_w0_re $and$ls180.v:3230$788_Y
+  connect \libresocsim_csrbank3_w0_we $and$ls180.v:3231$792_Y
   connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank3_r_re $and$ls180.v:3248$827_Y
-  connect \libresocsim_csrbank3_r_we $and$ls180.v:3249$831_Y
+  connect \libresocsim_csrbank3_r_re $and$ls180.v:3233$795_Y
+  connect \libresocsim_csrbank3_r_we $and$ls180.v:3234$799_Y
   connect \i2c_scl_1 \i2c_storage [0]
   connect \i2c_oe \i2c_storage [1]
   connect \i2c_sda0 \i2c_storage [2]
@@ -272496,37 +271716,37 @@ module \ls180
   connect \i2c_status \i2c_sda1
   connect \libresocsim_csrbank3_r_w \i2c_status
   connect \i2c_we \libresocsim_csrbank3_r_we
-  connect \libresocsim_csrbank4_sel $eq$ls180.v:3257$832_Y
+  connect \libresocsim_csrbank4_sel $eq$ls180.v:3242$800_Y
   connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0]
-  connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3259$835_Y
-  connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3260$839_Y
+  connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3244$803_Y
+  connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3245$807_Y
   connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0]
-  connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3262$842_Y
-  connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3263$846_Y
+  connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3247$810_Y
+  connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3248$814_Y
   connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0]
-  connect \sdram_command_issue_re $and$ls180.v:3265$849_Y
-  connect \sdram_command_issue_we $and$ls180.v:3266$853_Y
+  connect \sdram_command_issue_re $and$ls180.v:3250$817_Y
+  connect \sdram_command_issue_we $and$ls180.v:3251$821_Y
   connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0]
-  connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3268$856_Y
-  connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3269$860_Y
+  connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3253$824_Y
+  connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3254$828_Y
   connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w
-  connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3271$863_Y
-  connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3272$867_Y
+  connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3256$831_Y
+  connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3257$835_Y
   connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0]
-  connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3274$870_Y
-  connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3275$874_Y
+  connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3259$838_Y
+  connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3260$842_Y
   connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w
-  connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3277$877_Y
-  connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3278$881_Y
+  connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3262$845_Y
+  connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3263$849_Y
   connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w
-  connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3280$884_Y
-  connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3281$888_Y
+  connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3265$852_Y
+  connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3266$856_Y
   connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w
-  connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3283$891_Y
-  connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3284$895_Y
+  connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3268$859_Y
+  connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3269$863_Y
   connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w
-  connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3286$898_Y
-  connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3287$902_Y
+  connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3271$866_Y
+  connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3272$870_Y
   connect \sdram_sel \sdram_storage [0]
   connect \sdram_cke_1 \sdram_storage [1]
   connect \sdram_odt \sdram_storage [2]
@@ -272541,58 +271761,58 @@ module \ls180
   connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8]
   connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0]
   connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we
-  connect \libresocsim_csrbank5_sel $eq$ls180.v:3302$903_Y
+  connect \libresocsim_csrbank5_sel $eq$ls180.v:3287$871_Y
   connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_load3_re $and$ls180.v:3304$906_Y
-  connect \libresocsim_csrbank5_load3_we $and$ls180.v:3305$910_Y
+  connect \libresocsim_csrbank5_load3_re $and$ls180.v:3289$874_Y
+  connect \libresocsim_csrbank5_load3_we $and$ls180.v:3290$878_Y
   connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_load2_re $and$ls180.v:3307$913_Y
-  connect \libresocsim_csrbank5_load2_we $and$ls180.v:3308$917_Y
+  connect \libresocsim_csrbank5_load2_re $and$ls180.v:3292$881_Y
+  connect \libresocsim_csrbank5_load2_we $and$ls180.v:3293$885_Y
   connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_load1_re $and$ls180.v:3310$920_Y
-  connect \libresocsim_csrbank5_load1_we $and$ls180.v:3311$924_Y
+  connect \libresocsim_csrbank5_load1_re $and$ls180.v:3295$888_Y
+  connect \libresocsim_csrbank5_load1_we $and$ls180.v:3296$892_Y
   connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_load0_re $and$ls180.v:3313$927_Y
-  connect \libresocsim_csrbank5_load0_we $and$ls180.v:3314$931_Y
+  connect \libresocsim_csrbank5_load0_re $and$ls180.v:3298$895_Y
+  connect \libresocsim_csrbank5_load0_we $and$ls180.v:3299$899_Y
   connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3316$934_Y
-  connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3317$938_Y
+  connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3301$902_Y
+  connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3302$906_Y
   connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3319$941_Y
-  connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3320$945_Y
+  connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3304$909_Y
+  connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3305$913_Y
   connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3322$948_Y
-  connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3323$952_Y
+  connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3307$916_Y
+  connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3308$920_Y
   connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3325$955_Y
-  connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3326$959_Y
+  connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3310$923_Y
+  connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3311$927_Y
   connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank5_en0_re $and$ls180.v:3328$962_Y
-  connect \libresocsim_csrbank5_en0_we $and$ls180.v:3329$966_Y
+  connect \libresocsim_csrbank5_en0_re $and$ls180.v:3313$930_Y
+  connect \libresocsim_csrbank5_en0_we $and$ls180.v:3314$934_Y
   connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3331$969_Y
-  connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3332$973_Y
+  connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3316$937_Y
+  connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3317$941_Y
   connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_value3_re $and$ls180.v:3334$976_Y
-  connect \libresocsim_csrbank5_value3_we $and$ls180.v:3335$980_Y
+  connect \libresocsim_csrbank5_value3_re $and$ls180.v:3319$944_Y
+  connect \libresocsim_csrbank5_value3_we $and$ls180.v:3320$948_Y
   connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_value2_re $and$ls180.v:3337$983_Y
-  connect \libresocsim_csrbank5_value2_we $and$ls180.v:3338$987_Y
+  connect \libresocsim_csrbank5_value2_re $and$ls180.v:3322$951_Y
+  connect \libresocsim_csrbank5_value2_we $and$ls180.v:3323$955_Y
   connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_value1_re $and$ls180.v:3340$990_Y
-  connect \libresocsim_csrbank5_value1_we $and$ls180.v:3341$994_Y
+  connect \libresocsim_csrbank5_value1_re $and$ls180.v:3325$958_Y
+  connect \libresocsim_csrbank5_value1_we $and$ls180.v:3326$962_Y
   connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w
-  connect \libresocsim_csrbank5_value0_re $and$ls180.v:3343$997_Y
-  connect \libresocsim_csrbank5_value0_we $and$ls180.v:3344$1001_Y
+  connect \libresocsim_csrbank5_value0_re $and$ls180.v:3328$965_Y
+  connect \libresocsim_csrbank5_value0_we $and$ls180.v:3329$969_Y
   connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0]
-  connect \libresocsim_eventmanager_status_re $and$ls180.v:3346$1004_Y
-  connect \libresocsim_eventmanager_status_we $and$ls180.v:3347$1008_Y
+  connect \libresocsim_eventmanager_status_re $and$ls180.v:3331$972_Y
+  connect \libresocsim_eventmanager_status_we $and$ls180.v:3332$976_Y
   connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0]
-  connect \libresocsim_eventmanager_pending_re $and$ls180.v:3349$1011_Y
-  connect \libresocsim_eventmanager_pending_we $and$ls180.v:3350$1015_Y
+  connect \libresocsim_eventmanager_pending_re $and$ls180.v:3334$979_Y
+  connect \libresocsim_eventmanager_pending_we $and$ls180.v:3335$983_Y
   connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3352$1018_Y
-  connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3353$1022_Y
+  connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3337$986_Y
+  connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3338$990_Y
   connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24]
   connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16]
   connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8]
@@ -272609,31 +271829,31 @@ module \ls180
   connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0]
   connect \libresocsim_value_we \libresocsim_csrbank5_value0_we
   connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage
-  connect \libresocsim_csrbank6_sel $eq$ls180.v:3370$1023_Y
+  connect \libresocsim_csrbank6_sel $eq$ls180.v:3355$991_Y
   connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w
-  connect \rxtx_re $and$ls180.v:3372$1026_Y
-  connect \rxtx_we $and$ls180.v:3373$1030_Y
+  connect \rxtx_re $and$ls180.v:3357$994_Y
+  connect \rxtx_we $and$ls180.v:3358$998_Y
   connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3375$1033_Y
-  connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3376$1037_Y
+  connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3360$1001_Y
+  connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3361$1005_Y
   connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3378$1040_Y
-  connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3379$1044_Y
+  connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3363$1008_Y
+  connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3364$1012_Y
   connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0]
-  connect \eventmanager_status_re $and$ls180.v:3381$1047_Y
-  connect \eventmanager_status_we $and$ls180.v:3382$1051_Y
+  connect \eventmanager_status_re $and$ls180.v:3366$1015_Y
+  connect \eventmanager_status_we $and$ls180.v:3367$1019_Y
   connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0]
-  connect \eventmanager_pending_re $and$ls180.v:3384$1054_Y
-  connect \eventmanager_pending_we $and$ls180.v:3385$1058_Y
+  connect \eventmanager_pending_re $and$ls180.v:3369$1022_Y
+  connect \eventmanager_pending_we $and$ls180.v:3370$1026_Y
   connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0]
-  connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3387$1061_Y
-  connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3388$1065_Y
+  connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3372$1029_Y
+  connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3373$1033_Y
   connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3390$1068_Y
-  connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3391$1072_Y
+  connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3375$1036_Y
+  connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3376$1040_Y
   connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0]
-  connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3393$1075_Y
-  connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3394$1079_Y
+  connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3378$1043_Y
+  connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3379$1047_Y
   connect \libresocsim_csrbank6_txfull_w \txfull_status
   connect \txfull_we \libresocsim_csrbank6_txfull_we
   connect \libresocsim_csrbank6_rxempty_w \rxempty_status
@@ -272643,19 +271863,19 @@ module \ls180
   connect \txempty_we \libresocsim_csrbank6_txempty_we
   connect \libresocsim_csrbank6_rxfull_w \rxfull_status
   connect \rxfull_we \libresocsim_csrbank6_rxfull_we
-  connect \libresocsim_csrbank7_sel $eq$ls180.v:3404$1080_Y
+  connect \libresocsim_csrbank7_sel $eq$ls180.v:3389$1048_Y
   connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w
-  connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3406$1083_Y
-  connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3407$1087_Y
+  connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3391$1051_Y
+  connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3392$1055_Y
   connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w
-  connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3409$1090_Y
-  connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3410$1094_Y
+  connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3394$1058_Y
+  connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3395$1062_Y
   connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w
-  connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3412$1097_Y
-  connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3413$1101_Y
+  connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3397$1065_Y
+  connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3398$1069_Y
   connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w
-  connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3415$1104_Y
-  connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3416$1108_Y
+  connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3400$1072_Y
+  connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3401$1076_Y
   connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24]
   connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16]
   connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8]
@@ -272688,7 +271908,7 @@ module \ls180
   connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
   connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
   connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
-  connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3449$1115_Y
+  connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3434$1083_Y
   connect \sdrio_clk \sys_clk_1
   connect \sdrio_clk_1 \sys_clk_1
   connect \sdrio_clk_2 \sys_clk_1
@@ -272794,16 +272014,16 @@ module \ls180
   connect \sdrio_clk_101 \sys_clk_1
   connect \sdrio_clk_102 \sys_clk_1
   connect \sdrio_clk_103 \sys_clk_1
-  connect \libresocsim_dat_r $memrd$\mem$ls180.v:5530$1515_DATA
-  connect \ram_dat_r $memrd$\mem_1$ls180.v:5558$1565_DATA
+  connect \libresocsim_dat_r $memrd$\mem$ls180.v:5507$1459_DATA
+  connect \ram_dat_r $memrd$\mem_1$ls180.v:5527$1485_DATA
   connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
-  connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5576$1575_DATA
+  connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5545$1495_DATA
   connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
-  connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5590$1585_DATA
+  connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5559$1505_DATA
   connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
-  connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5604$1595_DATA
+  connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5573$1515_DATA
   connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
-  connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5618$1605_DATA
+  connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5587$1525_DATA
   connect \tx_fifo_wrport_dat_r \memdat_4
   connect \tx_fifo_rdport_dat_r \memdat_5
   connect \rx_fifo_wrport_dat_r \memdat_6
-- 
2.30.2