From 9374659426197d8d9a686332e2d8c82b124c6fff Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Tue, 24 Mar 2020 18:24:23 +0100 Subject: [PATCH] aco: validate register alignment of subdword operands and definitions MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Rhys Perry Reviewed-By: Timur Kristóf Part-of: --- src/amd/compiler/aco_validate.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 68e0c9caf8b..0fc80e68008 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -157,6 +157,12 @@ void validate(Program* program, FILE * output) } } + /* check subdword definitions */ + for (unsigned i = 0; i < instr->definitions.size(); i++) { + if (instr->definitions[i].regClass().is_subdword()) + check(instr->isSDWA() || instr->format == Format::PSEUDO, "Only SDWA and Pseudo instructions can write subdword registers", instr.get()); + } + if (instr->isSALU() || instr->isVALU()) { /* check literals */ Operand literal(s1); @@ -448,6 +454,8 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i); if (op.physReg() == vcc && !program->needs_vcc) err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i); + if (!(instr->isSDWA() || instr->format == Format::PSEUDO) && op.regClass().is_subdword() && op.physReg().byte()) + err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d must be aligned to a full register", i); if (!assignments[op.tempId()].firstloc.block) assignments[op.tempId()].firstloc = loc; if (!assignments[op.tempId()].defloc.block) -- 2.30.2