From 937cdd60698bef5e1d93f10fb9c866b78d49f2ed Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Fri, 30 Oct 2020 14:33:00 -0700 Subject: [PATCH] versa_ecp5.py add 4 arbitrarily assigned gpio pins to be used by Libre-SOC JTAG interface on ulx3s --- src/soc/litex/florent/versa_ecp5.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py index 1dfd049d..6bd917d8 100755 --- a/src/soc/litex/florent/versa_ecp5.py +++ b/src/soc/litex/florent/versa_ecp5.py @@ -85,6 +85,23 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC): device = "LFE5U-85F", **kwargs) + # get 4 arbitrarily assinged logical pins, each gpio has + # 2 distinct physical single non-differential pins p and n + gpio0 = self.platform.request("gpio", 0) + gpio1 = self.platform.request("gpio", 1) + + # assign p, n litex 'subsignals' of each gpio to jtag pins + jtag_tdi = gpio0.n + jtag_tms = gpio0.p + jtag_tck = gpio1.n + jtag_tdo = gpio1.p + + # wire the pins up to CPU JTAG + self.comb += self.cpu.jtag_tdi.eq(jtag_tdi) + self.comb += self.cpu.jtag_tms.eq(jtag_tms) + self.comb += self.cpu.jtag_tdi.eq(jtag_tdi) + self.comb += jtag_tdo.eq(self.cpu.jtag_tdo) + # Build # ---------------------------------------------------------------------------- -- 2.30.2