From 937f493a65ac2c00870c4dc61477c4fbaf27aba3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 17 Apr 2021 11:52:48 +0100 Subject: [PATCH] add chip conversion from ghdl to verilog --- ls180/post_pnr/Makefile | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/ls180/post_pnr/Makefile b/ls180/post_pnr/Makefile index c0a63c8..feeea4f 100644 --- a/ls180/post_pnr/Makefile +++ b/ls180/post_pnr/Makefile @@ -1,4 +1,4 @@ -.PHONY: all corona prepare cocotb gitupdate +.PHONY: all chip prepare cocotb gitupdate all: prepare cocotb @@ -16,8 +16,12 @@ cocotb: (cd cocotb && ./run_ghdl.sh) # builds just for fun (double-check) ghdl works -corona: +chip: ./vhd2obj.py - (cd obj && ghdl -e -g --std=08 corona) - (cd obj && ghdl -r -g --std=08 corona) + (cd obj && ghdl -e -g --std=08 chip) + (cd obj && ghdl -r -g --std=08 chip) +# imports all ghdl "stuff" and outputs verilog +chip_v: chip + (cd obj && yosys -m ghdl -p 'ghdl --std=08 chip' \ + -p 'proc' -p 'write_verilog chip.v') -- 2.30.2