From 9385881c995b8641607585a704f6e46bbe3993aa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 Mar 2019 10:12:34 +0000 Subject: [PATCH] add Makefile to generate Cam.v verilog --- TLB/src/Cam.py | 8 ++++++++ TLB/src/Makefile | 2 ++ 2 files changed, 10 insertions(+) create mode 100644 TLB/src/Makefile diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py index bea7ce54..62b5462a 100644 --- a/TLB/src/Cam.py +++ b/TLB/src/Cam.py @@ -1,6 +1,7 @@ from nmigen import Array, Module, Signal from nmigen.lib.coding import Encoder, Decoder from nmigen.compat.fhdl.structure import ClockDomain +from nmigen.cli import main #, verilog from CamEntry import CamEntry @@ -107,3 +108,10 @@ class Cam(): m.d.comb += self.data_hit.eq(0) return m + +if __name__ == '__main__': + cam = Cam(4, 4, 4) + main(cam, ports=[cam.command, cam.address, + cam.key_in, cam.data_in, + cam.data_hit, cam.data_out]) + diff --git a/TLB/src/Makefile b/TLB/src/Makefile new file mode 100644 index 00000000..1eb67acc --- /dev/null +++ b/TLB/src/Makefile @@ -0,0 +1,2 @@ +verilog: + python3 Cam.py generate -t v > Cam.v -- 2.30.2