From 939390091057f9163546d274e3dbeda1c94eed73 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 21:11:32 +0100 Subject: [PATCH] cleanup in litex core.py --- src/soc/litex/core.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py index 81d01089..f1fd3d81 100644 --- a/src/soc/litex/core.py +++ b/src/soc/litex/core.py @@ -9,13 +9,13 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat from litex import get_data_mod from litex.soc.interconnect import wishbone -from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +from litex.soc.cores.cpu import CPU CPU_VARIANTS = ["standard"] class LibreSOC(CPU): - name = "libre-soc" + name = "libre_soc" human_name = "Libre-SOC" variants = CPU_VARIANTS data_width = 64 @@ -135,8 +135,7 @@ class LibreSOC(CPU): def do_finalize(self): verilog_filename = os.path.join(self.platform.output_dir, "gateware", "libre-soc.v") - self.elaborate( - verilog_filename = verilog_filename) + self.elaborate(verilog_filename=verilog_filename) self.platform.add_source(verilog_filename) self.specials += Instance("test_issuer", **self.cpu_params) -- 2.30.2