From 939d3fdd8ce82f6fcf7ad0c56cd5a0e95fba987b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 7 Nov 2018 11:42:56 +0000 Subject: [PATCH] add mul elwidth redirection --- riscv/sv_insn_redirect.cc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index b06f270..1dcc3d4 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -580,7 +580,7 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_reg_t const & rhs) if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { sv_sreg_t result = lhs * rhs; fprintf(stderr, "mul result %lx %lx %lx\n", - (int64_t)lhs, (uint64_t)rhs, (uint64_t)result); + (int64_t)lhs, (uint64_t)rhs, (int64_t)result); return result; } int64_t result = vlhs * vrhs; @@ -589,7 +589,17 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_reg_t const & rhs) sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs) { - return lhs * rhs; + uint8_t bitwidth = _insn->src_bitwidth; + int64_t vlhs = 0; + int64_t vrhs = 0; + if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { + sv_sreg_t result = lhs * rhs; + fprintf(stderr, "mul result %lx %lx %lx\n", + (int64_t)lhs, (int64_t)rhs, (int64_t)result); + return result; + } + int64_t result = vlhs * vrhs; + return rv_int_op_finish(lhs, rhs, result, bitwidth); } /* 32-bit mulh/mulhu/mulhsu */ -- 2.30.2