From 939f091e7ed70c424c1f928c8cca5ae670dd1702 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Apr 2019 04:57:08 +0100 Subject: [PATCH] add TODO comment, bug #71, replace PLRU with LFSR --- TLB/src/SetAssociativeCache.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py index 20957b78..d2aa6f47 100644 --- a/TLB/src/SetAssociativeCache.py +++ b/TLB/src/SetAssociativeCache.py @@ -7,6 +7,10 @@ from nmigen.cli import main from nmigen.cli import verilog, rtlil from AddressEncoder import AddressEncoder + +# TODO: use a LFSR that advances continuously and picking the bottom +# few bits from it to select which cache line to replace, instead of PLRU +# http://bugs.libre-riscv.org/show_bug.cgi?id=71 from plru import PLRU SA_NA = "00" # no action (none) -- 2.30.2