From 93e84751a2151f3ae574a5da510ce669a60f38e7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 1 Sep 2021 13:58:54 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index d86dd398f..1ee9cac5d 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -218,7 +218,7 @@ cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv. ffirst LD/ST to multiple pages via a Vectorised base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore in these special circumstances requesting ffirst with a vector base is instead interpreted as element-strided LD/ST. See -# LOAD/STORE Elwidths +# LOAD/STORE Elwidths Loads and Stores are almost unique in that the OpenPOWER Scalar ISA provides a width for the operation (lb, lh, lw, ld). Only `extsb` and @@ -246,6 +246,17 @@ is treated effectively as completely separate and distinct from SV augmentation. This is primarily down to quirks surrounding LE/BE and byte-reversal in OpenPOWER. +It is unfortubately possible to request an elwidth override on the memory side which +does not mesh with the operation width: these result in `UNDEFINED` +behaviour. The reason is that the effect of attempting a 64-bit `sv.ld` +operation with a source elwidth override of 8/16/32 would result in +overlapping memory requests, particularly on unit and element strided +operations. Thus it is `UNDEFINED` when the elwidth is smaller than +the memory operation width. Examples include `sv.lw/sw=16/els` which +requests (overlapping) 4-byte memory reads offset from +each other at 2-byte intervals. Store likewise is also `UNDEFINED` +where the dest elwidth override is less than the operation width. + Note the following regarding the pseudocode to follow: * `scalar identity behaviour` SV Context parameter conditions turn this -- 2.30.2