From 940466db019768385f573611d5cb8416de74abad Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 13:23:13 +0100
Subject: [PATCH]

---
 openpower/sv/ldst.mdwn | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 511b3328c..f31122c35 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -109,7 +109,10 @@ Indexed LD is:
         if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
         if (RB.isvec) while (!(ps & 1<<k)) k++;
         if (RT.isvec) while (!(pd & 1<<j)) j++;
-        EA = ireg[RA+i] + ireg[RB+k] # indexed address
+        if svctx.ldstmode == elementstride:
+            EA = ireg[RA] + ireg[RB]*j   # register-strided
+        else
+            EA = ireg[RA+i] + ireg[RB+k] # indexed address
         if RAupdate: ireg[RAupdate+u] = EA
         ireg[RT+j] <= MEM[EA];
         if (!RT.isvec)
@@ -128,7 +131,7 @@ Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update" mode (`ldux
 A minor complication (caused by the retro-fitting of modern Vector
 features to a Scalar ISA) is that certain features do not exactly make
 sense or are considered a security risk.  Fail-first on Vector Indexed
-allows attackers to probe large numbers of pages from userspace, where
+would allow attackers to probe large numbers of pages from userspace, where
 strided fail-first (by creating contiguous sequential LDs) does not.
 
 In addition, reduce mode makes no sense, and for LD/ST with immediates
-- 
2.30.2