From 940baa5333f529f7a3461f5a1b510dbc1c231292 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Thu, 10 Jun 2021 11:17:20 +0200 Subject: [PATCH] Rebame root clock signal from "core.por_clk" into "core.pll_clk". --- experiments9/tsmc_c018/doDesign.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py index a48b14f..d4230f2 100644 --- a/experiments9/tsmc_c018/doDesign.py +++ b/experiments9/tsmc_c018/doDesign.py @@ -243,10 +243,7 @@ def scriptMain (**kw): ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO' ls180Conf.coreSize = (coreSizeX, coreSizeY) ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) ) - #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' ) - # XXX this is probably just por_clk not core.por_clk - # or, more likely, core.pllclk_clk - ls180Conf.useHTree( 'core.por_clk' ) + ls180Conf.useHTree( 'core.pll_clk' ) ls180Conf.useHTree( 'jtag_tck_from_pad' ) tiPath = 'test_issuer.ti.' -- 2.30.2