From 942b7c89fabab122da8f22a09877c213a60c4914 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 9 Jul 2020 17:21:19 -0700 Subject: [PATCH] format file --- src/soc/decoder/power_fieldsn.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py index 74fcd007..6f1b0bae 100644 --- a/src/soc/decoder/power_fieldsn.py +++ b/src/soc/decoder/power_fieldsn.py @@ -29,17 +29,16 @@ class SignalBitRange(BitRange): if stop < 0: stop = len(self) + stop + 1 for t in range(start, stop, step): - t = len(self) - 1 - t # invert field back + t = len(self) - 1 - t # invert field back k = OrderedDict.__getitem__(self, t) - res.append(self.signal[self._rev(k)]) # reverse-order here + res.append(self.signal[self._rev(k)]) # reverse-order here return Cat(*res) else: if subs < 0: subs = len(self) + subs - subs = len(self) - 1 - subs # invert field back + subs = len(self) - 1 - subs # invert field back k = OrderedDict.__getitem__(self, subs) - return self.signal[self._rev(k)] # reverse-order here - + return self.signal[self._rev(k)] # reverse-order here class SigDecode(Elaboratable): @@ -57,13 +56,14 @@ class SigDecode(Elaboratable): def ports(self): return [self.opcode_in] + def create_sigdecode(): s = SigDecode(32) return s + if __name__ == '__main__': sigdecode = create_sigdecode() vl = rtlil.convert(sigdecode, ports=sigdecode.ports()) with open("decoder.il", "w") as f: f.write(vl) - -- 2.30.2