From 9436eef70f511e53b1edd4e014fa8c91025b829d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 19:31:05 +0100 Subject: [PATCH] add extra args to ISA in branch test_pipe_caller --- src/soc/fu/branch/test/test_pipe_caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 99913dcb..199a5eba 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -181,7 +181,8 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, test.cr) + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr) initial_cia = 0x2000 simulator.set_pc(initial_cia) gen = program.generate_instructions() -- 2.30.2