From 943d9e55c15bee4419a3f6a47a980628059c0451 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 19:50:33 +0000 Subject: [PATCH] bit_length is 1 more than needed: subtract 1 from XLEN first --- src/soc/fu/shift_rot/main_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index df8b17c2..4f83a99d 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -49,7 +49,7 @@ class ShiftRotMainStage(PipeModBase): comb += bitwise_lut.inputs[1].eq(self.i.ra) comb += bitwise_lut.inputs[2].eq(self.i.rc) # 6 == log2(64) because we have 64-bit values - grev = GRev(log2_width=XLEN.bit_length()) + grev = GRev(log2_width=(XLEN-1).bit_length()) m.submodules.grev = grev with m.If(op.is_32bit): # 32-bit, so input is lower 32-bits zero-extended -- 2.30.2