From 94499950b4c3305c166c3aea0320050de53a302f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Jul 2022 23:09:06 +0100 Subject: [PATCH] --- openpower/sv/overview.mdwn | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index a6055f1d2..dd9d2846f 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -141,9 +141,7 @@ by SimpleV: (VSX Rijndael and SHA primitives; VSX shuffle and bitpermute operations) * register files above 128 entries * Vector lengths over 64 -* Unit-strided LD/ST and other comprehensive memory operations - (struct-based LD/ST from RVV for example) -* 32-bit instruction lengths. [[svp64]] had to be added as 64 bit. +* 32-bit instruction lengths. [[sv/svp64]] had to be added as 64 bit. These limitations, which stem inherently from the adaptation process of starting from a Scalar ISA, are not insurmountable. Over time, they may -- 2.30.2