From 9460e048ec782900c3199ebded0e57128c8216ac Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Apr 2020 15:08:48 +0200 Subject: [PATCH] tools/litex_sim: use similar analyzer configuration than wiki. --- litex/tools/litex_sim.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 7a526f83..987681d3 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -270,10 +270,19 @@ class SimSoC(SoCSDRAM): # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ - self.cpu.ibus, - self.cpu.dbus + self.cpu.ibus.stb, + self.cpu.ibus.cyc, + self.cpu.ibus.adr, + self.cpu.ibus.we, + self.cpu.ibus.ack, + self.cpu.ibus.sel, + self.cpu.ibus.dat_w, + self.cpu.ibus.dat_r, ] - self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + depth = 512, + clock_domain = "sys", + csr_csv = "analyzer.csv") self.add_csr("analyzer") # Build -------------------------------------------------------------------------------------------- -- 2.30.2