From 9485a47f9a677193b04a92bf593e1c83cf13f07d Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Wed, 29 Jul 2020 16:15:35 +0200 Subject: [PATCH] Match SoC granularity with decoder granularity --- gram/test/test_soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index d086b91..2a96b3d 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -25,7 +25,7 @@ class DDR3SoC(SoC, Elaboratable): self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8, features={"cti", "bte"}) - self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=32) + self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8) tck = 2/(2*2*100e6) nphases = 2 -- 2.30.2