From 9491aa84dc99b5372a03f601f5137b826ece8a39 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 May 2020 10:56:28 +0100 Subject: [PATCH] update comments on condition register --- src/soc/cr/main_stage.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py index dea936a6..b3b2b44f 100644 --- a/src/soc/cr/main_stage.py +++ b/src/soc/cr/main_stage.py @@ -1,6 +1,7 @@ # This stage is intended to do Condition Register instructions # and output, as well as carry and overflow generation. -# NOTE: we really should be doing the field decoding which +# NOTE: with the exception of mtcrf and mfcr, we really should be doing +# the field decoding which # selects which bits of CR are to be read / written, back in the # decoder / insn-isue, have both self.i.cr and self.o.cr # be broken down into 4-bit-wide "registers", with their -- 2.30.2