From 94965b8219508954a5fddd74e7c6de4503cd9931 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 30 Jul 2017 16:41:39 +0200 Subject: [PATCH] radeonsi: set up HTILE in descriptors only when level 0 is accessible MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Compression isn't enabled with non-zero levels. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 18b070ba3a2..b080562348c 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -432,7 +432,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, if (sscreen->b.chip_class <= VI) meta_va += base_level_info->dcc_offset; - } else if (tex->tc_compatible_htile) { + } else if (tex->tc_compatible_htile && first_level == 0) { meta_va = tex->resource.gpu_address + tex->htile_offset; } -- 2.30.2