From 94a681f41daedc3e841cc9559225e2231270701c Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 13 Apr 2023 05:43:12 +0100
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index be125bde4..a7e53d90d 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -196,6 +196,16 @@ for example), which
 will force implementations to perform divide and modulo
 calculations.
 
+An additional caveat involves Condition Register Fields
+when also used as Predicate Masks. An operation that
+overwrites the same CR Fields that are simultaneously
+being used as a Predicate Mask is `UNDEFINED` behaviour.
+This allows implementations to relax some of the
+otherwise-draconian Register Hazards that would otherwise
+occur, and to consider internal cacheing of the CR-based
+Predicate
+bits. 
+
 ## Register files, elements, and Element-width Overrides
 
 The relationship between register files, elements, and element-width
-- 
2.30.2