From 94b6f9f01a0878a4404ad2a7959abeb7709be977 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 3 Jul 2020 14:29:32 +0200 Subject: [PATCH] Fix autopep8 madness --- contrib/simulation | 2 ++ gram/dfii.py | 9 +++------ 2 files changed, 5 insertions(+), 6 deletions(-) create mode 100644 contrib/simulation diff --git a/contrib/simulation b/contrib/simulation new file mode 100644 index 0000000..83f1922 --- /dev/null +++ b/contrib/simulation @@ -0,0 +1,2 @@ +cd gram/simulation +time ./runsimcrg.sh \ No newline at end of file diff --git a/gram/dfii.py b/gram/dfii.py index 34d85bc..53053fe 100644 --- a/gram/dfii.py +++ b/gram/dfii.py @@ -61,12 +61,9 @@ class DFIInjector(Elaboratable): def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1): self._nranks = nranks - self._inti = dfi.Interface( - addressbits, bankbits, nranks, databits, nphases) - self.slave = dfi.Interface( - addressbits, bankbits, nranks, databits, nphases) - self.master = dfi.Interface( - addressbits, bankbits, nranks, databits, nphases) + self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) + self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) + self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) self._control = csr_bank.csr(4, "w") # sel, cke, odt, reset_n -- 2.30.2