From 94c80bf9470e8bd442c5daba2ed750c4d5c24bce Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 30 May 2023 01:00:59 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 3c94ca182..9298ed998 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -47,12 +47,7 @@ Table of contents Simple-V is a type of Vectorization best described as a "Prefix Loop Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and to the 8086 `REP`[^bib_rep] Prefix instruction. More advanced features are similar -to the Z80 `CPIR`[^bib_cpir] instruction. If naively viewed one-dimensionally as an -actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable -Vector instructions on the SFFS Subset and closer to 10 million 64-bit -True-Scalable Vector instructions if introduced on VSX. SVP64, the -instruction format used by Simple-V, is therefore best viewed as an -orthogonal RISC-paradigm "Loop Prefixing" subsystem instead. +to the Z80 `CPIR`[^bib_cpir] instruction. [^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir) [^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir) @@ -129,8 +124,11 @@ only 24 bits: Different classes of operations require different formats. The earlier sections cover the common formats and the five separate modes have their own section later: -CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store -Immediate, Load/Store Indexed, and Branch-Conditional. +* CR operations (crops), +* Arithmetic/Logical (termed "normal"), +* Load/Store Immediate, +* Load/Store Indexed, +* Branch-Conditional. ## Definition of Reserved in this spec. -- 2.30.2