From 94c8df0d6018db62979002d25faa21bfbf002eb1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 21:38:51 +0100 Subject: [PATCH] rename module, remove extraneous code and imports --- src/soc/fu/trap/main_stage.py | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index c29ac0a8..9141a30d 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -1,7 +1,6 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed) from nmutil.pipemodbase import PipeModBase -from nmutil.clz import CLZ from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData from soc.decoder.power_enums import InternalOp @@ -9,14 +8,7 @@ from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange -def array_of(count, bitwidth): - res = [] - for i in range(count): - res.append(Signal(bitwidth, reset_less=True)) - return res - - -class LogicalMainStage(PipeModBase): +class TrapMainStage(PipeModBase): def __init__(self, pspec): super().__init__(pspec, "main") self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn]) -- 2.30.2