From 94f687bd9ae37ece9391a3c42783c5768d26e81d Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 18 May 2020 17:25:39 +0200 Subject: [PATCH] i386: Improve vector mode and TFmode ABS and NEG patterns MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit gcc/ChangeLog: 2020-05-18 Uroš Bizjak * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): Do not emit FLAGS_REG clobber for TFmode. * config/i386/i386.md (*tf2_1): Rewrite as define_insn_and_split. Mark operands 1 and 2 commutative. (*nabstf2_1): Ditto. (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF. Do not swap memory operands. Simplify RTX generation. (neg abs SSE splitter): Ditto. * config/i386/sse.md (*2): Mark operands 1 and 2 commutative. Do not swap operands. Simplify RTX generation. (*nabs2): Ditto. --- gcc/ChangeLog | 14 ++++ gcc/config/i386/i386-expand.c | 6 +- gcc/config/i386/i386.md | 116 +++++++++++++++------------------- gcc/config/i386/sse.md | 56 ++++------------ 4 files changed, 80 insertions(+), 112 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 795507bc485..580b3cda64c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2020-05-18 Uroš Bizjak + + * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): + Do not emit FLAGS_REG clobber for TFmode. + * config/i386/i386.md (*tf2_1): Rewrite as + define_insn_and_split. Mark operands 1 and 2 commutative. + (*nabstf2_1): Ditto. + (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF. + Do not swap memory operands. Simplify RTX generation. + (neg abs SSE splitter): Ditto. + * config/i386/sse.md (*2): Mark operands 1 and 2 + commutative. Do not swap operands. Simplify RTX generation. + (*nabs2): Ditto. + 2020-05-18 Richard Biener * tree-vect-slp.c (vect_slp_bb): Start after labels. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 26531585c5f..2865cced66c 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -1716,9 +1716,7 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, machine_mode vmode = mode; rtvec par; - if (vector_mode) - use_sse = true; - else if (mode == TFmode) + if (vector_mode || mode == TFmode) use_sse = true; else if (TARGET_SSE_MATH) { @@ -1743,7 +1741,7 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, Create the appropriate mask now. */ mask = ix86_build_signbit_mask (vmode, vector_mode, code == ABS); use = gen_rtx_USE (VOIDmode, mask); - if (vector_mode) + if (vector_mode || mode == TFmode) par = gen_rtvec (2, set, use); else { diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9fd32f28bf3..aa4f25b7065 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10005,32 +10005,6 @@ [(set_attr "type" "negnot") (set_attr "mode" "")]) -(define_expand "tf2" - [(set (match_operand:TF 0 "register_operand") - (absneg:TF (match_operand:TF 1 "register_operand")))] - "TARGET_SSE" - "ix86_expand_fp_absneg_operator (, TFmode, operands); DONE;") - -(define_insn "*tf2_1" - [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") - (absneg:TF - (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m"))) - (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv")) - (clobber (reg:CC FLAGS_REG))] - "TARGET_SSE" - "#" - [(set_attr "isa" "noavx,noavx,avx,avx")]) - -(define_insn "*nabstf2_1" - [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") - (neg:TF - (abs:TF - (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m")))) - (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))] - "TARGET_SSE" - "#" - [(set_attr "isa" "noavx,noavx,avx,avx")]) - ;; Special expand pattern to handle integer mode abs (define_expand "abs2" @@ -10056,6 +10030,39 @@ DONE; }) +(define_expand "tf2" + [(set (match_operand:TF 0 "register_operand") + (absneg:TF (match_operand:TF 1 "register_operand")))] + "TARGET_SSE" + "ix86_expand_fp_absneg_operator (, TFmode, operands); DONE;") + +(define_insn_and_split "*tf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,Yv") + (absneg:TF + (match_operand:TF 1 "vector_operand" "%0,Yv"))) + (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (:TF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) + +(define_insn_and_split "*nabstf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,Yv") + (neg:TF + (abs:TF + (match_operand:TF 1 "vector_operand" "%0,Yv")))) + (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ior:TF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) + (define_expand "2" [(set (match_operand:X87MODEF 0 "register_operand") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] @@ -10108,36 +10115,24 @@ (symbol_ref "false"))))]) (define_split - [(set (match_operand:SSEMODEF 0 "sse_reg_operand") - (absneg:SSEMODEF - (match_operand:SSEMODEF 1 "vector_operand"))) + [(set (match_operand:MODEF 0 "sse_reg_operand") + (absneg:MODEF + (match_operand:MODEF 1 "vector_operand"))) (use (match_operand: 2 "vector_operand")) (clobber (reg:CC FLAGS_REG))] - "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || (TARGET_SSE && (mode == TFmode))) + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && reload_completed" - [(set (match_dup 0) (match_dup 3))] + [(set (match_dup 0) + (: (match_dup 1) (match_dup 2)))] { machine_mode mode = mode; machine_mode vmode = mode; - enum rtx_code absneg_op = == ABS ? AND : XOR; operands[0] = lowpart_subreg (vmode, operands[0], mode); operands[1] = lowpart_subreg (vmode, operands[1], mode); - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (absneg_op, vmode, operands[1], operands[2]); + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); }) (define_split @@ -10168,15 +10163,15 @@ [(set_attr "isa" "noavx,noavx,avx")]) (define_split - [(set (match_operand:SSEMODEF 0 "sse_reg_operand") - (neg:SSEMODEF - (abs:SSEMODEF - (match_operand:SSEMODEF 1 "vector_operand")))) + [(set (match_operand:MODEF 0 "sse_reg_operand") + (neg:MODEF + (abs:MODEF + (match_operand:MODEF 1 "vector_operand")))) (use (match_operand: 2 "vector_operand"))] - "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || (TARGET_SSE && (mode == TFmode))) + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && reload_completed" - [(set (match_dup 0) (match_dup 3))] + [(set (match_dup 0) + (ior: (match_dup 1) (match_dup 2)))] { machine_mode mode = mode; machine_mode vmode = mode; @@ -10184,19 +10179,8 @@ operands[0] = lowpart_subreg (vmode, operands[0], mode); operands[1] = lowpart_subreg (vmode, operands[1], mode); - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (IOR, vmode, operands[1], operands[2]); + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); }) ;; Conditionalize these after reload. If they match before reload, we diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 28d2c434caf..153982c9f12 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1638,59 +1638,31 @@ "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") (define_insn_and_split "*2" - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (absneg:VF - (match_operand:VF 1 "vector_operand" "0, xBm,v, m"))) - (use (match_operand:VF 2 "vector_operand" "xBm,0, vm,v"))] + (match_operand:VF 1 "vector_operand" "%0,v"))) + (use (match_operand:VF 2 "vector_operand" "xBm,vm"))] "TARGET_SSE" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 3))] -{ - enum rtx_code absneg_op = == ABS ? AND : XOR; - - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (absneg_op, mode, operands[1], operands[2]); -} - [(set_attr "isa" "noavx,noavx,avx,avx")]) + [(set (match_dup 0) + (:VF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) (define_insn_and_split "*nabs2" - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (neg:VF (abs:VF - (match_operand:VF 1 "vector_operand" "0,xBm,v,m")))) - (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] + (match_operand:VF 1 "vector_operand" "%0,v")))) + (use (match_operand:VF 2 "vector_operand" "xBm,vm"))] "TARGET_SSE" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 3))] -{ - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (IOR, mode, operands[1], operands[2]); -} - [(set_attr "isa" "noavx,noavx,avx,avx")]) + [(set (match_dup 0) + (ior:VF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) (define_expand "3" [(set (match_operand:VF 0 "register_operand") -- 2.30.2