From 9517ab3b6f92f8117a6f71ec008cbf5d328c0a08 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 13:59:29 +0100 Subject: [PATCH] clarify --- openpower/sv/rfc/ls001.mdwn | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index a45f523af..82c87a6a1 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -79,14 +79,13 @@ to be reserved. Power ISA is long-term stable. A catastrophic mistake has been made in ARM SVE/2 and RISC-V RVV: "Silicon-Partner" Scalability, marketed as a feature, allows the same instructions to mean different things on -different implementations (a different Vector bitwidth). +different implementations (a different Vector bitwidth). Binary interoperability is thus not only impossible to achieve but Illegal Instruction trap-and-emulate is also out of the question. Worse than that a **future** vendor may suddenly render -**all existing** hardware non-interoperable. It is the worst possible -thing for any specification to permit new vendors to damage earlier -implementations, yet this is what is permitted in SVE and RVV -*by design*. +**all existing** hardware non-interoperable, which is the worst possible +thing for any specification to permit +yet this is what SVE and RVV do *by design*. **Simple-V guarantees binary interoperability** by defining fixed register file bitwidths and size for all instructions. This does -- 2.30.2