From 9517b371ec67d36af11c2335b49a0d4024465331 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 16 Sep 2022 10:37:39 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index a66313b9d..d73e71f37 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -161,10 +161,9 @@ such large numbers of registers, even for Multi-Issue microarchitectures. # Simple-V Architectural Resources * No new Interrupt types are required. -* No modifications to existing Power ISA opcodes are required either. -* No new Register Files are required (because Simple-V is a category of - Zero-Overhead Looping on top of existing instructions and - existing registers, not an actual Vector ISA) + No modifications to existing Power ISA opcodes are required. + No new Register Files are required (all because Simple-V is a category of + Zero-Overhead Looping on Scalar instructions) * GPR FPR and CR Field Register extend to 128. A future version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx] * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO) -- 2.30.2