From 9517ec778cde46fee56fcaaef18019fbe61e9432 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 17:53:31 +0100 Subject: [PATCH] sigh - another instance where write-mask needed to mask out wr.rel --- src/soc/experiment/compalu_multi.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 350b4b82..baebed09 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -199,7 +199,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # is enough, when combined with when read-phase is done (rst_l.q) wr_any = Signal(reset_less=True) req_done = Signal(reset_less=True) - m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel.bool())) + m.d.comb += self.done_o.eq(self.busy_o & \ + ~((self.wr.rel & ~self.wrmask).bool())) m.d.comb += wr_any.eq(self.wr.go.bool()) m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \ ((req_l.q & self.wrmask) == 0)) -- 2.30.2