From 952ac7eed6b83222fba6d229deb1688e4bc32872 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 5 Oct 2019 07:56:14 +0100
Subject: [PATCH]

---
 simple_v_extension/vector_ops.mdwn | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn
index 4d93ab2ed..9d16c7593 100644
--- a/simple_v_extension/vector_ops.mdwn
+++ b/simple_v_extension/vector_ops.mdwn
@@ -317,3 +317,9 @@ Another is to overwrite one of the src registers.
 # Opcode Table
 
 TODO
+
+# Links
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002736.html>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002733.html>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=142>
-- 
2.30.2