From 955806950f1c5b737afa3936bef02937bca5b01b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 15 Dec 2020 18:52:11 -0800 Subject: [PATCH] add fields for 3R1W --- openpower/sv/svp_rewrite/svp64.mdwn | 31 +++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 0bba84923..5e650b113 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -38,15 +38,30 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant | MASK | `1:3` | Execution Mask | | ELWIDTH | `4:5` | Element Width | | SUBVL | `6:7` | Sub-vector length | -| Rdest_EXTRA | `8:10` | extra bits for Rdest | -| Rsrc1_EXTRA | `11:13` | extra bits for Rsrc1 | -| Rsrc2_EXTRA | `14:16` | extra bits for Rsrc2 | -| Rsrc3_EXTRA | `17:19` | extra bits for Rsrc3 | +| Rdest_EXTRA | `8:10` | extra bits for Rdest (Uses R\*_EXTRA Encoding) | +| Rsrc1_EXTRA | `11:13` | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding) | +| Rsrc2_EXTRA | `14:16` | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding) | +| Rsrc3_EXTRA | `17:19` | extra bits for Rsrc3 (Uses R\*_EXTRA Encoding) | | MASK_SRC | `14:16` | Execution Mask for Source (only on instructions with twin-predication) | | ELWIDTH_SRC | `17:18` | Element Width for Source (only on instructions with twin-predication) | | SUBVL_SRC | `19:20` | Sub-vector length for Source (only on instructions with twin-predication) | | TBD | `21:23` | TBD | +## R\*_EXTRA Encoding + +In the following table, `` denotes the value of the corresponding register field in the SVP64 suffix word. + +| R\*_EXTRA | Vector/Scalar
Mode | CR Register | Int/FP
Register | +|-----------|------------------------|---------------|---------------------| +| 000 | Scalar | `SVCR_000` | `SV[F]R_00` | +| 001 | Scalar | `SVCR_010` | `SV[F]R_01` | +| 010 | Scalar | `SVCR_100` | `SV[F]R_10` | +| 011 | Scalar | `SVCR_110` | `SV[F]R_11` | +| 100 | Vector | `SVCR_000` | `SV[F]R_00` | +| 101 | Vector | `SVCR_010` | `SV[F]R_01` | +| 110 | Vector | `SVCR_100` | `SV[F]R_10` | +| 111 | Vector | `SVCR_110` | `SV[F]R_11` | + ## ELWIDTH Encoding | Instruction Kind | ELWIDTH Value | Mnemonic | Description | @@ -171,7 +186,7 @@ There are two different encodings: single-predication (typically arithmetic oper # Register Naming -SV Registers are numbered using the notation `SV[F]R_` where `` is a decimal integer and `` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to ``. +SV Registers are numbered using the notation `SV[F|C]R_` where `` is a decimal integer and `` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to ``. For all `SV[F|C]R_` registers, the N is the upper bits in decimal and the M is the lower bits in binary, so `SVR5_01` is @@ -457,6 +472,6 @@ TBD Remapped Encoding Fields: -| | -|--| -| | +| `0` | `1:3` | `4:5` | `6:7` | `8:10` | `11:13` | `14:16` | `17:19` | `20:23` | +|-----------|-------|---------|-------|-------------|-------------|-------------|-------------|----------| +| MASK_KIND | MASK | ELWIDTH | SUBVL | Rdest_EXTRA | Rsrc1_EXTRA | Rsrc2_EXTRA | Rsrc3_EXTRA | Reserved | -- 2.30.2