From 95830c988a648e55042f4999f1f6a06e0879e533 Mon Sep 17 00:00:00 2001 From: Alex Coplan Date: Tue, 8 Sep 2020 14:13:45 +0100 Subject: [PATCH] aarch64: Add base support for Armv8-R This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set. --- bfd/ChangeLog | 7 +++++++ bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/cpu-aarch64.c | 6 +++++- gas/ChangeLog | 5 +++++ gas/config/tc-aarch64.c | 1 + gas/doc/c-aarch64.texi | 2 +- include/ChangeLog | 7 +++++++ include/opcode/aarch64.h | 8 +++++++- opcodes/ChangeLog | 8 ++++++++ opcodes/aarch64-dis.c | 33 +++++++++++++++++++++++++++++++++ 11 files changed, 76 insertions(+), 3 deletions(-) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 4faa8f23511..0ae5d3047c2 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2020-09-08 Alex Coplan + + * archures.c (bfd_mach_aarch64_8R): New. + * bfd-in2.h: Regenerate. + * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. + (bfd_aarch64_arch_ilp32): Update tail pointer. + 2020-09-08 Alan Modra PR 13250 diff --git a/bfd/archures.c b/bfd/archures.c index 969fa208739..50698648d6a 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -530,6 +530,7 @@ DESCRIPTION .#define bfd_mach_tilegx32 2 . bfd_arch_aarch64, {* AArch64. *} .#define bfd_mach_aarch64 0 +.#define bfd_mach_aarch64_8R 1 .#define bfd_mach_aarch64_ilp32 32 . bfd_arch_nios2, {* Nios II. *} .#define bfd_mach_nios2 0 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 3c85b073013..2202cab4393 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1930,6 +1930,7 @@ enum bfd_architecture #define bfd_mach_tilegx32 2 bfd_arch_aarch64, /* AArch64. */ #define bfd_mach_aarch64 0 +#define bfd_mach_aarch64_8R 1 #define bfd_mach_aarch64_ilp32 32 bfd_arch_nios2, /* Nios II. */ #define bfd_mach_nios2 0 diff --git a/bfd/cpu-aarch64.c b/bfd/cpu-aarch64.c index b3df3faad9e..8d9b420a425 100644 --- a/bfd/cpu-aarch64.c +++ b/bfd/cpu-aarch64.c @@ -107,8 +107,12 @@ scan (const struct bfd_arch_info *info, const char *string) "aarch64", PRINT, 4, DEFAULT, compatible, scan, \ bfd_arch_default_fill, NEXT, 0 } +static const bfd_arch_info_type bfd_aarch64_arch_v8_r = + N (bfd_mach_aarch64_8R, "aarch64:armv8-r", 64, FALSE, NULL); + static const bfd_arch_info_type bfd_aarch64_arch_ilp32 = - N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, NULL); + N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, + &bfd_aarch64_arch_v8_r); const bfd_arch_info_type bfd_aarch64_arch = N (0, "aarch64", 64, TRUE, &bfd_aarch64_arch_ilp32); diff --git a/gas/ChangeLog b/gas/ChangeLog index 117f7e00a0c..1c5929d90ab 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-09-08 Alex Coplan + + * config/tc-aarch64.c (aarch64_archs): Add armv8-r. + * doc/c-aarch64.texi: Document -march=armv8-r. + 2020-09-07 Mark Wielaard * dwarf2dbg.c (add_line_strp): New function. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index db5edcb3dc3..effa976980a 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8997,6 +8997,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = { {"armv8.4-a", AARCH64_ARCH_V8_4}, {"armv8.5-a", AARCH64_ARCH_V8_5}, {"armv8.6-a", AARCH64_ARCH_V8_6}, + {"armv8-r", AARCH64_ARCH_V8_R}, {NULL, AARCH64_ARCH_NONE} }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 86b6efc52bd..89725a7e2f8 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -100,7 +100,7 @@ issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: @code{armv8-a}, @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} -@code{armv8.5-a}, and @code{armv8.6-a}. +@code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}. If both @option{-mcpu} and @option{-march} are specified, the assembler will use the setting for @option{-mcpu}. If neither are diff --git a/include/ChangeLog b/include/ChangeLog index 62d88221a9c..10a3c7d4ca5 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2020-09-08 Alex Coplan + + * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. + (AARCH64_FEATURE_V8_R): New. + (AARCH64_ARCH_V8): Include new A-profile feature bit. + (AARCH64_ARCH_V8_R): New. + 2020-09-02 Alan Modra * opcode/v850.h (struct v850_operand ): Make param op an diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 5122ea85658..85f4fb5961e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -40,6 +40,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */ #define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */ #define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */ +#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */ #define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */ #define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */ #define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */ @@ -48,6 +49,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9) #define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ +#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ @@ -90,7 +92,8 @@ typedef uint32_t aarch64_insn; /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ - AARCH64_FEATURE_FP \ + AARCH64_FEATURE_V8_A \ + | AARCH64_FEATURE_FP \ | AARCH64_FEATURE_SIMD) #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ AARCH64_FEATURE_CRC \ @@ -125,6 +128,9 @@ typedef uint32_t aarch64_insn; AARCH64_FEATURE_V8_6 \ | AARCH64_FEATURE_BFLOAT16 \ | AARCH64_FEATURE_I8MM) +#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ + AARCH64_FEATURE_V8_R) \ + & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7740c888608..bbba2553020 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2020-09-08 Alex Coplan + + * aarch64-dis.c (arch_variant): New. + (determine_disassembling_preference): Disassemble according to + arch variant. + (select_aarch64_variant): New. + (print_insn_aarch64): Set feature set. + 2020-09-02 Alan Modra * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3), diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 326fabb7168..9d23b3154a2 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -35,6 +35,7 @@ enum map_type MAP_DATA }; +static aarch64_feature_set arch_variant; /* See select_aarch64_variant. */ static enum map_type last_type; static int last_mapping_sym = -1; static bfd_vma last_stop_offset = 0; @@ -2690,6 +2691,13 @@ determine_disassembling_preference (struct aarch64_inst *inst, DEBUG_TRACE ("skip %s as base opcode not match", alias->name); continue; } + + if (!AARCH64_CPU_HAS_FEATURE (arch_variant, *alias->avariant)) + { + DEBUG_TRACE ("skip %s: we're missing features", alias->name); + continue; + } + /* No need to do any complicated transformation on operands, if the alias opcode does not have any operand. */ if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value) @@ -3360,6 +3368,24 @@ get_sym_code_type (struct disassemble_info *info, int n, return FALSE; } +/* Set the feature bits in arch_variant in order to get the correct disassembly + for the chosen architecture variant. + + Currently we only restrict disassembly for Armv8-R and otherwise enable all + non-R-profile features. */ +static void +select_aarch64_variant (unsigned mach) +{ + switch (mach) + { + case bfd_mach_aarch64_8R: + arch_variant = AARCH64_ARCH_V8_R; + break; + default: + arch_variant = AARCH64_ANY & ~(AARCH64_FEATURE_V8_R); + } +} + /* Entry-point of the AArch64 disassembler. */ int @@ -3374,6 +3400,7 @@ print_insn_aarch64 (bfd_vma pc, unsigned int size = 4; unsigned long data; aarch64_operand_error errors; + static bfd_boolean set_features; if (info->disassembler_options) { @@ -3385,6 +3412,12 @@ print_insn_aarch64 (bfd_vma pc, info->disassembler_options = NULL; } + if (!set_features) + { + select_aarch64_variant (info->mach); + set_features = TRUE; + } + /* Aarch64 instructions are always little-endian */ info->endian_code = BFD_ENDIAN_LITTLE; -- 2.30.2