From 9591ba8f5edc0b352b9f24164f3257062c39d356 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 16:25:24 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 537543e5b..95ce2d867 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -610,9 +610,24 @@ the Coherent Memory accesses. This design is almost identical to the early Vector Processors of the late 1950s and early 1960s, which also critically relied on implicit auto-increment addressing. The barrel-architecture neatly -solves one of the inherent problems with those designs (memory +solves one of the inherent problems of those early designs ( a mismatch in memory speed) and the presence of a full register file caters for a second limitation of pure Memory-based Vector Processors: temporary -variables needed in the computation of intermediate results put +variables needed in the computation of intermediate results, which +also were put in memory, put an awfully high artificial load on Memory bandwidth. +The similarity to SVP64 should be clear: SVP64 Prefixing and the +associated REMAP system is just another form of register "tagging" +that augments what was formerly designated by its original authors +as "just a Scalar ISA", tagging allows for dramatic implicit alteration +with advanced behaviour not previously envisaged. + +What Snitch brings to the table therefore is a further illustration of +the concept introduced by Extra-V: where Extra-V brought information +about Sparse-Distributed Data to the attention of the main CPU in +a coherent fashion *without the CPU having to ask for it*, Snitch +demonstrates a classic LOAD-COMPUTE-STORE cycle in the same +distributed coherent manner. + + -- 2.30.2