From 959539fbbd1fc18fab85b23bb93e0716c170d010 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Wed, 26 Aug 2020 22:24:19 -0700 Subject: [PATCH] intel/isl: Drop unnecessary check on 16bpp depth format Drop unnecessary check which allows enabling of lossless write through compression (HiZ + CCS) for D16_UNORM format on Gen12+. We had misleading HSD information previously which used to claim that compression can not be supported for 16bpp format. Although BSpec does not have any restriction for D16_UNORM format. Signed-off-by: Sagar Ghuge Reviewed-by: Nanley Chery Acked-by: Jason Ekstrand Part-of: --- src/intel/isl/isl.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index e9731616bb1..8e3d408bd3b 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1972,20 +1972,6 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1) return false; - /* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if - * it has HiZ. If not for GEN:BUG:1406512483 "deprecate compression - * enable states", D16 would be supported. Supporting D16 requires being - * able to specify that the control surface is present and - * simultaneously disabling compression. The above bug makes it so that - * it's not possible to specify this configuration. - * - * Note: ISL Doesn't currently support depth CCS without HiZ at all. - */ - if (isl_surf_usage_is_depth(surf->usage) && - surf->format == ISL_FORMAT_R16_UNORM) { - return false; - } - /* On Gen12, 8BPP surfaces cannot be compressed if any level is not * 32Bx4row-aligned. For now, just reject the cases where alignment * matters. -- 2.30.2