From 95953d2928a66c426bd020d45a7ae9b8b2c83abd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 7 Aug 2019 08:36:04 +0200 Subject: [PATCH] platforms/default_clk_period: use 1e9/freq --- litex/boards/platforms/arty.py | 2 +- litex/boards/platforms/avalanche.py | 2 +- litex/boards/platforms/de0nano.py | 2 +- litex/boards/platforms/genesys2.py | 2 +- litex/boards/platforms/kc705.py | 2 +- litex/boards/platforms/kcu105.py | 2 +- litex/boards/platforms/machxo3.py | 2 +- litex/boards/platforms/minispartan6.py | 2 +- litex/boards/platforms/netv2.py | 2 +- litex/boards/platforms/nexys4ddr.py | 2 +- litex/boards/platforms/nexys_video.py | 2 +- litex/boards/platforms/tinyfpga_bx.py | 2 +- litex/boards/platforms/ulx3s.py | 2 +- litex/boards/platforms/versa_ecp3.py | 2 +- litex/boards/platforms/versa_ecp5.py | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 2e5af334..f79b2146 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -237,7 +237,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self, variant="a7-35"): device = { diff --git a/litex/boards/platforms/avalanche.py b/litex/boards/platforms/avalanche.py index a28fb440..c14b2a58 100644 --- a/litex/boards/platforms/avalanche.py +++ b/litex/boards/platforms/avalanche.py @@ -88,7 +88,7 @@ _io = [ class Platform(MicrosemiPlatform): default_clk_name = "clk50" - default_clk_period = 20.0 + default_clk_period = 1e9/50e6 def __init__(self): MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io) diff --git a/litex/boards/platforms/de0nano.py b/litex/boards/platforms/de0nano.py index 5328f614..ee0f5c5f 100644 --- a/litex/boards/platforms/de0nano.py +++ b/litex/boards/platforms/de0nano.py @@ -96,7 +96,7 @@ _io = [ class Platform(AlteraPlatform): default_clk_name = "clk50" - default_clk_period = 20 + default_clk_period = 1e9/50e6 def __init__(self): AlteraPlatform.__init__(self, "EP4CE22F17C6", _io) diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index a86fc486..675e50c4 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -110,7 +110,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk200" - default_clk_period = 5 + default_clk_period = 1e9/200e6 def __init__(self): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 54ea3e6c..8563938c 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -531,7 +531,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk156" - default_clk_period = 6.4 + default_clk_period = 1e9/156.5e6 def __init__(self): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 4cf6fb10..9ebe1473 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -486,7 +486,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk125" - default_clk_period = 8.0 + default_clk_period = 1e9/125e6 def __init__(self): XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado") diff --git a/litex/boards/platforms/machxo3.py b/litex/boards/platforms/machxo3.py index ec4d7346..edad3214 100644 --- a/litex/boards/platforms/machxo3.py +++ b/litex/boards/platforms/machxo3.py @@ -35,7 +35,7 @@ _io = [ class Platform(LatticePlatform): default_clk_name = "clk12" - default_clk_period = 83 + default_clk_period = 1e9/12e6 def __init__(self): LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io) diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py index c32b72ee..f8538ca2 100644 --- a/litex/boards/platforms/minispartan6.py +++ b/litex/boards/platforms/minispartan6.py @@ -115,7 +115,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk32" - default_clk_period = 31.25 + default_clk_period = 1e9/32e6 def __init__(self, device="xc6slx25"): XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py index f2b52c48..9a07b4fd 100644 --- a/litex/boards/platforms/netv2.py +++ b/litex/boards/platforms/netv2.py @@ -96,7 +96,7 @@ _io = [ class Platform(XilinxPlatform): default_clk_name = "clk50" - default_clk_period = 20.0 + default_clk_period = 1e9/50e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado") diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py index 3d0e7595..2c245b1b 100644 --- a/litex/boards/platforms/nexys4ddr.py +++ b/litex/boards/platforms/nexys4ddr.py @@ -105,7 +105,7 @@ _io = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado") diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index fd7bb357..4a58f54e 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -219,7 +219,7 @@ _connectors = [ class Platform(XilinxPlatform): default_clk_name = "clk100" - default_clk_period = 10.0 + default_clk_period = 1e9/100e6 def __init__(self): XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado") diff --git a/litex/boards/platforms/tinyfpga_bx.py b/litex/boards/platforms/tinyfpga_bx.py index 70ae8656..d01f784a 100644 --- a/litex/boards/platforms/tinyfpga_bx.py +++ b/litex/boards/platforms/tinyfpga_bx.py @@ -59,7 +59,7 @@ serial = [ class Platform(LatticePlatform): default_clk_name = "clk16" - default_clk_period = 62.5 + default_clk_period = 1e9/16e6 def __init__(self): LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm") diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py index 1d9e9641..d083a868 100644 --- a/litex/boards/platforms/ulx3s.py +++ b/litex/boards/platforms/ulx3s.py @@ -69,7 +69,7 @@ _io = [ class Platform(LatticePlatform): default_clk_name = "clk25" - default_clk_period = 40 + default_clk_period = 1e9/25e6 def __init__(self, device="LFE5U-45F", **kwargs): LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs) diff --git a/litex/boards/platforms/versa_ecp3.py b/litex/boards/platforms/versa_ecp3.py index 6013da60..907595e1 100644 --- a/litex/boards/platforms/versa_ecp3.py +++ b/litex/boards/platforms/versa_ecp3.py @@ -79,7 +79,7 @@ _io = [ class Platform(LatticePlatform): default_clk_name = "clk100" - default_clk_period = 10 + default_clk_period = 1e9/100e6 def __init__(self): LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io) diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index 0b27a657..7375895f 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -196,7 +196,7 @@ _connectors = [ class Platform(LatticePlatform): default_clk_name = "clk100" - default_clk_period = 10 + default_clk_period = 1e9/100e6 def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) -- 2.30.2