From 959a7d4ff9641229a3c96133164dfef0f3abf9e1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Nov 2021 12:29:53 +0000 Subject: [PATCH] remove some of the uses of wrmask (redundant) https://bugs.libre-soc.org/show_bug.cgi?id=742 in MultiCompUnit, wrmask is the amalgamation of the incoming "data ok" signals from an ALU. ALUs are given the *option* to write to registers: they are not told, "you absolutely have to write to this register" but of course for Hazard purposes, the MultiCompUnit has to be told to "hold" off the write until such time as the ALU can determine whether it has anything to write it _should_ now be possible for the ReservationStation version of FunctionUnit to use combinatorial-setting of write data+ok --- src/soc/experiment/compalu_multi.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 101f86cd..55655a74 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -215,11 +215,9 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # is enough, when combined with when read-phase is done (rst_l.q) wr_any = Signal(reset_less=True) req_done = Signal(reset_less=True) - m.d.comb += self.done_o.eq(self.busy_o & - ~((self.wr.rel_o & ~self.wrmask).bool())) + m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel_o).bool()) m.d.comb += wr_any.eq(self.wr.go_i.bool() | prev_wr_go.bool()) - m.d.comb += req_done.eq(wr_any & ~self.alu.n.i_ready & - ((req_l.q & self.wrmask) == 0)) + m.d.comb += req_done.eq(wr_any & ~self.alu.n.i_ready & (req_l.q == 0)) # argh, complicated hack: if there are no regs to write, # instead of waiting for regs that are never going to happen, # we indicate "done" when the ALU is "done" @@ -360,7 +358,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # write-release gated by busy and by shadow (and write-mask) brd = Repl(self.busy_o & self.shadown_i, self.n_dst) - m.d.comb += self.wr.rel_o.eq(req_l.q & brd & self.wrmask) + m.d.comb += self.wr.rel_o.eq(req_l.q & brd) # output the data from the latch on go_write for i in range(self.n_dst): -- 2.30.2