From 95a4dd92bec0f411a2e7b51be526a42d3397edf4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 28 Jun 2019 10:40:59 +0100 Subject: [PATCH] vl, mvl, subvl should all be 1 when returned from CSR_SV_STATE --- riscv/insns/mret.h | 1 + riscv/processor.cc | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 2e2e811..da60b16 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -8,4 +8,5 @@ s = set_field(s, MSTATUS_MPIE, 1); s = set_field(s, MSTATUS_MPP, PRV_U); p->set_privilege(prev_prv); p->set_csr(CSR_MSTATUS, s); +fprintf(stderr, "CSR SVSTATE: %x\n", svstate); p->set_csr(CSR_SV_STATE, svstate); diff --git a/riscv/processor.cc b/riscv/processor.cc index 583e4c9..fcfdb6d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -147,10 +147,11 @@ void state_t::reset(reg_t max_isa) msv.vl = msv.mvl = 0; ssv.vl = ssv.mvl = 0; usv.vl = usv.mvl = 0; - // SUBVL all 1 + // SUBVL all 1, including in xesvstate msv.subvl = 1; ssv.subvl = 1; usv.subvl = 1; + mesvstate = sesvstate = 0; #endif } @@ -901,10 +902,17 @@ reg_t processor_t::get_csr(int which) case CSR_SV_CFG: return (state.sv().state_bank) | (state.sv().state_size<<3); case CSR_SV_STATE: - return (state.sv().vl-1) | ((state.sv().mvl-1)<<6) | - (state.sv().srcoffs<<12) | (state.sv().destoffs<<18) | - ((state.sv().subvl-1)<<24) | - (state.sv().ssvoffs<<26) | (state.sv().dsvoffs<<28); + fprintf(stderr, "get CSR_SV_STATE vl %d mvl %d subvl %d\n", + state.sv().vl, + state.sv().mvl, + state.sv().subvl); + return ((std::max((int)state.sv().vl, 1))-1) | + ((std::max((int)state.sv().mvl, 1)-1)<<6) | + (state.sv().srcoffs<<12) | + (state.sv().destoffs<<18) | + ((std::max((int)state.sv().subvl, 1)-1)<<24) | + (state.sv().ssvoffs<<26) | + (state.sv().dsvoffs<<28); case CSR_SV_MVL: return state.sv().mvl; case CSR_SV_SUBVL: -- 2.30.2