From 95cfc444e60ea18fa0efef229582923b2e695631 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Mar 2015 11:26:10 +0200 Subject: [PATCH] migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method --- migen/fhdl/specials.py | 19 ++++++++++--------- migen/fhdl/verilog.py | 5 +++++ 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index f65beb7a..361f51a1 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -6,6 +6,15 @@ from migen.fhdl.tools import * from migen.fhdl.tracer import get_obj_var_name from migen.fhdl.verilog import _printexpr as verilog_printexpr +def _new_file(fdict, requested_filename, contents): + filename = requested_filename + i = 1 + while filename in fdict.keys(): + filename = requested_filename + str(i) + i += 1 + fdict[filename] = contents + return filename, fdict + class Special(HUID): def iter_expressions(self): for x in []: @@ -307,15 +316,7 @@ class Memory(Special): r += "\n" if memory.init is not None: - memory_filename = gn(memory) + ".init" - - # XXX move I/O to mibuild? - # (Implies mem init won't work with simple Migen examples?) - f = open(memory_filename, "w") - for d in memory.init: - f.write("{:x}\n".format(d)) - f.close() - + memory_filename, fdict = _new_file(fdict, gn(memory) + ".init", memory.init) r += "initial begin\n" r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n" r += "end\n\n" diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 499c74e3..f75dd9fb 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -315,6 +315,11 @@ class VerilogConvert: fdict = OrderedDict() src, fdict = _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns, fdict) r += src + for filename, contents in fdict.items(): + f = open(filename, "w") + for data in contents: + f.write("{:x}\n".format(data)) + f.close() r += "endmodule\n" return r -- 2.30.2