From 95d587a69d4ac03827ce8bb83f53c780fa56b92c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Feb 2022 13:55:15 +0000 Subject: [PATCH] add microwatt SYSCON peripheral at 0xc000_0000 this is for (Sys)tem (Con)figuration info --- src/ls2.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index 9482112..49fc731 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -24,6 +24,7 @@ from lambdasoc.soc.base import SoC from soc.bus.uart_16550 import UART16550 # opencores 16550 uart from soc.bus.external_core import ExternalCore # external libresoc/microwatt from soc.bus.wb_downconvert import WishboneDownConvert +from soc.bus.syscon import MicrowattSYSCON from gram.core import gramCore from gram.phy.ecp5ddrphy import ECP5DDRPHY @@ -90,9 +91,14 @@ class DDR3SoC(SoC, Elaboratable): self.bootmem.init = bios self._decoder.add(self.bootmem.bus, addr=fw_addr) # ROM at fw_addr + # System Configuration info + self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq, + has_uart=(uart_pins is not None)) + self._decoder.add(self.syscon.bus, addr=0xc000000) # at 0xc000_0000 + # SRAM (read-writeable BRAM) self.ram = SRAMPeripheral(size=4096) - self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_000 + self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000 # UART if uart_pins is not None: @@ -136,6 +142,7 @@ class DDR3SoC(SoC, Elaboratable): if hasattr(self, "bootmem"): m.submodules.bootmem = self.bootmem + m.submodules.syscon = self.syscon m.submodules.ram = self.ram m.submodules.uart = self.uart m.submodules.arbiter = self._arbiter -- 2.30.2